Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 13 and 15-26 are pending.
Response to Arguments
Applicant's arguments filed 1/06/2026 have been fully considered but they are not persuasive. Applicant argues that the idle/rest modes are not disclosed by the Fabien reference. The applicant’s specifications describe, on page 12 lines 20-29, that in the second operating mode, the processing occurs in different phases. An idle phase is a phase during which no computational output is called for. Section 2111 of the MPEP states that “The Patent and Trademark Office ("PTO") determines the scope of claims in patent applications not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction "in light of the specification as it would be interpreted by one of ordinary skill in the art."” Based on the specifications and the knowledge of a person ordinarily skilled in the art, a rest/idle mode would be a time/phase when no computational output is called for. A person ordinarily skilled in the art would conclude that, in the Fabien reference, the pipeline stages that are not actively performing signal processing would be in an idle/rest mode. While these stages await the next clock signal, no computational output is called for. Thus, it is maintained that the Fabien reference does teach the limitation of the pipeline stages being in an idle/rest mode.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13, 15-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fabien (US 20180004270 A1).
Regarding Claim 13: Fabien discloses an operating method for a data/signal evaluation system, in which a plurality of digital signal-processing processors is provided in a sequential pipeline for a data and/or signal evaluation (Fig. 4, pipeline 400, stages 302, 304 and 306, data values D0-D3; The use of input registers indicates that this is specifically digital data; [0044] “the clock controller 402 may generate all of the clock signals CLK0 to CLKN to have one or more in-phase edges, such that the pipeline stages operate synchronously with each other, or to spread each processing cycle over 2 or more clock phases, and up to N+1 clock phases”), the method comprising:
in a first operating mode, processing task that require a comparatively greater processing effort with a comparatively greater measure of processing power to be generated by the digital signal processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] and [0055] Teach synchronous operation of all the pipeline stages, providing greater processing power);
in a second operating mode, processing tasks that require a comparatively lower processing effort with a comparatively lower measure of power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] and [0055] Teach a mode where processors operate at different times thus providing lower processing power); wherein:
in the first operating mode, the digital-signal processing processors of the sequential pipeline are operated in parallel (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] “In the processing cycles C4 and C7 of FIG. 5B, the clock signals CLK0 to CLK3 all comprise the same high pulse P10 of the master clock, and thus all the pipeline stages operate synchronously”); and
in the second operating mode, at least one pair of the plurality of digital signal-processing processors of the sequential pipeline is operated in sequence (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] “the processing cycle of the pipeline is spread over four consecutive clock cycles of the master clock”),
wherein, in the second operating mode, a digital signal-processing processor of the pair to be operated subsequently is at least intermittently operated in an idle mode and/or is at least intermittently kept in a rest mode (Fig. 5B, processing cycle C5, where CLK0-CLK3 are operated sequentially. Before the clock signal is received, the processors can be considered at rest, and between each of the clock signals, there is a time frame where all of the processors are at rest), while a digital signal-processing processor of the pair to be operated in advance is operated in a normal manner in advance (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest) such that at least a portion of a time in which the processor operated in advance performs signal processing overlaps with a time in which the processor operated subsequently is in the idle mode or rest mode (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest. The time in which CLK3 operates overlaps with the rest time of CLK2 CLK1 and CLK0; [0053] the processing is spread over four consecutive clock cycles, so this means the processor operated in advance performs signal processing in a time that overlaps with the idle mode of the subsequent processors).
Regarding Claim 15: Fabien discloses the operating method as recited in claim 13. Fabien further discloses wherein, in the second operating mode, a digital signal-processing processor of the pair to be operated in advance is at least partly operated in an idle mode and/or is kept at least intermittently in a rest mode (Fig. 5B, processing cycle C5, where the processor corresponding to CLK3 is idle/at rest after the clock signal that contains pulse P11), while a digital signal-processing processor of the pair to be subsequently operated is subsequently operated in a normal manner (Fig. 5B, processing cycle C5, where processors corresponding to CLK0-CLK2 are sequentially activated).
Regarding Claim 16: Fabien discloses the operating method as recited in claim 13. Fabien further discloses wherein the digital signal-processing processor to be subsequently operated in the second operating mode processes data that were processed by the digital signal-processing processor to be operated in advance in the second operating mode ([0043] “the pipeline stages 302, 304 and 306 each receive a clock signal CLK0, CLK1 and CLK2 respectively”; Fig. 4, stage 302 outputs D1, which is operated first by CLK0 and input into stage 304, which is then sequentially operated by CLK1).
Regarding Claim 17: Fabien discloses the operating method as recited in claim 15. Fabien further discloses wherein the digital signal processing processor to be subsequently operated in the second operating mode processes data that were processed by the digital signal-processing processor to be operated in advance in the second operating mode ([0043] “the pipeline stages 302, 304 and 306 each receive a clock signal CLK0, CLK1 and CLK2 respectively”; Fig. 4, stage 302 outputs D1, which is operated first by CLK0 and input into stage 304, which is then sequentially operated by CLK1).
Regarding Claim 20: Fabien discloses the operating method as recited in claim 13. Fabien further discloses wherein an operating segment is started with the first operating mode, and/or an operation of the first operating mode is started when a first condition is satisfied (Fig. 5B, processing cycle C4 is the first cycle; [0051-0052]), and/or
during an operation, a switch is made to the second operating mode as soon as the first operating mode is or was ended (Fig. 5B, processing cycle C5 is immediately after C4; [0051] “the clock controller 402 is for example capable of dynamically modifying the clock phases of each pipeline stage from one processing cycle to the next”), and/or
during an operation, the first operating mode is ended when a second condition is satisfied (Fig. 5B, processing cycle C4 ends after a first master clock cycle elapses; [0052]), and/or
during an operation, the second operating mode is ended when a third condition is satisfied (Fig. 5B, processing cycle C5 ends after all the clock signals have elapsed; where the condition is stated in [0053]: “that the processing cycle of the pipeline is spread over four consecutive clock cycles of the master clock”), wherein:
the second condition is satisfied when a given first time span has elapsed since the start of the first operating mode (Fig. 5B, processing cycle C4 ends after a first master clock cycle elapses; [0052], where the first time span is equal to one master clock cycle), and/or
the third condition is satisfied when a given second time span has elapsed since the start of the second operating mode (Fig. 5B, processing cycle C5 ends after all the clock signals have elapsed, where the second time span is equal to the number of individual clock signals multiplied by the span of one master clock cycle; [0053]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fabien (US 20180004270 A1) in view of Sherburne (US 20060080566 A1).
Regarding Claim 18: Fabien discloses the operating method as recited in claim 13. Fabien does not disclose: wherein the digital signal-processing data processor to be operated subsequently in the second operating mode is coupled with the digital signal-processing processor to be operated in advance in the second operating mode via a FIFO memory for a buffered transmission of data of an output of the digital signal-processing processor to be operated in advance in the second operating mode, to an input of the digital signal-processing processor to be subsequently operated in the second operating mode.
However, Sherburne does teach a FIFO buffer which transmits data from a first processor in a pipeline to a second processor in a pipeline, similar to the one taught by Fabien (Fig. 2, processors 320 and 330, buffer 324; [0029] “A buffer 324 accepts data generated by the processor 320”; [0030] “The output of the buffer 324 is provided to a processor 330”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the operating method for a plurality of processors taught by Fabien with the FIFO buffer between processors taught by Sherburne. The reasoning for this is that by placing these buffers to receive and transmit data from between processors, it will avoid issues with stalling while transferrin this data and thus avoid excess power consumption (Sherburne, Paragraphs [0004] and [0005]).
Regarding Claim 19: Fabien discloses the operating method as recited in claim 15. Fabien does not disclose: wherein the digital signal-processing data processor to be operated subsequently in the second operating mode is coupled with the digital signal-processing processor to be operated in advance in the second operating mode via a FIFO memory for a buffered transmission of data of an output of the digital signal-processing processor to be operated in advance in the second operating mode, to an input of the digital signal-processing processor to be subsequently operated in the second operating mode.
However, Sherburne does teach a FIFO buffer which transmits data from a first processor in a pipeline to a second processor in a pipeline, similar to the one taught by Fabien (Fig. 2, processors 320 and 330, buffer 324; [0029] “A buffer 324 accepts data generated by the processor 320”; [0030] “The output of the buffer 324 is provided to a processor 330”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the operating method for a plurality of processors taught by Fabien with the FIFO buffer between processors taught by Sherburne. The reasoning for this is that by placing these buffers to receive and transmit data from between processors, it will avoid issues with stalling while transferrin this data and thus avoid excess power consumption (Sherburne, Paragraphs [0004] and [0005]).
Claims 21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Fabien (US 20180004270 A1) in view of Grinenval (US 20150105936 A1).
Regarding Claim 21: Fabien discloses the operating method as recited in claim 20. Fabien does not disclose: which is set up for operation of an ultrasonic operation assistance system or an ultrasonic driver-assistance system of a vehicle.
However, Grinenval teaches an ultrasonic operation assistance system or an ultrasonic driver-assistance system of a vehicle using two sequential processors, similar to those taught by Fabien (Figs. 1 and 5, vehicle guidance 1, vehicle movement control 2, interface 3, sensors 4, and processing units 5 and 7; [0023] “First processing unit 5 is connected to a second processing unit 7 of vehicle movement control 2 via interface 3. Second processing unit 7 is connected to actuators 9 of the vehicle via signal and control lines 8”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the operating method for a plurality of processors taught by Fabien by applying it to the ultrasonic driver-assistance system for a vehicle taught by Grinenval. The reasoning for this is that by applying the operating method taught by Fabien to the system taught by Grinenval, it will predictably yield the power management and security advantages taught by Fabien (Fabien, Paragraph [0005]) while maintaining the vehicle guidance capabilities taught by Grinenval which reliably account for vehicle surroundings (Grinenval, Paragraph [0005]).
Regarding Claim 23: Fabien discloses a control unit for a data/signal-evaluation system, the data/signal evaluation system including a plurality of digital signal-processing processors provided in a sequential pipeline for a data and/or signal evaluation (Fig. 4, pipeline 400, stages 302, 304 and 306, data values D0-D3; The use of input registers indicates that this is specifically digital data; [0044] “the clock controller 402 may generate all of the clock signals CLK0 to CLKN to have one or more in-phase edges, such that the pipeline stages operate synchronously with each other, or to spread each processing cycle over 2 or more clock phases, and up to N+1 clock phases”), the control unit configured to control the data/signal-evaluation system to:
in a first operating mode, process tasks that require a comparatively greater processing effort with a comparatively greater measure of processing power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] and [0055] Teach synchronous operation of all the pipeline stages, providing greater processing power); and
in a second operating mode, process tasks that require a comparatively lower processing effort with a comparatively lower measure of processing power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] and [0055] Teach a mode where processors operate at different times thus providing lower processing power); wherein:
in the first operating mode, the digital signal-processing processors of the sequential pipeline are operated in parallel (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] “In the processing cycles C4 and C7 of FIG. 5B, the clock signals CLK0 to CLK3 all comprise the same high pulse P10 of the master clock, and thus all the pipeline stages operate synchronously”); and
in the second operating mode, at least one pair of the plurality of signal-processing processors of the sequential pipeline is operated in sequence (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] “the processing cycle of the pipeline is spread over four consecutive clock cycles of the master clock”),
wherein, in the second operating mode, a digital signal-processing processor of the pair to be operated subsequently is at least intermittently operated in an idle mode and/or is at least intermittently kept in a rest mode (Fig. 5B, processing cycle C5, where CLK0-CLK3 are operated sequentially. Before the clock signal is received, the processors can be considered at rest, and between each of the clock signals, there is a time frame where all of the processors are at rest), while a digital signal-processing processor of the pair to be operated in advance is operated in a normal manner in advance such that at least a portion of a time in which the processor operated in advance performs signal processing overlaps with a time in which the processor operated subsequently is in the idle mode or rest mode (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest).
However, Fabien fails to disclose: a control unit for a data/signal-evaluation system in an ultrasonic operation assistance system.
However, Grinenval teaches an ultrasonic operation assistance system or an ultrasonic driver-assistance system of a vehicle using two sequential processors, similar to those taught by Fabien (Figs. 1 and 5, vehicle guidance 1, vehicle movement control 2, interface 3, sensors 4, and processing units 5 and 7; [0023] “First processing unit 5 is connected to a second processing unit 7 of vehicle movement control 2 via interface 3. Second processing unit 7 is connected to actuators 9 of the vehicle via signal and control lines 8”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the operating method for a plurality of processors taught by Fabien by applying it to the ultrasonic driver-assistance system for a vehicle taught by Grinenval. The reasoning for this is that by applying the operating method taught by Fabien to the system taught by Grinenval, it will predictably yield the power management and security advantages taught by Fabien (Fabien, Paragraph [0005]) while maintaining the vehicle guidance capabilities taught by Grinenval which reliably account for vehicle surroundings (Grinenval, Paragraph [0005]).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Fabien (US 20180004270 A1), in view of Grinenval (US 20150105936 A1), further in view of Davidson (US 4733355 A). Fabien, as modified by Grinenval, teaches the operating method as recited in claim 21.
This combination fails to teach: wherein: the first condition is satisfied when an ultrasonic transmit signal is emitted and/or when a predefined third time span has elapsed since an emission of an ultrasonic transmit signal, and/or the first time span for the second condition is a time span that is characteristic of a near field of an underlying working device, and/or the second time span for the third condition is a time span that is characteristic of a far field of the underlying working device after an emission of an ultrasonic transmit signal.
However, Davidson does teach a detection window for an ultrasound sensor, which would involve the activation of processors similar to what proceeds the first mode of operation taught by Fabien, occurs after a delay period following the transmission of a pulse into the environment (FIGS. 2 and 4, rangefinder 34, window detector circuit 38, window position adjustment circuit 40, and delay time period 60, Col 2 Ln 54-Col 3 Ln 3, Col 5 Ln 19-31, Col 6 Ln 20-35).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to further modify the operating method for a plurality of processors taught by Fabien, and previously modified by applying it to the ultrasonic driver-assistance system for a vehicle taught by Grinenval, with the delayed detection period taught by Davidson. The reasoning for this is that by applying a small delay time before detection occurs, and thus before the first operating mode of the processors is activated, it will predictably prevent any unimportant obstructions near the sensor, such as dirt or debris, from giving an erroneous distance measurement (Davidson, Col 2 Ln 54-Col 3 Ln 3).
Claims 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Grinenval (US 20150105936 A1) in view of Fabien (US 20180004270 A1).
Regarding Claim 24: Grinenval discloses a data/signal evaluation system in an ultrasonic operation assistance system, including a plurality of digital signal-processing processors provided in a sequential pipeline for a data and/or signal evaluation (Figs. 1 and 5, vehicle guidance 1, vehicle movement control 2, interface 3, sensors 4, and processing units 5 and 7; [0023] “First processing unit 5 is connected to a second processing unit 7 of vehicle movement control 2 via interface 3. Second processing unit 7 is connected to actuators 9 of the vehicle via signal and control lines 8”).
However, Grinenval does not disclose: the data/signal evaluation system configured to: in a first operating mode, process tasks that require a comparatively greater processing effort with a comparatively greater measure of processing power to be generated by the digital signal-processing processors; and in a second operating mode, process tasks that require a comparatively lower processing effort with a comparatively lower measure of processing power to be generated by the digital signal-processing processors; wherein: in the first operating mode, the digital signal-processing processors of the sequential pipeline are operated in parallel; and in the second operating mode, at least one pair of the plurality of digital signal-processing processors of the sequential pipeline is operated in sequence, wherein in the second operating mode, a digital signal-processing processor of the pair to be operated subsequently is at least intermittently operated in an idle mode and/or is at least intermittently kept in a rest mode, while a digital signal-processing processor of the pair to be operated in advance is operated in a normal manner in advance.
However, Fabien teaches: the data/signal evaluation system configured to:
in a first operating mode, process tasks that require a comparatively greater processing effort with a comparatively greater measure of processing power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] and [0055] Teach synchronous operation of all the pipeline stages, providing greater processing power); and
in a second operating mode, process tasks that require a comparatively lower processing effort with a comparatively lower measure of processing power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] and [0055] Teach a mode where processors operate at different times thus providing lower processing power); wherein:
in the first operating mode, the digital signal-processing processors of the sequential pipeline are operated in parallel (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] “In the processing cycles C4 and C7 of FIG. 5B, the clock signals CLK0 to CLK3 all comprise the same high pulse P10 of the master clock, and thus all the pipeline stages operate synchronously”);
and in the second operating mode, at least one pair of the plurality of digital signal-processing processors of the sequential pipeline is operated in sequence (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] “the processing cycle of the pipeline is spread over four consecutive clock cycles of the master clock”),
wherein, in the second operating mode, a digital signal-processing processor of the pair to be operated subsequently is at least intermittently operated in an idle mode and/or is at least intermittently kept in a rest mode (Fig. 5B, processing cycle C5, where CLK0-CLK3 are operated sequentially. Before the clock signal is received, the processors can be considered at rest, and between each of the clock signals, there is a time frame where all of the processors are at rest), while a digital signal-processing processor of the pair to be operated in advance is operated in a normal manner in advance (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest) such that at least a portion of a time in which the processor operated in advance performs signal processing overlaps with a time in which the processor operated subsequently is in the idle mode or rest mode (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest. The time in which CLK3 operates overlaps with the rest time of CLK2 CLK1 and CLK0; [0053] the processing is spread over four consecutive clock cycles, so this means the processor operated in advance performs signal processing in a time that overlaps with the idle mode of the subsequent processors).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the data/signal evaluation system in an ultrasonic operation assistance system taught by Grinenval, with the processor operating method taught by Fabien. The reasoning for this is that the method taught by Fabien provides a means of managing the power utilized by the processors (Fabien, Paragraph [0005]). Thus, by utilizing this method, the user or designer will predictably be able to better manage the power used by this system and thus enhance overall efficiency.
Regarding Claim 25: Grinenval discloses an ultrasonic operation assistance system, comprising: a plurality of digital signal-processing processors provided in a sequential pipeline for a data and/or signal evaluation (Figs. 1 and 5, vehicle guidance 1, vehicle movement control 2, interface 3, sensors 4, and processing units 5 and 7; [0023] “First processing unit 5 is connected to a second processing unit 7 of vehicle movement control 2 via interface 3. Second processing unit 7 is connected to actuators 9 of the vehicle via signal and control lines 8”).
However, Grinenval does not disclose: the data/signal evaluation system configured to: in a first operating mode, process tasks that require a comparatively greater processing effort with a comparatively greater measure of processing power to be generated by the digital signal-processing processors; and in a second operating mode, process tasks that require a comparatively lower processing effort with a comparatively lower measure of processing power to be generated by the digital signal-processing processors; wherein: in the first operating mode, the digital signal-processing processors of the sequential pipeline are operated in parallel; and in the second operating mode, at least one pair of the plurality of digital signal-processing processors of the sequential pipeline is operated in sequence, wherein in the second operating mode, a digital signal-processing processor of the pair to be operated subsequently is at least intermittently operated in an idle mode and/or is at least intermittently kept in a rest mode, while a digital signal-processing processor of the pair to be operated in advance is operated in a normal manner in advance.
However, Fabien teaches: the data/signal evaluation system configured to:
in a first operating mode, process tasks that require a comparatively greater processing effort with a comparatively greater measure of processing power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] and [0055] Teach synchronous operation of all the pipeline stages, providing greater processing power); and
in a second operating mode, process tasks that require a comparatively lower processing effort with a comparatively lower measure of processing power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] and [0055] Teach a mode where processors operate at different times thus providing lower processing power); wherein:
in the first operating mode, the digital signal-processing processors of the sequential pipeline are operated in parallel (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] “In the processing cycles C4 and C7 of FIG. 5B, the clock signals CLK0 to CLK3 all comprise the same high pulse P10 of the master clock, and thus all the pipeline stages operate synchronously”);
and in the second operating mode, at least one pair of the plurality of digital signal-processing processors of the sequential pipeline is operated in sequence (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] “the processing cycle of the pipeline is spread over four consecutive clock cycles of the master clock”),
wherein, in the second operating mode, a digital signal-processing processor of the pair to be operated subsequently is at least intermittently operated in an idle mode and/or is at least intermittently kept in a rest mode (Fig. 5B, processing cycle C5, where CLK0-CLK3 are operated sequentially. Before the clock signal is received, the processors can be considered at rest, and between each of the clock signals, there is a time frame where all of the processors are at rest), while a digital signal-processing processor of the pair to be operated in advance is operated in a normal manner in advance (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest) such that at least a portion of a time in which the processor operated in advance performs signal processing overlaps with a time in which the processor operated subsequently is in the idle mode or rest mode (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest. The time in which CLK3 operates overlaps with the rest time of CLK2 CLK1 and CLK0; [0053] the processing is spread over four consecutive clock cycles, so this means the processor operated in advance performs signal processing in a time that overlaps with the idle mode of the subsequent processors).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the data/signal evaluation system in an ultrasonic operation assistance system taught by Grinenval, with the processor operating method taught by Fabien. The reasoning for this is that the method taught by Fabien provides a means of managing the power utilized by the processors (Fabien, Paragraph [0005]). Thus, by utilizing this method, the user or designer will predictably be able to better manage the power used by this system and thus enhance overall efficiency.
Regarding Claim 26: Grinenval discloses a vehicle, comprising: an operating unit with a drive, which is developed with an ultrasonic operation assistance system for the control of the operating unit (Figs. 1 and 5, vehicle guidance 1, vehicle movement control 2, interface 3, sensors 4, and processing units 5 and 7, Paragraphs [0020-0023] and [0032]. System includes a memory which contains instructions for the processors of the operating unit.), the ultrasonic operation assistance system including:
a plurality of digital signal-processing processors provided in a sequential pipeline for a data and/or signal evaluation (Figs. 1 and 5, vehicle guidance 1, vehicle movement control 2, interface 3, sensors 4, and processing units 5 and 7, Paragraphs [0020-0023] and [0035]. Data passes from processing unit 5 to 7 in a sequential order).
Grinenval fails to teach the digital signal- processing processors configured to: in a first operating mode, process tasks that require a comparatively greater processing effort with a comparatively greater measure of processing power to be generated by the digital signal-processing processors; and in a second operating mode, process tasks that require a comparatively lower processing effort with a comparatively lower measure of processing power to be generated by the digital signal-processing processors; wherein: in the first operating mode, the digital signal-processing processors of the sequential pipeline are operated in parallel; and in the second operating mode, at least one pair of the plurality of digital signal-processing processors of the sequential pipeline is operated in sequence, wherein, in the second operating mode, a digital signal-processing processor of the pair to be operated subsequently is at least intermittently operated in an idle mode and/or is at least intermittently kept in a rest mode, while a digital signal-processing processor of the pair to be operated in advance is operated in a normal manner in advance such that hat least a portion of a time in which the processor operated in advance performs signal processing overlaps with a time in which the processor operated subsequently is in the idle mode or rest mode.
However, Fabien does teach: in a first operating mode, process tasks that require a comparatively greater processing effort with a comparatively greater measure of processing power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] and [0055] Teach synchronous operation of all the pipeline stages, providing greater processing power); and
in a second operating mode, process tasks that require a comparatively lower processing effort with a comparatively lower measure of processing power to be generated by the digital signal-processing processors (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] and [0055] Teach a mode where processors operate at different times thus providing lower processing power); wherein:
in the first operating mode, the digital signal-processing processors of the sequential pipeline are operated in parallel (Fig. 4, stages 302-306 and Fig. 5B, processing cycles C4 and C7; [0052] “In the processing cycles C4 and C7 of FIG. 5B, the clock signals CLK0 to CLK3 all comprise the same high pulse P10 of the master clock, and thus all the pipeline stages operate synchronously”);
and in the second operating mode, at least one pair of the plurality of digital signal-processing processors of the sequential pipeline is operated in sequence (Fig. 4, stages 302-306 and Fig. 5B, processing cycle C5; [0053] “the processing cycle of the pipeline is spread over four consecutive clock cycles of the master clock”),
wherein in the second operating mode, a digital signal-processing processor of the pair to be operated subsequently is at least intermittently operated in an idle mode and/or is at least intermittently kept in a rest mode (Fig. 5B, processing cycle C5, where CLK0-CLK3 are operated sequentially. Before the clock signal is received, the processors can be considered at rest, and between each of the clock signals, there is a time frame where all of the processors are at rest), while a digital signal-processing processor of the pair to be operated in advance is operated in a normal manner in advance (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest) such that at least a portion of a time in which the processor operated in advance performs signal processing overlaps with a time in which the processor operated subsequently is in the idle mode or rest mode (Fig. 5B, processing cycle C5, where CLK3 comprises high pulse P11, operating while the other signal processors are at rest. The time in which CLK3 operates overlaps with the rest time of CLK2 CLK1 and CLK0; [0053] the processing is spread over four consecutive clock cycles, so this means the processor operated in advance performs signal processing in a time that overlaps with the idle mode of the subsequent processors).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the vehicle taught by Grinenval, with the processor operating method taught by Fabien. The reasoning for this is that the method taught by Fabien provides a means of managing the power utilized by the processors (Fabien, Paragraph [0092]). Thus, by utilizing this method, the user or designer will predictably be able to better manage the power used by this system and thus enhance overall efficiency.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISABELLE LIN BOEGHOLM whose telephone number is (571)270-0570. The examiner can normally be reached Monday-Thursday 7:30am-5pm, Fridays 8am-12pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yuqing Xiao can be reached at (571) 270-3603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ISABELLE LIN BOEGHOLM/Examiner, Art Unit 3645
/YUQING XIAO/Supervisory Patent Examiner, Art Unit 3645