Prosecution Insights
Last updated: April 19, 2026
Application No. 17/272,283

METHOD OF MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE, AND DISPLAY DEVICE

Non-Final OA §103
Filed
Aug 21, 2023
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allow Rate
651 granted / 914 resolved
+3.2% vs TC avg
Strong +19% interview lift
Without
With
+19.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
73 currently pending
Career history
987
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
48.7%
+8.7% vs TC avg
§102
30.5%
-9.5% vs TC avg
§112
17.5%
-22.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 914 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant elects Species I, which is associated with claims 1-13 and 17-20 is acknowledged. Claims 14-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/14/2025 is acknowledged. In response, a PCT restriction is a shown below. REQUIREMENT FOR UNITY OF INVENTION As provided in 37 CFR 1.475( a), a national stage application shall relate to one invention only or to a group of inventions so linked as to form a single general inventive concept (“requirement of unity of invention”). Where a group of inventions is claimed in a national stage application, the requirement of unity of invention shall be fulfilled only when there is a technical relationship among those inventions involving one or more of the same or corresponding special technical features. The expression “special technical features” shall mean those technical features that define a contribution which each of the claimed inventions, considered as a whole, makes over the prior art. The determination whether a group of inventions is so linked as to form a single general inventive concept shall be made without regard to whether the inventions are claimed in separate claims or as alternatives within a single claim. See 37 CFR 1.475(e). When Claims Are Directed to Multiple Categories of Inventions: As provided in 37 CFR 1.475 (b), a national stage application containing claims to different categories of invention will be considered to have unity of invention if the claims are drawn only to one of the following combinations of categories: (1) A product and a process specially adapted for the manufacture of said product; or (2) A product and process of use of said product; or (3) A product, a process specially adapted for the manufacture of the said product, and a use of the said product; or (4) A process and an apparatus or means specifically designed for carrying out the said process; or (5) A product, a process specially adapted for the manufacture of the said product, and an apparatus or means specifically designed for carrying out the said process. Otherwise, unity of invention might not be present. See 37 CFR 1.475 (c). Restriction is required under 35 U.S.C. 121 and 372. This application contains the following inventions or groups of inventions which are not so linked as to form a single general inventive concept under PCT Rule 13.1. This application contains claims directed to more than one species of the generic invention. These species are deemed to lack unity of invention because they are not so linked as to form a single general inventive concept under PCT Rule 13.1. The species are as follows: Species 1 – figs. 2a-2g; Species 2 – fig. 3a-3g. The special technical features as claimed do not provide a contribution over the prior art as shown below: PNG media_image1.png 729 606 media_image1.png Greyscale PNG media_image2.png 361 593 media_image2.png Greyscale Applicant is required, in reply to this action, to elect a single species to which the claims shall be restricted if no generic claim is finally held to be allowable. The reply must also identify the claims readable on the elected species, including any claims subsequently added. An argument that a claim is allowable or that all claims are generic is considered non-responsive unless accompanied by an election. Upon the allowance of a generic claim, applicant will be entitled to consideration of claims to additional species which are written in dependent form or otherwise require all the limitations of an allowed generic claim. Currently, the following claim(s) are generic: claims 29-42, and 54-55. The inventions listed as Groups I and II do not relate to a single general inventive concept under PCT Rule 13.1 because, under PCT Rule 13.2, they lack the same or corresponding special technical features for the following reasons: The special technical features as claimed do not provide a contribution over the prior art. Applicant is advised that the reply to this requirement to be complete must include (i) an election of a species or invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention. The election of an invention or species may be made with or without traverse. To preserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable on the elected invention or species. Should applicant traverse on the ground that the inventions have unity of invention (37 CFR 1.475(a)), applicant must provide reasons in support thereof. Applicant may submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. Where such evidence or admission is provided by applicant, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103(a) of the other invention. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 6-7, 9-13 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over SAOTOME et al. 20160267873 in view of CN103184408A Beijing Huaxia Yimaibaibai Network Technology Co ltd, ETC (hereinafter CN103184408A). PNG media_image3.png 220 349 media_image3.png Greyscale Regarding claim 1, SAOTOME discloses a method of manufacturing an array substrate, comprising: a step of providing a substrate 21 (fig. 3B); a step of preparing a driving circuit layer on the substrate (TFT on 21 – fig. 3B); a step of preparing a first passivation layer 27a on the driving circuit layer; a step of preparing a second passivation layer 27b on the first passivation layer 27a. SAOTOME does not disclose of a step of preparing an original metal layer on the first passivation layer; a step of preparing an oxygen source layer on the original metal layer; a step of heat-treating the oxygen source layer and the original metal layer, wherein the original metal layer is oxidized to form a second passivation layer, and the oxygen source layer is deoxidized to form a deoxidation layer; and a step of removing the deoxidation layer. However, CN103184408A discloses a method for heat treatment of a metal layer and discloses the following (see paragraphs 13-39 of the specification): providing a substrate, the surface of which is formed with a metal layer (i.c. Original metal layer), the metal layer may also be aluminum; heat treating the substrate: providing a powdered metal peroxide (i.e., oxygen source layer) for heat treatment; metal peroxides react with water vapor and carbon dioxide in the vacuum heat treating furnace to release reactive oxygen atoms to oxidize the metal of the substrate surface to metal oxide (i.e., heat treating the oxygen source layer and the original metal layer, which is oxidized). The substrate is removed and rinsed under a water gun until the pH of the surface of the metal oxide layer is neutral to remove reactants remaining on the surface of the metal oxide layer after heat treatment. In view of such teaching, it would have been obvious to form a method of SAOTOME comprising a step of preparing an original metal layer on the first passivation layer; a step of preparing an oxygen source layer on the original metal layer; a step of heat-treating the oxygen source layer and the original metal layer, wherein the original metal layer is oxidized to form a second passivation layer, and the oxygen source layer is deoxidized to form a deoxidation layer; and a step of removing the deoxidation layer such as taught by CN103184408A in order to use prior art knowledge to form a second a passivation layer to save research cost of new knowledge. PNG media_image4.png 581 771 media_image4.png Greyscale Regarding claim 6, CN103184408A discloses wherein the step of heat-treating the oxygen source layer and the original metal layer, wherein the original metal layer is oxidized to form the second passivation layer, and the oxygen source layer is deoxidized to form the deoxidation layer (carbon dioxide layer), includes: performing heat treatment on the oxygen source layer and the original metal layer over a preset duration at a preset temperature; the original metal layer is oxidized to form the second passivation layer; and the oxygen source layer is deoxidized to form the deoxidation layer. PNG media_image5.png 214 768 media_image5.png Greyscale Regarding claim 7, CN103184408A discloses wherein a temperature value of the preset temperature ranges from 200 degrees centigrade to 500 degrees centigrade, and a time value of the preset duration ranges from 1 minute to 300 minutes. Regarding claim 9, CN103184408A discloses wherein a material for preparing the original metal layer includes aluminum. Regarding claim 10, it would have been obvious to form a method comprising wherein a material for preparing the oxygen source layer includes molybdenum oxide and/or indium zinc oxide as these are prior art known material. Regarding claim 11, SAOTOME and CN103184408A disclose claim 1. Fig. 3B of SAOTOME wherein the step of preparing the driving circuit layer on the substrate includes: a step of preparing a gate on the substrate; a step of preparing a gate insulating layer covering the gate; a step of preparing an active layer on the gate insulating layer; and a step of preparing a source and a drain on two opposite ends of the active layer on the gate insulating layer, wherein the source and the drain are electrically connected to the active layer, respectively. Regarding claim 12, it would have been obvious to form a method comprising wherein the step of preparing the gate on the substrate includes: depositing a metal conductive layer on the substrate through a physical deposition process; and patterning the metal conductive layer to form the gate through a photomask etching process as this convention metal in the art. Regarding claim 13, it would have been obvious to form a method comprising wherein the step of preparing the source and the drain on the two opposite ends of the active layer on the gate insulating layer includes: depositing a metal conductive layer on the gate insulating layer through a physical deposition process; and patterning the metal conductive layer to form the source and the drain through a photomask etching process as this is conventional in the art. Regarding claim 18, the resulting structure of SAOTOME and CN103184408A is an array substrate, wherein the array substrate is provided by the method of manufacturing the array substrate of claim 1. Regarding claim 19, the resulting structure of SAOTOME and CN103184408A would have been a display device, wherein the display device comprises the array substrate according to claim 18. Claims 8 and 20 is rejected under 35 U.S.C. 103 as being unpatentable over SAOTOME and CN103184408A in view of Ju 20210134197. Regarding claim 20, SAOTOME and CN103184408A disclose claim 19, but do not disclose wherein the array substrate comprises the first passivation layer and the second passivation layer disposed on the driving circuit layer, the first passivation layer comprises silicon oxide, and the second passivation layer includes aluminum oxide. However, par [0118] of Ju discloses that of a first passivation layer PAS1, and a second passivation layer PAS2 which may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide. As such it would have been obvious to form a device of SAOTOME and CN103184408A comprising wherein the array substrate comprises the first passivation layer and the second passivation layer disposed on the driving circuit layer, the first passivation layer comprises silicon oxide, and the second passivation layer includes aluminum oxide such as taught by Ju in order to use prior art material to save cost. PNG media_image6.png 412 496 media_image6.png Greyscale Regarding claim 8, SAOTOME and CN103184408A discloses claim 1, but do not disclose wherein after the step of removing the deoxidation layer, the method further includes: forming a via hole on the first passivation layer and the second passivation layer, so that drain is exposed through the via hole; and forming a pixel electrode layer on the second passivation layer, wherein the pixel electrode layer is electrically connected to the drain through the via hole. However, fig. 7 of Ju discloses forming a via hole on the first passivation layer VIA1 and the second passivation layer VIA2, so that drain is exposed through the via hole; and forming a pixel electrode layer on the second passivation layer, wherein the pixel electrode layer is electrically connected to the drain through the via hole. In view of such teaching, it would have been obvious to form a method of SAOTOME and CN103184408A wherein after the step of removing the deoxidation layer, the method further includes: forming a via hole on the first passivation layer and the second passivation layer, so that drain is exposed through the via hole; and forming a pixel electrode layer on the second passivation layer, wherein the pixel electrode layer is electrically connected to the drain through the via hole such as taught by Ju in order to driving a light emitting device. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over SAOTOME and CN103184408A in view of Huang et al. 20140264863. Regarding claim 17, SAOTOME and CN103184408A disclose claim 1, but do not disclose wherein the step of preparing the first passivation layer on the driving circuit layer includes: preparing a silicon dioxide layer on the driving circuit layer through a chemical vapor deposition process; and the silicon dioxide layer covers the driving circuit layer to form the first passivation layer. Fig. 3B of SAOTOME discloses wherein the step of preparing the first passivation layer on the driving circuit layer includes: preparing dielectric layer on the driving circuit layer and the dielectric layer covers the driving circuit layer to form the first passivation layer. However, par [0075] of Huang discloses that the buffer layer 902 is a dielectric passivation material such as silicon dioxide, polyimide, or the like, that may be placed or formed, depending at least in part on the precise material chosen, using a process such as chemical vapor deposition. As such it would have been obvious to form a method comprising disclose wherein the step of preparing the first passivation layer on the driving circuit layer includes: preparing a silicon dioxide layer on the driving circuit layer through a chemical vapor deposition process; and the silicon dioxide layer covers the driving circuit layer to form the first passivation layer such as taught by Huang as silicon dioxide is conventional use and is formed by chemical vapor deposition. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over SAOTOME and CN103184408A in view of Ryu et al. 20210066437. Regarding claim 2, SAOTOME and CN103184408A disclose claim 1, but do not disclose wherein the step of preparing the original metal layer on the first passivation layer includes: depositing the original metal layer of a first thickness on the first passivation layer by a physical deposition process. However, par [0108] of Ryu disclose deposition a metal layer is formed on an exposed portion of the lower surface and the inclined side surface of the display panel by a physical deposition process such as sputtering, evaporation. In view of such teaching, it would have been obvious to form a method comprising wherein the step of preparing the original metal layer on the first passivation layer includes: depositing the original metal layer of a first thickness on the first passivation layer by a physical deposition process such as taught by Ryu as known prior art method. Regarding claim 3, SAOTOME and CN103184408A and Ryu do not disclose wherein a thickness value of the first thickness ranges from 100 angstroms to 1000 angstroms. In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. As such it would have been obvious to form a method comprising wherein a thickness value of the first thickness ranges from 100 angstroms to 1000 angstroms in order to meet the applicant specification. Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over SAOTOME and CN103184408A in view of SON et al. 20160225999. Regarding claim 4, SAOTOME and CN103184408A disclose claim 1, but do not disclose wherein the step of preparing the oxygen source layer on the original metal layer includes: depositing the oxygen source layer of a second thickness on the original metal layer by a physical deposition process. However, par [0132] of Son discloses a step of forming a metal oxide thin film between the first electrode and the electron transport layer. To form the metal oxide thin film, any chemical or physical deposition process used conventionally in semiconductor fabrication processes may be carried out. As such it would have been obvious to form a method of SAOTOME and CN103184408A comprising wherein the step of preparing the oxygen source layer on the original metal layer includes: depositing the oxygen source layer of a second thickness on the original metal layer by a physical deposition process such as taught by Son as this is conventional method. Regarding claim 5, SAOTOME and CN103184408A and Son do not disclose wherein a thickness value of the second thickness ranges from 500 angstroms to 5000 angstroms. In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. As such it would have been obvious to form a method comprising wherein a thickness value of the second thickness ranges from 500 angstroms to 5000 angstroms in order to meet the applicant specification. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 21, 2023
Application Filed
Feb 20, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 14, 2026
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NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME
2y 5m to grant Granted Mar 24, 2026
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2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+19.1%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 914 resolved cases by this examiner. Grant probability derived from career allow rate.

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