Prosecution Insights
Last updated: April 19, 2026
Application No. 17/276,676

Switching Device for Separating a Current Path

Non-Final OA §103
Filed
Mar 16, 2021
Examiner
O TOOLE, COLLEEN J
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siemens Aktiengesellschaft
OA Round
7 (Non-Final)
57%
Grant Probability
Moderate
7-8
OA Rounds
3y 3m
To Grant
68%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allow Rate
345 granted / 608 resolved
-11.3% vs TC avg
Moderate +12% lift
Without
With
+11.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
27 currently pending
Career history
635
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
57.6%
+17.6% vs TC avg
§102
31.9%
-8.1% vs TC avg
§112
8.8%
-31.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 608 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (CN106024497 cited in the Information Disclosure Statement filed March 29, 2024, hereafter Wen). Claim 1: Wen teaches a switching device for disconnecting a current path in a DC supply system (Abstract and Figure 4), said current path comprising source-end and load-end inductances (inherent source-end and load-end inductances of conductors provided at the source-end and the load-end), the switching device comprising: two series-connected switching modules (IGBTs in Figure 4), wherein each of the switching modules comprises three parallel branches (shown in Figure 4 and defined below); the first branch including a first controllable semiconductor switching element (IGBT); the second branch including a first resistor (R2) connected in series to a second resistor (R1) and then a first capacitor (C1); the third branch including a second capacitor (C2) in series with a respective second switching element comprising a disconnectable thyristor (thyristor D1 and [0022], [0023], [0054], [0078] and [0080] where D1 is turned on and off, or connected and disconnected, in the time period between the IGBT starting to conduct commutation and turning off the current); wherein a first node (node connecting IGBT, C2 and R2) joins the first end of all three branches so the first resistor (R2) is connected to a first load terminal of the first controllable semiconductor switching element (IGBT) and a second load terminal of the first controllable semiconductor switching element (node connecting IGBT, C1 and D1) is connected to the first capacitor (C1); and a connecting leg runs from an intermediate node of the second branch (node connecting D1, C2, R1 and R2) to a respective intermediate node of the third branch (the node connecting D1, C2, R1 and R2 is the same node), wherein the intermediate node of the second branch is between the first resistor and the second resistor (node between R2 and R1) and the respective intermediate node of the third branch is between the second capacitor and the second switching element (node between C1 and D1). Wen further teaches that the discharge time of the second capacitor is equal to the resistance of R2 times the capacitance value of the second capacitor ([0058]). Wen does not specifically teach that a desired discharge time of the first capacitor is set by the ratio of the resistance values of the resistors in the series circuit. However, the selection of a desired discharge time of the first capacitor is set by the ratio of the resistance values of the resistors in the series circuit for the switching device would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a desired discharge time of the first capacitor is set by the ratio of the resistance values of the resistors in the series circuit when employing the switching device of Wen to maximize the overall performance of the switching device. Furthermore, such a provision of selecting a specific discharge time involves only routine design expedient. Claim 2: Wen further teaches the respective second switching elements (D1) can be switched to a conducting state and a blocking state via a control signal ([0054], [0078] and [0080] where D1 is turned on and off in the time period between the IGBT starting to conduct commutation and turning off the current). Claim 6: Wen further teaches that the thyristors can be turned off by a turn-off circuit (the inherent turn-off circuit that controls D1 in the manner described in [0058] and [0080]). Claim 7: Wen further teaches that the first controllable semiconductor switching element (IGBT) is an element of the turn-off circuit ([0080] where when IGBT is turned off, the voltage across the IGB rises and the current will oscillate until the charging current on C2 drops to zero, turning off D1). Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wen in view of Cairoli et al. (U.S. Patent 10,230,260, hereafter Cairoli). Claim 3: Wen teaches the limitations of claim 1 above. Wen does not specifically teach that the respective second switching element (thyristor D1 of Wen) is an insulated-gate bipolar transistor. Cairoli teaches a respective second switching elements comprise an insulated-gate bipolar transistor (column 2 lines 59-67). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the further controllable semiconductor switching element taught by Cairoli in the circuit of Wen to provide a controlled turn off device (column 2 lines 59-67 of Cairoli). Response to Arguments Applicant’s arguments filed October 27, 2025 with respect to the rejection(s) of claim(s) 1 and 9 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 U.S.C. 103 as being unpatentable over Wen. Applicant asserts that Wen does not teach setting a desired discharge time of the first capacitor based on the ratio of resistance values of the resistors in the series circuit. Examiner notes that Wen teaches that the discharge time of the second capacitor is equal to the resistance of R2 times the capacitance value of the second capacitor ([0058]). Wen does not specifically teach that a desired discharge time of the first capacitor is set by the ratio of the resistance values of the resistors in the series circuit. However, the selection of a desired discharge time of the first capacitor is set by the ratio of the resistance values of the resistors in the series circuit for the switching device would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a desired discharge time of the first capacitor is set by the ratio of the resistance values of the resistors in the series circuit when employing the switching device of Wen to maximize the overall performance of the switching device. Furthermore, such a provision of selecting a specific discharge time involves only routine design expedient. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.J.O/Examiner, Art Unit 2849 /Menatoallah Youssef/SPE, Art Unit 2849
Read full office action

Prosecution Timeline

Mar 16, 2021
Application Filed
Mar 16, 2021
Response after Non-Final Action
Sep 24, 2021
Non-Final Rejection — §103
Dec 10, 2021
Response Filed
Feb 28, 2022
Final Rejection — §103
Apr 07, 2022
Response after Non-Final Action
Apr 20, 2022
Request for Continued Examination
Apr 25, 2022
Response after Non-Final Action
Jun 16, 2022
Non-Final Rejection — §103
Sep 02, 2022
Response Filed
Dec 13, 2022
Final Rejection — §103
Jan 24, 2023
Response after Non-Final Action
Feb 24, 2023
Response after Non-Final Action
Mar 15, 2023
Notice of Allowance
Apr 19, 2023
Response after Non-Final Action
Apr 30, 2023
Response after Non-Final Action
Jul 29, 2023
Response after Non-Final Action
Sep 21, 2023
Response after Non-Final Action
Sep 25, 2023
Response after Non-Final Action
Sep 26, 2023
Response after Non-Final Action
Sep 26, 2023
Response after Non-Final Action
Nov 26, 2024
Response after Non-Final Action
Jan 29, 2025
Request for Continued Examination
Jan 30, 2025
Response after Non-Final Action
Mar 08, 2025
Non-Final Rejection — §103
May 21, 2025
Response Filed
Aug 23, 2025
Final Rejection — §103
Oct 27, 2025
Response after Non-Final Action
Nov 25, 2025
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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POWER SWITCH CIRCUIT
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SWITCH LINEARIZATION WITH ASYMMETRICAL ANTI-SERIES VARACTOR PAIR
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Patent 12556164
CONDITIONAL ACTIVE THERMAL CONTROL TO INCREASE POWER SEMICONDUCTOR LIFETIME AND EFFICIENCY
2y 5m to grant Granted Feb 17, 2026
Patent 12556082
DRIVING CIRCUIT OF BRIDGE CIRCUIT
2y 5m to grant Granted Feb 17, 2026
Patent 12541216
CONTROLLER AREA NETWORK (CAN) TRANSCEIVER
2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
57%
Grant Probability
68%
With Interview (+11.5%)
3y 3m
Median Time to Grant
High
PTA Risk
Based on 608 resolved cases by this examiner. Grant probability derived from career allow rate.

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