DETAILED ACTION
Claims 1 and 11 are amended. Claims 3, 5, 9, 13, 15 and 19 are withdrawn. Claims 6, 8, 10, 16, 18 and 20 are cancelled. Claims 21-26 are added. Claims 1-2, 4, 7, 11-12, 14, 17 and 21-26 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7, 11-12, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 20160225312) in view of Jeong (US 20120026145) in view of Wu (US 20150339973) in view of Lu (US 20080074360).
As per claims 1 and 11, Byun discloses a pixel driving circuit (display panel, comprising a pixel driving circuit) (Fig. 3, #152), (wherein the pixel driving circuit comprises) comprising a first transistor (#T1), a second transistor (#T2), a third transistor (#T5), a fourth transistor (#T6), a first capacitor (#C1), a second capacitor (#C2), and an organic light emitting diode (#OLED; [0070]; [0072]);
wherein a gate of the first transistor (#T1) is connected to a first node, a source of the first transistor (#T1) is connected to a second node, and a drain of the first transistor (#T1) is connected to a third node;
a gate of the second transistor (#T2) is connected to a first scan signal (#SCn), a source of the second transistor (#T2) is connected to a data signal (#DAm), and a drain of the second transistor (#T2) is connected to the second node;
a gate of the third transistor (#T5) is connected to an enabling signal (#En), a source of the third transistor (#T5) is connected to a first power signal (#ELVDDL), and a drain of the third transistor (#T5) is connected to the second node;
a gate of the fourth transistor (#T6) is connected to the enabling signal (#En), a source of the fourth transistor (#T6) is connected to the third node, and a drain of the fourth transistor (#TR6) is connected to an anode of the organic light emitting diode (#OLED);
one end of the first capacitor (#C1) is connected to the first power signal (#ELVDDL), and another end of the first capacitor (#C1) is connected to the first node;
one end of the second capacitor (#C2) is connected to the gate of the second transistor (#T2), and another end of the second capacitor (#C2) is connected to the first node;
a cathode of the organic light emitting diode (#OLED) is connected to a second power signal (#ELVSS);
the pixel driving circuit further comprises a fifth transistor (#T3), a gate of the fifth transistor (#T3) is connected to the first scan signal (#SCn), and a second electrode of the fifth transistor (#T3) is connected to the third node.
However, Byun does not teach an eighth transistor, a gate of the eighth transistor is connected to the first scan signal, a source of the eighth transistor is directly connected to the first node, a drain of the eighth transistor is directly connected to a first electrode of the fifth transistor.
Jeong teaches an eighth transistor (Fig. 4, #M3), a gate of the eighth transistor (#M3) is connected to the first scan signal (#S1n), a source of the eighth transistor (#M3) is directly connected to the first node (#N1), a drain of the eighth transistor (#M3) is directly connected to a first electrode of the fifth transistor (#M2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the eighth transistor disclosed by Jeong to the pixel driving circuit of Byun so as to electrically connect the fifth transistor to the first node.
However, the prior art of Byun and Jeong do not teach the pixel driving circuit further comprises a seventh transistor;
wherein a gate of the seventh transistor is connected to a second scan signal, a source of the seventh transistor is connected to the third node, and a drain of the seventh transistor is connected to the anode of the organic light emitting diode.
Wu teaches the pixel driving circuit further comprises a seventh transistor (#T3; [0032]);
wherein a gate of the seventh transistor (#T3) is connected to a second scan signal (#S2), a source of the seventh transistor (#T3) is connected to the third node, and a drain of the seventh transistor (#T3) is connected to the anode of the organic light emitting diode (#L; [0033]; [0035]; [0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the seventh transistor disclosed by Wu to the pixel driving circuit of Byun in view of Jeong so as to provide a seventh transistor connected to a second scan signal, a source of the seventh transistor is connected to the third node, and a drain of the seventh transistor is connected to the anode of the organic light emitting diode.
However, the prior art of Byun, Jeong and Wu do not teach the second transistor is a low-temperature polysilicon transistor.
Lu teaches the transistor is a low-temperature polysilicon transistor ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second transistor of Byun in view of Jeong and Wu formed according to Lu so as to provide a low-temperature polysilicon thin film transistor (LTPS TFT) substrate (Lu: [0005]).
As per claims 2 and 12, Byun in view of Jeong in view of Wu in view of Lu discloses the pixel driving circuit (display panel) according to claim 1 (claim 11), wherein the first transistor (Byun: #T1), the third transistor (Byun: #T5), and the fourth transistor (Byun: #T6) are low-temperature polysilicon transistors (Lu: [0005]).
As per claims 4 and 14, Byun in view of Jeong in view of Wu in view of Lu discloses the pixel driving circuit (display panel) according to claim 2 (claim 12), further comprising a sixth transistor (Byun: #T4);
wherein a gate of the sixth transistor (Byun: #T4) is connected to the second scan signal (Byun: #SCn-1), and a first electrode of the sixth transistor (Byun: #T4) is connected to the first electrode of the fifth transistor (Byun: #T3); and
wherein the sixth transistor (Byun: #T4) is an oxide semiconductor transistor or a low-temperature polysilicon transistor (Lu: [0005]).
As per claims 7 and 17, Byun in view of Jeong in view of Wu in view of Lu discloses the pixel driving circuit (display panel) according to claim 4 (claim 14), wherein a second electrode of the sixth transistor (Byun: #T4) is connected to a reference voltage (Byun: #Vint) or connected to the anode of the organic light emitting diode;
the first electrode of the sixth transistor (Byun: #T4) is a source, and the second electrode of the sixth transistor (Byun: #T4) is a drain if the sixth transistor is a p-type transistor (Byun: see Fig. 3); and
the first electrode of the sixth transistor is a drain, and the second electrode of the sixth transistor is a source if the sixth transistor is an n-type transistor.
Claims 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Byun in view of Jeong in view of Zhu (US 20190019452) in view of Lu.
As per claim 21, Byun discloses a pixel driving circuit (Fig. 3, #152), comprising a first transistor (#T1), a second transistor (#T2), a third transistor (#T5), a fourth transistor (#T6), a first capacitor (#C1), a second capacitor (#C2), and an organic light emitting diode (#OLED; [0070]; [0072]);
wherein a gate of the first transistor (#T1) is connected to a first node, a source of the first transistor (#T1) is connected to a second node, and a drain of the first transistor (#T1) is connected to a third node;
a gate of the second transistor (#T2) is connected to a first scan signal (#SCn), a source of the second transistor (#T2) is connected to a data signal (#DAm), and a drain of the second transistor (#T2) is connected to the second node;
a gate of the third transistor (#T5) is connected to an enabling signal (#En), a source of the third transistor (#T5) is connected to a first power signal (#ELVDDL), and a drain of the third transistor (#T5) is connected to the second node;
a gate of the fourth transistor (#T6) is connected to the enabling signal (#En), a source of the fourth transistor (#T6) is connected to the third node, and a drain of the fourth transistor (#TR6) is connected to an anode of the organic light emitting diode (#OLED);
one end of the first capacitor (#C1) is connected to the first power signal (#ELVDDL), and another end of the first capacitor (#C1) is connected to the first node;
one end of the second capacitor (#C2) is connected to the gate of the second transistor (#T2), and another end of the second capacitor (#C2) is connected to the first node;
a cathode of the organic light emitting diode (#OLED) is connected to a second power signal (#ELVSS);
the pixel driving circuit further comprises a fifth transistor (#T3), a gate of the fifth transistor (#T3) is connected to the first scan signal (#SCn), and a second electrode of the fifth transistor (#T3) is connected to the third node.
However, Byun does not teach an eighth transistor, a gate of the eighth transistor is connected to the first scan signal, a source of the eighth transistor is directly connected to the first node, a drain of the eighth transistor is directly connected to a first electrode of the fifth transistor.
Jeong teaches an eighth transistor (Fig. 4, #M3), a gate of the eighth transistor (#M3) is connected to the first scan signal (#S1n), a source of the eighth transistor (#M3) is directly connected to the first node (#N1), a drain of the eighth transistor (#M3) is directly connected to a first electrode of the fifth transistor (#M2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the eighth transistor disclosed by Jeong to the pixel driving circuit of Byun so as to electrically connect the fifth transistor to the first node.
However, the prior art of Byun and Jeong do not teach the pixel driving circuit further comprises a seventh transistor;
wherein a gate of the seventh transistor is connected to the enabling signal, a source of the seventh transistor is connected to a reference voltage, and a drain of the seventh transistor is connected to the anode of the organic light emitting diode.
Zhu teaches the pixel driving circuit (Fig. 3B, #110) further comprises a seventh transistor (#T3);
wherein a gate of the seventh transistor (#T3) is connected to the enabling signal (#Em1), a source of the seventh transistor (#T3) is connected to a reference voltage (#VINIT), and a drain of the seventh transistor (#T3) is connected to the anode of the organic light emitting diode (#OLED; [0089]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the seventh transistor disclosed by Zhu to the pixel driving circuit of Byun in view of Jeong so as to provide the initialization voltage VINIT to the anode of the OLED.
However, the prior art of Byun, Jeong and Zhu do not teach the second transistor is a low-temperature polysilicon transistor.
Lu teaches the transistor is a low-temperature polysilicon transistor ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second transistor of Byun in view of Jeong and Zhu formed according to Lu so as to provide a low-temperature polysilicon thin film transistor (LTPS TFT) substrate (Lu: [0005]).
As per claim 22, Byun in view of Jeong in view of Zhu in view of Lu discloses the pixel driving circuit according to claim 21, the fifth transistor (Byun: #T3) is an oxide semiconductor transistor or a low-temperature polysilicon transistor (Lu: [0005]);
the first electrode is a source, and the second electrode is a drain if the fifth transistor (Byun: #T3) is a p-type transistor;
the first electrode is a drain, and the second electrode is a source if the fifth transistor is an n-type transistor.
As per claim 23, Byun in view of Jeong in view of Zhu in view of Lu discloses the pixel driving circuit according to claim 21, wherein the first transistor (Byun: #T1), the third transistor (Byun: #T5), and the fourth transistor (Byun: #T6) are low-temperature polysilicon transistors (Lu: [0005]).
As per claim 24, Byun in view of Jeong in view of Zhu in view of Lu discloses the pixel driving circuit according to claim 23, further comprising a sixth transistor (Byun: #T4);
wherein a gate of the sixth transistor (Byun: #T4) is connected to the second scan signal (Byun: #SCn-1), and a first electrode of the sixth transistor (Byun: #T4) is connected to the first electrode of the fifth transistor (Byun: #T3); and
wherein the sixth transistor (Byun: #T4) is an oxide semiconductor transistor or a low-temperature polysilicon transistor (Lu: [0005]).
As per claim 25, Byun in view of Jeong in view of Zhu in view of Lu discloses the pixel driving circuit according to claim 24, wherein a second electrode of the sixth transistor (Byun: #T4) is connected to a reference voltage (Byun: #Vint) or connected to the anode of the organic light emitting diode;
the first electrode of the sixth transistor (Byun: #T4) is a source, and the second electrode of the sixth transistor (Byun: #T4) is a drain if the sixth transistor is a p-type transistor (Byun: see Fig. 3); and
the first electrode of the sixth transistor is a drain, and the second electrode of the sixth transistor is a source if the sixth transistor is an n-type transistor.
As per claim 26, Byun in view of Jeong in view of Zhu in view of Lu discloses the pixel driving circuit according to claim 21, wherein the eighth transistor (Jeong: Fig. 4, #M3) is an oxide semiconductor transistor;
the first electrode of the fifth transistor (Byun: #T3) is a source, and the second electrode of the fifth transistor (Byun: #T3) is a drain if the fifth transistor (Byun: #T3) is a p-type transistor; the first electrode of the fifth transistor is a drain, and the second electrode of the fifth transistor is a source if the fifth transistor is an n-type transistor.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because of the new grounds of rejection as presented above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached on 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nelson Lam/Examiner, Art Unit 2627
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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