Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Election/Restrictions
Applicant’s election without traverse of Species F, identified as encompassing Claims 1, 11-17, 19 and 20 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng et al. (US 2024/0186419 A1), hereinafter as Z1 and Seko et al. (US 10263116 B2), hereinafter as S1.
Regarding Claim 1, Z1 discloses an array substrate (see FIG. 2, and [0019] ln. 1 “the embodiments of the present disclosure provide a thin film transistor and an array substrate” where the embodiment in FIG. 2 is being used), comprising:
a substrate (see FIG. 2, element 10, and [0021] ln. 3 “the thin film transistor includes a substrate 10”);
a light-shielding layer disposed on the substrate (see FIG. 2, elements 20, and [0023] ln. 1 “The light-shielding layer 20 of the TFT provided by the embodiments of present disclosure includes a first light-shielding pattern 21 , a second light-shielding pattern 22 connected to the first light-shielding pattern 21 , and a third light-shielding pattern 23 connected to the first light-shielding pattern 21” shown in FIG. 2); and
an active layer disposed on the light-shielding layer (see FIG. 2, element 40, and [0021] ln. 4 “active layer 40” and [0022] ln 3 “active layer 40 includes a channel area 43 and conductive areas located on both sides of the channel area 43, and are defined as a first conductive area 41 and a second conductive area 42” as seen in FIG. 2 and where the light shielding layer is disposed beneath the active layer 40),
Z1 does not explicitly disclose wherein an orthographic projection of the active layer on the substrate is positioned within an orthographic projection of the light-shielding layer on the substrate.
S1 discloses wherein an orthographic projection of the active layer (see FIG. 22A, element 5, col. 10 ln. 22 “active layer 5”) on the substrate (see col. 6 ln. 47 “basic structure of the thin film according to the present invention are stacked on a glass substrate”) is positioned within an orthographic projection of the light-shielding layer (see FIG. 2A, element 6, and col. 10 ln. 47 “light shielding layer 6”) on the substrate (see FIG. 2A where the projection of the active layer 5 is within the projection of the light-shielding layer 6).
The projection of the active layer within the light-shielding layer projection as disclosed by S1 is incorporated in Z1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of S1 into Z1 as the alignment of elements yields predictable results – there is motivation to align the active layer within the light-shielding layer in this way to prevent leakage of unwanted light escaping or entering the array substrate and therefore ensuring performance within the device yielding predictable results (see Z1 [0006-0008] and S1 col. 7 ln 43).
Regarding Claim 11, Z1 and S1 disclose the array substrate according to claim 1, where S1 further discloses wherein the light-shielding layer (element 6) comprises a first light-shielding part, a second light-shielding part, and a third light-shielding part connected to each other in sequence (see FIG. 2A where the light shielding element 6 has left, middle, and right portions. The left most portion corresponds to the first light shielding part, the middle section covers the VLDD regions, element 2 col. 10 ln. 26 “LDD [light doped drain] region 2”, and the channel region element 1 col. 10 col. 25 “channel region 1” corresponding to the second light shielding part, and the right most portion corresponds to the third light shielding part), and the first light-shielding part and the third light-shielding part are positioned on different sides of the second light- shielding part (see FIG. 2A where the described first and third light shielding parts are on different sides of the described second light shielding part).
Regarding Claim 12, Z1 and S1 discloses the array substrate according to claim 11, where S1 further discloses wherein the active layer (element 5) comprises a first active part, a second active part, and a third active part connected to each other in sequence (see FIG. 2A where the active layer element 5 has left, middle, and right portions. The left most portion corresponds to the first active part, the middle section covers the VLDD regions element 2, and the channel region element 1 corresponding to the second active part, and the right most portion corresponds to the third active part), the first active part is disposed on the first light-shielding part (see FIG. 2A where the left most portion of the active and light shielding portions overlap), the second active part is disposed on the second light-shielding part (see FIG. 2A where the middle portion of the active and light shielding portion overlap), and the third active part is disposed on the third light-shielding part (see FIG. 2A where the right most portion of the active and light shielding portions overlap).
Regarding Claim 13, Z1 and S1 disclose the array substrate according to claim 12, where S1 further discloses wherein the second active part comprises first conducting regions (see FIG. 2A, element 2, and col. 10 ln. 26 “LDD [light doped drain] region 2”) and a first channel region (see FIG. 2A, element 1, and col. 10 col. 25 “channel region 1”), the first conducting regions are disposed on both ends of the first channel region (see FIG. 2A where the two element 2 regions are on both sides of the channel region 1), and the first active part and the third active part are second conducting regions (see FIG. 2A, element 3, col. 10 ln. 27 “both ends of the active layer 5 is a source-drain region 3” which would be conductive region on the left and right).
Regarding Claim 14, Z1 and S1 disclose the array substrate according to claim 13, where Z1 further discloses wherein the second light-shielding part (see FIG. 2, element 20 and 21, [0023] ln. 1 “light-shielding layer 20...includes a first light-shielding pattern 21” where element 21 corresponds to second light shielding layer) is provided with a first protrusion (see FIG. 2 where the light shielding element 21 protrudes outward), a protruding direction of the first protrusion is perpendicular to an extending direction of the first channel region (see FIG. 2 where the protrusion of light shielding element 21 protrudes perpendicular to a first channel region 43, [0023] ln. 6 “light-shielding pattern 21 is located below the channel area 43”), and the first protrusion is positioned in an area of the second light-shielding part corresponding to the first conducting regions (see FIG. 2 and [0022] ln. 4 “conductive areas located on both sides of the channel area 43, and are defined as a first conductive area 41 and a second conductive area 42” where elements 42 and 41 are the described first and third conductive parts at the sides of element 43, where the protrusion at the light shielding element 21 corresponds to the conductive regions at the sides of element 43).
Regarding Claim 20, Z1 and S1 disclose the array substrate according to claim 1, where S1 further discloses wherein a thickness of the active layer ranges from 30 nm to 70 nm (see col. 10 ln. 22 “active layer 5 of 30nm” which is within the presented range).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zheng et al. (US 2024/0186419 A1), hereinafter as Z1 and Seko et al. (US 10263116 B2), hereinafter as S1, in view of Liu et al. (US 10312271 B2), hereinafter as L1.
Regarding Claim 15, Z1 and S1 disclose the array substrate according to claim 14, but does not explicitly disclose wherein an edge of an orthographic projection of an area of the active layer excluding the first conducting regions overlaps an edge of the orthographic projection of the light-shielding layer.
L1 discloses wherein an edge of an orthographic projection of an area of the active layer (see FIG. 3(a), element 70, col. 4 ln. 58 “active layer 70”) excluding the first conducting regions overlaps an edge of the orthographic projection of the light-shielding layer (see FIG. 3(a), element 20, col. 5 ln. 18 “20 may be a metal light-shielding layer”, where the edge projection of the active layer 70 overlaps an edge of the light shielding layer 20 projection in FIG. 3(a)).
The placement and overlap of the active layer and light shielding layer as disclosed by L1 is incorporated into the disclosure of S1 and Z1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of L1 with Z1 and S1 because there is motivation to shield the light at the edges of the array substrate, which produces predictable results-by having the light shielding layer extend to the edges of the active area, the device can effectively shield unwanted light leakage in the edges of the device which obtains predictable results (see L1 col. 7 ln. 24).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Zheng et al. (US 2024/0186419 A1), hereinafter as Z1 and Seko et al. (US 10263116 B2), hereinafter as S1, in view of Sasaki et al. (US 2005/0213173 A1), hereinafter as S2.
Regarding Claim 16, Z1 and S1 disclose the array substrate according to claim 13, but do not disclose wherein a doping concentration of the first channel region is less than a doping concentration of the first conducting regions, and the doping concentration of the first conducting regions is less than a doping concentration of the second conducting regions.
S2 discloses wherein a doping concentration of the first channel region (see FIG. 3, elements 25 and 25a, and [0052] ln. 3 “semiconductor thin film 25… formed with a channel region 25a composed of an intrinsic region”) is less than a doping concentration of the first conducting regions (see FIG. 3, elements 25b, and [0052] ln. 5 “on either side are source-drain regions 25b composed of an N-type impurity low concentration region”), and the doping concentration of the first conducting regions is less than a doping concentration of the second conducting regions (see FIG. 3, elements 25c, and [0052] ln. 7 “further on either side (subsequent outer end sides) are source-drain regions 25c composed of an N-type impurity high concentration region” where the channel 25a is intrinsic, the first conducting areas 25b around the channel 25a have a low concentration of impurities, and the second conducting region 25c around the first has a high concentration of impurities. The intrinsic channel is less than the low concentration, and the low concentration is less than the high concentration.).
The channel doping concentration being lower than the conductive regions as disclosed by S2 is incorporated as the channel region in Z1 and S1. The doping concentrations of the two conducting regions as disclosed by S2 is incorporated into the disclosure of Z1 and S1. It would have been obvious to one of ordinary skill in the art to have included the disclosure of S2 into Z1 and S1 as there is motivation for there to be two different concentrations surrounding the channel to properly modulate the current flow across the device. By having a heavily doped conductor around the surrounding lightly doped conductor the current flows through the channel in a desired direction while lowering the likelihood of leakage. Doping the conducting regions in this manner yields predictable results (see S2 [0052] and [0138])
Claims 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng et al. (US 2024/0186419 A1), hereinafter as Z1 and Seko et al. (US 10263116 B2), hereinafter as S1, in view of Yuan et al. (US 2024/0297174 A1), hereinafter as Y1.
Regarding Claim 17, Z1 and S1 disclose the array substrate according to claim 13, but do not explicitly disclose wherein a distance from an edge of an orthographic projection of the first conducting regions on the substrate to an edge of the orthographic projection of the light-shielding layer on the substrate ranges from 400 nm to 2,000 nm.
Y1 discloses wherein a distance from an edge of an orthographic projection of the first conducting regions (see FIG. 4, elements 30, 31, and 32, [0076] ln. 1 “the active layer 30 includes a channel region 31, a lightly doped region 32” where the active layer 30 is a conductive region, with element 32 being the first conductive region) on the substrate (see FIG. 4, element 10, [0069] ln. 1 “the array substrate includes a base substrate 10”) to an edge of the orthographic projection of the light-shielding layer (see FIG.4, element LS, [0069] ln. 7 “light-shielding layer LS”) on the substrate ranges from 400 nm to 2,000 nm (see FIG. 4, element a, and [0078] ln. 1 “a distance between a boundary of an orthographic projection of one of the light-shielding layers LS on the base substrate 10 and a boundary of an orthographic projection of the channel region 31 adjacent to the one of the light-shielding layers LS on the base substrate 10 is a, and a ≥2 microns” where element 32 is aligned with element 31 and at the same distance of element a and therefore the same distance away from the edge of the projection and where 2 microns is equivalent to 2000nm and within the presented range).
The distance between the active layer projection and the light-shielding layer projection as presented by Y1 is incorporated into the disclosure of Z1 and S1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of Y1 with Z1 and S1 because there is motivation to shield the light at the edges of the array substrate, which produces predictable results-by having the light shielding at this distance from the conductive region, the device can effectively shield unwanted light leakage in the edges of the device which obtains predictable results (see Y1 [00078]).
Regarding Claim 19, Z1 and Y1 disclose the array substrate according to claim 1, but do not explicitly disclose wherein a distance from an edge of the orthographic projection of the active layer on the substrate to an edge of the orthographic projection of the light-shielding layer on the substrate ranges from 0 nm to 6,000 nm.
Y1 discloses wherein a distance from an edge of the orthographic projection of the active layer (element 30) on the substrate to an edge of the orthographic projection of the light-shielding layer (element LS) on the substrate ranges from 0 nm to 6,000 nm (see FIG. 4, element a, and [0078] ln. 1 “a distance between a boundary of an orthographic projection of one of the light-shielding layers LS on the base substrate 10 and a boundary of an orthographic projection of the channel region 31 adjacent to the one of the light-shielding layers LS on the base substrate 10 is a, and a ≥2 microns” where the channel region 31 is within the active region 30 and at the distance of element a, and 2 microns is equivalent to 2000nm and within the presented range).
The distance between the active region projection and the light-shielding layer projection as presented by Y1 is incorporated into the disclosure of Z1 and S1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of Y1 with Z1 and S1 because there is motivation to shield the light at the edges of the array substrate, which produces predictable results-by having the light shielding at this distance from the active region, the device can effectively shield unwanted light leakage in the edges of the device which obtains predictable results (see Y1 [00078]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENNEN STUART CUDA whose telephone number is (571)272-6563. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/B.S.C./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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