DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura (US 2011/0170029).
Regarding Claim 1, Kimura discloses an array substrate (shown in Fig 28 and Fig 29A-B-30A-B), comprising:
a base substrate (first substrate 2001 [0258] Fig 28);
a plurality of data lines (signal line 116 [0168] and potential supply line 1219 [0219] Fig 21) extending in a vertical direction (vertical direction Fig 21),
wherein the plurality of data lines (116 and 1219 Fig 21) comprise a plurality of first-type data lines (116 Fig 21) and a plurality of second-type data lines (1219 Fig 21) arranged in parallel with the first-type data lines (116 Fig 21), and
the first-type data lines (116 Fig 21) and the second-type data lines (1219 Fig 21) are respectively configured with data voltages with opposite polarities (signals having different polarities are input to the signal lines 116_1 and 116_2 [0202] Fig 12, may be positive polarity and negative polarity [0189], and the potential supply line 1219 and the signal line 116 can be reversed to function [0222]);
a plurality of scan lines (scan line 117 [0170] Fig 21) extending in a horizontal direction (horizontal direction Fig 21); and
a plurality of pixel units (pixel unit [0212] shown in Fig 17 and annotated Fig 21), wherein each of the pixel units (shown in Fig 17) comprises a plurality of sub-pixels (sub-pixels 1100a and 1100b [0211] Fig 17) defined by intersecting the scan lines (scan lines 117a and 117b [0211] Fig 17) and the data lines (116 Fig 17 and Fig 21), and
the plurality of sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) comprise a plurality of first sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) electrically connected to the first-type data lines (116 Fig 21) and a plurality of second sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) electrically connected to the second-type data lines (1219 Fig 21),
wherein each of the sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) is correspondingly provided with one of thin film transistors (thin film transistor TFT [0036], shown in annotated Fig 28, and first transistor 212 and third transistor 213 [0184] shown in Fig 21]) and one of light-shielding layers (first conductive layer 2003 [0264] Fig 28, may be aluminum [0351], the first conductive layer made of aluminum is capable of acting as a light shielding layer) located between the thin film transistor (shown in annotated Fig 28) and the base substrate (2001), and
one of the light-shielding layers (2003 Fig 28) corresponding to each of the first sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) is at least electrically connected to one of the light-shielding layers (2003 Fig 28) corresponding to one of the second sub- pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) through a connecting line (common electrode 118 [0168] Fig 21).
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Regarding Claim 2, Kimura discloses the limitations of claim 1 as explained above. Kimura et al further discloses
wherein the first-type data lines (116 Fig 21) and the second-type data lines (1219 Fig 21) are respectively configured to transmit data voltages of equal magnitude (the potential supply line 1219 and the signal line 116 can be reversed to function [0222], and a positive potential may be equal to Vsig (0) and a negative potential may be -Vsig (0) [0204] Fig 13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 2011/0170029) in view of Ji et al (CN 112394578).
Regarding Claim 3, Kimura discloses the limitations of claim 1 as explained above. Kimura does not disclose
wherein the first-type data lines and the second-type data lines are alternately arranged in the horizontal direction; and
the first sub-pixels and the second sub-pixels are alternately arranged in the horizontal direction to form pixel rows, and
one of the light-shielding layers corresponding to each of the first sub-pixels is at least electrically connected to one of the light-shielding layers corresponding to adjacent one of the second sub-pixels through the connecting line.
Ji et al, in the related art of semiconductor devices that include array substrates, discloses
wherein the first-type data lines (first data line 310 [page 8, lines 8-10] Fig 2A) and the second-type data lines (second data line 320 [page 8, lines 8-10] Fig 2A) are alternately arranged (shown in Fig 2A) in the horizontal direction (horizontal direction Fig 2A); and
the first sub-pixels (first color sub-pixel 110 [page 9, lines 1-6] Fig 2A) and the second sub-pixels (second color sub-pixel 120 [page 9, lines 1-6] Fig 2A) are alternately arranged (alternately arranged [page 9, lines 1-6] Fig 2A) in the horizontal direction (horizontal direction Fig 2A) to form pixel rows (shown in Fig 2A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kimura to include wherein the first-type data lines and the second-type data lines are alternately arranged in the horizontal direction; and the first sub-pixels and the second sub-pixels are alternately arranged in the horizontal direction to form pixel rows, and one of the light-shielding layers corresponding to each of the first sub-pixels is at least electrically connected to one of the light-shielding layers corresponding to adjacent one of the second sub-pixels through the connecting line as taught by Ji et al in order to ensure brightness uniformity [page 9, lines 1-14] and allow for different colors to be used. Further, a person of ordinary skill in the art would have recognized that having brightness uniformity would be advantageous in improving the quality and performance of the device (see MPEP 2143.I(D)).
The combination of Kimura and Ji et al now discloses
one of the light-shielding layers (2003 Fig 28 Kimura) corresponding to each of the first sub-pixels (110 Fig 2A Ji et al) is at least electrically connected to one of the light-shielding layers (2003 Fig 28 Kimura) corresponding to adjacent one of the second sub-pixels (120 Fig 2A Ji et al) through the connecting line (common electrode 118 [0168] Fig 21 Kimura).
Regarding Claim 4, the combination of Kimura discloses the limitations of claim 1 as explained above. Kimura does not disclose
wherein a plurality of adjacent ones of the sub-pixels in each of the pixel rows form one of pixel groups, and
the light-shielding layers corresponding to the sub-pixels in a same one of the pixel groups are electrically connected through the connecting line.
Ji et al, in the related art of semiconductor devices that include array substrates, discloses
wherein a plurality of adjacent ones of the sub-pixels (first color sub-pixel 110, second color sub-pixel 120, and third color sub-pixel 130 [page 9, lines 1-6] Fig 2A) in each of the pixel rows (shown in Fig 2A) form one of pixel groups (shown in Fig 2A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kimura to include wherein a plurality of adjacent ones of the sub-pixels in each of the pixel rows form one of pixel groups as taught by Ji et al in order to ensure brightness uniformity [page 9, lines 1-14] and allow for different colors to be used. Further, a person of ordinary skill in the art would have recognized that having brightness uniformity would be advantageous in improving the quality and performance of the device (see MPEP 2143.I(D)).
The combination of Kimura and Ji et al now discloses
the light-shielding layers (2003 Fig 28 Kimura) corresponding to the sub-pixels (110, 120, 130 Fig 2A Ji et al) in a same one of the pixel groups (shown in Fig 2A Ji et al) are electrically connected through the connecting line (common electrode 118 [0168] Fig 21 Kimura).
Regarding Claim 5, the combination of Kimura and Ji et al discloses the limitations of claim 4 as explained above. The combination of Kimura and Ji et al further discloses
wherein each of the pixel rows (shown in Fig 2A Ji et al) comprises one or more of the pixel groups (shown in Fig 2A Ji et al).
Regarding Claim 6, the combination of Kimura and Ji et al discloses the limitations of claim 5 as explained above. The combination of Kimura and Ji et al further discloses
wherein each of the pixel rows comprises a plurality of the pixel groups (shown in Fig 2A Ji et al), and each of the pixel groups (shown in Fig 2A Ji et al) comprises a same number (2 sub-pixels Fig 2A Ji et al) of the sub- pixels (110, 120, 130 Fig 2A Ji et al).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 2011/0170029) in view of Hu et al (US 2016/0291431).
Regarding Claim 13, Kimura discloses the limitations of claim 1 as explained above. Kimura does not directly disclose
wherein, in each of the sub-pixels, the one of the thin film transistors comprises an active layer, a gate, a source, and a drain that are stacked;
the active layer comprises a channel region, a lightly doped region, and a heavily doped region; and
an orthographic projection of one of the light-shielding layers on the active layer covers the channel region, the lightly doped region, and the heavily doped region.
Hu et al, in the related art of semiconductor devices that include TFT transistors, discloses
wherein the thin film transistor (n-type transistor [0046] Fig 2) comprises an active layer (active layer 18 [0062] Fig 5), a gate (gate 10 [0006] Fig 2), a source (source 12 [0006] Fig 2), and a drain (drain 13 [0006] Fig 2) that are stacked;
the active layer (18 Fig 5) comprises a channel region (channel region 4 [0006] Fig 2), a lightly doped region (light doping regions 5 [0007] Fig 2), and a heavily doped region (heavy doping regions 7 [0005] Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumura to include wherein, in each of the sub-pixels, the one of the thin film transistors comprises an active layer, a gate, a source, and a drain that are stacked; the active layer comprises a channel region, a lightly doped region, and a heavily doped region; and an orthographic projection of one of the light-shielding layers on the active layer covers the channel region, the lightly doped region, and the heavily doped region as taught by Hu et al in order to . Further, a person of ordinary skill in the art would have recognized that having a heavily doped region, a channel region, and a lightly doped region in the active layer of a TFT transistor would be advantageous in allowing for a threshold voltage required to be achieved [0062]. Further, a person of ordinary skill in the art would have recognized that achieving a threshold voltage would optimize the electron mobility of the device (see MPEP 2143.I(D)).
The combination of Kimura and Hu et al now discloses
wherein, in each of the sub-pixels (1100a and 1100b Fig 17, shown above in annotated Fig 21 Kimura), the one of the thin film transistors (shown above in annotated Fig 28 Kimura/n-type transistor [0046] Fig 2 Hu et al) comprises an active layer (active layer 18 [0062] Fig 5 Hu et al), a gate (gate 10 [0006] Fig 2 Hu et al), a source (source 12 [0006] Fig 2 Hu et al), and a drain (drain 13 [0006] Fig 2 Hu et al) that are stacked; and
an orthographic projection of one of the light-shielding layers (2003 Fig 28 Kimura) on the active layer (18 Fig 5 Hu et l) covers (it can be observed that the light-shielding layer 2003 covers the entire TFT shown above in annotated Fig 28 Kimura) the channel region (channel region 4 [0006] Fig 2 Hu et al), the lightly doped region (light doping regions 5 [0007] Fig 2 Hu et al), and the heavily doped region (heavy doping regions 7 [0005] Fig 2 Hu et al).
Regarding Claim 15, the combination of Kimura and Hu et al discloses the limitations of claim 13 as explained above. The combination of Kimura and Hu et al further discloses
wherein an orthographic projection of the connecting line (common electrode 118 [0168] Fig 21 Kimura) on the base substrate (first substrate 2001 [0258] Fig 28 kimura) and an orthographic projection of the gate (gate 10 [0006] Fig 2 Hu et al) on the base substrate (first substrate 2001 [0258] Fig 28 Kimura) do not overlap (it can be observed that the thin film transistors (thin film transistor TFT [0036], shown in annotated Fig 28, and first transistor 212 and third transistor 213 [0184] shown in Fig 21 Kimura et al) that comprise the gate 10 Hu et al do not overlap the connecting line 118 Fig 21 Kimura).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 2011/0170029) in view of Hu et al (US 2016/0291431), and in further view of Murade (CN 1195786).
Regarding Claim 14, the combination of Kimura and Hu et al discloses the limitations of claim 13 as explained above. The combination of Kimura and Hu et al does not directly disclose
wherein a distance between a boundary of an orthographic projection of one of the light-shielding layers on the base substrate and a boundary of an orthographic projection of the channel region adjacent to the one of the light- shielding layers on the base substrate is a, and a > 2 microns.
Murade, in the related art of semiconductor devices that include display devices, discloses
a TFT with a channel length of 5 micrometers and a channel width of 20 micrometers [page 24, lines 24-43].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kimura and Hu et al to include wherein a distance between a boundary of an orthographic projection of one of the light-shielding layers on the base substrate and a boundary of an orthographic projection of the channel region adjacent to the one of the light- shielding layers on the base substrate is a, and a > 2 microns as taught by Murade in order to optimize the optical and electrical functioning of the device while meeting small size parameters from miniaturization [page 24, lines 24-43] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
The combination of Kimura, Hu et al, and Murade now discloses
wherein a distance between a boundary of an orthographic projection (shown in annotated Fig 28 Kimura) of one of the light-shielding layers (2003 Fig 28 Kimura) on the base substrate (first substrate 2001 [0258] Fig 28 Kimura) and a boundary of an orthographic projection (shown in annotated Fig 28 Kimura) of the channel region (channel region 4 [0006] Fig 2 Hu et al) adjacent to the one of the light- shielding layers (2003 Fig 28 Kimura) on the base substrate (first substrate 2001 [0258] Fig 28 Kimura) is a, and a > 2 microns ([page 24, lines 24-43] Murade).
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Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 2011/0170029) in view of Zhang et al (US 2022/0199733).
Regarding Claim 16, Kimura discloses the limitations of claim 1 as explained above. Kimura does not directly disclose
wherein a width of the connecting line ranges from 1 micron to 15 microns.
Zhang et al, in the related art of semiconductor devices that include display devices, discloses
wherein a width of the connecting line (second power connection line has a width of 20 microns to 30 microns [00216]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kimura et al to include wherein a width of the connecting line ranges from 1 micron to 15 microns as taught by Zhang et al in order to optimize the electrical function of the device and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 2011/0170029) in view of Wang (CN 109445169) and in further view of Murade (CN 1195786).
Regarding Claim 17, Kimura discloses the limitations of claim 1 as explained above. Kimura does not directly disclose
wherein a thickness of the light-shielding layer and a thickness of the connecting line both range from 300A to 1500A.
Wang, in the related art of semiconductor devices that include display devices, discloses
wherein a thickness of the connecting line (second connection line 22 [page 6, lines 13-49] Fig 4) and a thickness of the light-shielding layer (light shielding part [page 6, lines 13-49] Fig 4) are same [page 6, lines 13-49].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kimura to include wherein a thickness of the connecting line and a thickness of the light-shielding layer are same as taught by Wang in order to meet the small size parameters of the device and because it would have been an obvious matter of design choice to optimize the thickness of the light shielding layer and the connecting line since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that having a light shielding layer thick enough to cover the connecting line but not thicker than the connecting line would be advantageous in protecting the device while optimizing the optical performance of the device (see MPEP 2143.I(D)).
The combination of Kimura and Wang does not directly disclose
wherein a thickness of the light-shielding layer and a thickness of the connecting line both range from 300A to 1500A.
Murade, in the related art of semiconductor devices that include display devices, discloses
wherein a thickness of the light-shielding layer (first light shielding film 7 [page 24, lines 24-43]) is in a range from 300A to 1500A (1000 Angstroms [page 24, lines 24-43]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kimura and Wang to include wherein a thickness of the light-shielding layer and a thickness of the connecting line both range from 300A to 1500A as taught by Murade in order to help improve the image signal and improve the image display quality [page 24, lines 24-43], and because it would have been an obvious matter of design choice to optimize the thickness of the connecting line and the light shielding layer since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that optimizing the thickness of the light shielding layer and connecting line would help optimize the electrical functioning of the device while maintaining adequate light shielding protective qualities (see MPEP 2143.I(D)).
The combination of Kimura, Wang, and Murade now discloses
wherein a thickness of the light-shielding layer (first light shielding film 7 [page 24, lines 24-43] Murade) and a thickness of the connecting line (common electrode 118 [0168] Fig 21 Kimura) both (same thickness [page 6, lines 13-49] Wang) range from 300A to 1500A (1000 Angstroms [page 24, lines 24-43] Murade).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 2011/0170029) in view of Wang (CN 109445169).
Regarding Claim 18, Kimura discloses the limitations of claim 1 as explained above. Kimura does not directly disclose
wherein a thickness of the connecting line and a thickness of the light-shielding layer are same.
Wang, in the related art of semiconductor devices that include display devices, discloses
wherein a thickness of the connecting line (second connection line 22 [page 6, lines 13-49] Fig 4) and a thickness of the light-shielding layer (light shielding part [page 6, lines 13-49] Fig 4) are same [page 6, lines 13-49].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kimura to include wherein a thickness of the connecting line and a thickness of the light-shielding layer are same as taught by Wang in order to meet the small size parameters of the device and because it would have been an obvious matter of design choice to optimize the thickness of the light shielding layer and the connecting line since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that having a light shielding layer thick enough to cover the connecting line but not thicker than the connecting line would be advantageous in protecting the device while optimizing the optical performance of the device (see MPEP 2143.I(D)).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 2011/0170029) in view of Lee (US 2006/0274009) and Okada et al (US 2007/0216827).
Regarding Claim 19, Kimura discloses a display panel (display panel [0019]), wherein the display panel (display panel [0019]) comprises an array substrate (shown in Fig 28 and Fig 29A-B-30A-B) and a second substrate (second substrate 2016 [0256] Fig 28) disposed above thin film transistors (shown in annotated Fig 28) of the array substrate (shown in Fig 28 and Fig 29A-B-30A-B), and
a light shielding film (light shielding film 2014 [0259] Fig 28) is disposed on a side of the second substrate (2016 Fig 28) close to the array substrate (shown in Fig 28 and Fig 29A-B-30A-B), wherein the array substrate (shown in Fig 28 and Fig 29A-B-30A-B) comprises:
a base substrate (first substrate 2001 [0258] Fig 28);
a plurality of data lines (signal line 116 [0168] and potential supply line 1219 [0219] Fig 21) extending in a vertical direction (vertical direction Fig 21),
wherein the plurality of data lines (116 and 1219 Fig 21) comprise a plurality of first-type data lines (116 Fig 21) and a plurality of second-type data lines (1219 Fig 21) arranged in parallel with the first-type data lines (116 Fig 21), and
the first-type data lines (116 Fig 21) and the second-type data lines (1219 Fig 21) are respectively configured with data voltages with opposite polarities (signals having different polarities are input to the signal lines 116_1 and 116_2 [0202] Fig 12, may be positive polarity and negative polarity [0189], and the potential supply line 1219 and the signal line 116 can be reversed to function [0222]);
a plurality of scan lines (scan line 117 [0170] Fig 21) extending in a horizontal direction (horizontal direction Fig 21); and
a plurality of pixel units (pixel unit [0212] shown in Fig 17 and annotated Fig 21), wherein each of the pixel units (shown in Fig 17) comprises a plurality of sub-pixels (sub-pixels 1100a and 1100b [0211] Fig 17) defined by intersecting the scan lines (scan lines 117a and 117b [0211] Fig 17) and the data lines (116 Fig 17 and Fig 21),
the plurality of sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) comprise a plurality of first sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) electrically connected to the first-type data lines (116 Fig 21) and a plurality of second sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) electrically connected to the second-type data lines (1219 Fig 21),
wherein each of the sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) is correspondingly provided with one of thin film transistors (thin film transistor TFT [0036], shown in annotated Fig 28, and first transistor 212 and third transistor 213 [0184] shown in Fig 21]) and one of light-shielding layers (first conductive layer 2003 [0264] Fig 28, may be aluminum [0351], the first conductive layer made of aluminum is capable of acting as a light shielding layer) located between the thin film transistor (shown in annotated Fig 28) and the base substrate (2001), and
one of the light-shielding layers (2003 Fig 28) corresponding to each of the first sub-pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) is at least electrically connected to one of the light-shielding layers (2003 Fig 28) corresponding to one of the second sub- pixels (1100a and 1100b Fig 17, shown in annotated Fig 21) through a connecting line (common electrode 118 [0168] Fig 21); and
wherein an orthographic projection of the light shielding layer (2014 Fig 28) on the array substrate (shown in Fig 28 and Fig 29A-B-30A-B) covers the connecting line (118 Fig 21).
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Kimura does not directly disclose
a black matrix is disposed on a side of the second substrate close to the array substrate.
Lee, in the related art of semiconductor devices that include display devices, discloses
a black matrix (light blocking member 220, referred to as a black matrix [0102] Fig 7A) is disposed on a side of the second substrate (insulating substrate 210 [0102] Fig 7A) close to the array substrate (shown in annotated Fig 7A).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kimura to include a black matrix is disposed on a side of the second substrate close to the array substrate as taught by Lee in order to prevent light from entering the TFT (especially channel region) [0005] as referred to by Okada et al. Further, a person of ordinary skill in the art would have recognized that have a black matrix as a light shielding layer would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Regarding Claim 20, the combination of Kimura, Lee, and Okada et al discloses the limitations of claim 19 as explained above. The combination of Kimura, Lee, and Okada et al further discloses
wherein the display device (liquid crystal display device [0006]) comprises the display panel (display panel [0019]).
Allowable Subject Matter
Claims 7-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7: The prior art does not anticipate or render obvious, alone or in combination, that “wherein each of the pixel rows comprises a plurality of first pixel groups arranged in succession, and each of the first pixel groups comprises N number of adjacent ones of the sub-pixels, where N is a positive integer greater than or equal to 2,” in the combination required by the claim.
Specifically, although the combination of Kimura and Ji et al discloses each of the first pixel groups comprises 2 sub-pixel, the combination of Kimura and Ji et al does not disclose that the first pixel groups are arranged in succession, i.e. arranged one after another without interruption. Further, should another reference be found that discloses this feature, it would not be obvious to a person of ordinary skill in the art to combine the references to make this alteration to Kimura and Ji et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 8- 12 would be allowable based on their dependency on Claim 7.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsubata (US 2011/0211130) which discloses a liquid crystal display device that has sub-pixels [0004], and Hashimoto et al (US 2006/0007213) which discloses a liquid crystal display panel with scan lines and data lines [0009].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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