Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12th May 2026 has been entered.
Response to Amendments
This action is in response to Applicant’s amendments filed 12th May 2026. Claims 1-20 were previously pending. Claims 1, 5, 8, 12, 15 and 19 have been amended according to Applicant’s amendments. No new claims have been added or cancelled. Accordingly, claims 1-20 remain pending and under consideration.
Response to Arguments
35 USC 103 –
Applicant’s arguments, see remarks page 7, filed 15 January 2026, with respect to the rejection of claims 1, 2, 4-7, 9, 11-16, and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Additionally, Applicant’s arguments do not specifically address the Kimura reference and its teachings and accordingly examiner maintains Kimura teaches that which it was cited for.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 2, 4, 6, 8-9, 11, 13, 15, 16, and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 of U.S. Patent No. 9547441. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the instant application are fully disclosed by claims 1-12 of US 9547441.
Further, many of the dependent claims of the instant application have corresponding dependent claims with identical claim limitation wording.
Claims 3, 10, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, and 9 of U.S. Patent No. 9547441 in view of Hayes et al (US 8868825). Claims 3, 10 and 17 are fully disclosed by claims 1, 5, and 9 of US Patent 9547441 except for the physical address referring to the location in the storage device for the entire life of the storage device. However, Hayes discloses write address referring to the location in the storage device for the entire life of the storage device (See Hayes, Col. 1, lines 29-32, disclosing use of nonrepeating addresses which exceed the maximum number of addresses expected to be applied during a lifespan of the storage device).
It would have been obvious to a person having ordinary skill to modify US 9547441 with the non-repeating addresses of Hayes as it enhances the ability to write to pages in flash memory, and for reading the flash memory to recover a previous version of user data (See Hayes, Col 3, lines 53-56).
Claims 1, 2, 4, 6, 8-9, 11, 13, 15, 16, and 18 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 10216447. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the instant application are fully disclosed by claims 1-18 of US 10216447.
Further, many of the dependent claims of the instant application have corresponding dependent claims with identical claim limitation wording.
Claims 3, 10 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, and 13 of U.S. Patent No. 10216447. Claims 3, 10 and 17 are fully disclosed by claims 1, 7, and 13 of US Patent 10216447 except for the physical address referring to the location in the storage device for the entire life of the storage device. However, Hayes discloses write address referring to the location in the storage device for the entire life of the storage device (See Hayes, Col. 1, lines 29-32, disclosing use of nonrepeating addresses which exceed the maximum number of addresses expected to be applied during a lifespan of the storage device).
It would have been obvious to a person having ordinary skill to modify US 10216447 with the non-repeating addresses of Hayes as it enhances the ability to write to pages in flash memory, and for reading the flash memory to recover a previous version of user data (See Hayes, Col 3, lines 53-56).
Claims 1, 2, 4, 6, 8-9, 11, 13, 15, 16, and 18 are further rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No.10564882. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the instant application are fully disclosed by claims 1-18 of US 10564882.
Further, many of the dependent claims of the instant application have corresponding dependent claims with identical claim limitation wording.
Claims 3, 10 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, and 13 of U.S. Patent No. 10564882 in view of Hayes et al (US 8868825). Claims 3, 10 and 17 are fully disclosed by claims 1, 5, and 9 of US Patent 10564882 except for the physical address referring to the location in the storage device for the entire life of the storage device. However, Hayes discloses write address referring to the location in the storage device for the entire life of the storage device (See Hayes, Col. 1, lines 29-32, disclosing use of nonrepeating addresses which exceed the maximum number of addresses expected to be applied during a lifespan of the storage device).
It would have been obvious to a person having ordinary skill to modify US 10564882 with the non-repeating addresses of Hayes as it enhances the ability to write to pages in flash memory, and for reading the flash memory to recover a previous version of user data (See Hayes, Col 3, lines 53-56).
Claims 1-4, 6, 8-11, 13, 15-18 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 11010080. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the instant application are fully disclosed by claims 1-18 of US 11010080. Further, many of the dependent claims of the instant application have corresponding dependent claims with identical claim limitation wording.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-7, 9, 11-14, 15-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura et al (US 2012/0072680 A1, hereinafter Kimura).
Regarding claims 1, 8, and 15, taking claim 8 as exemplary, Kimura discloses a storage system, comprising: a plurality of storage devices (See Kimura, Fig. 2, disclosing multiple SSD 60 and [0031], “A server 100 and a plurality of semiconductor memory devices (SSDs) 60 are connected”); and
a storage array controller operatively coupled to the plurality of storage devices, the storage array controller comprising a processing device (See Kimura, [0031] “A server 100 and a plurality of semiconductor memory devices (SSDs) 60 are connected, via respective interfaces thereof, to a Redundant Array of Inexpensive Disks (RAID) controller 50 that is the semiconductor memory controlling device…The RAID controller 50 includes a server communicating unit 51, a controller 52, a device controlling unit 53, and a memory 54. Also, although not shown, a nonvolatile memory that stores therein system programs is installed in the RAID controller 50. Further, a display unit that displays information may be connected to the RAID controller 50” and [0032] “The controller 52 is implemented by a Central Processing Unit (CPU)”), the processing device to:
receive information describing a layout of memory in a storage device operatively coupled to a processing device of a storage array controller (See Kimura, [0052], “The RAID controller 50 checks that the block size and the page size are each the same for all the SSDs 60);
determine, by the storage array controller, a write size based on the information describing the layout of memory in the storage device of the plurality of storage devices, wherein the write size is determined by the storage array controller instead of a host system (See Kimura, [0035] disclosing server operating in units of data in sector size whereas the SSD operate in units sized as pages and [0082] the writing timing controlling unit 71a controls the timing with which the pieces of data and the redundant information are written into the SSDs 60, by managing, within the data buffer 75, a data storing buffer that stores therein the data and the redundant information in units of pages” or in other words, the controller operates in units of pages determined by the SSD page sizes); and
send a write request to store data at a location of the storage device (See Kimura, [0056] “a procedure in a process performed by the RAID controller 50 to write writing target data in the SSDs 60 in response to a write command from the server 100”), wherein the write request includes a physical address of the location in the storage device and wherein the storage device stores the data using the physical address without performing logical-to-physical address translation at the storage device (See (See Kimura, [0047] “During this writing operation, the device controlling unit 53 sets a write pointer so as to sequentially indicate the writing position for each of the unwritten pages within an erased block in each of the corresponding SSDs 60. Subsequently, the device controlling unit 53 writes the writing target data into the page in the position indicated by the write pointer. After that, the device controlling unit 53 updates the write pointer so as to indicate the position of an unwritten page that follows the page on which the writing process has been performed. Accordingly, the value of the write pointer sequentially changes so as to indicate the next writing position. For example, in the case where each of the blocks is identified by a 15-bit physical address in each channel and where one block contains 64 pages, the write pointer is 21 (=15+6) bits in total”, or in other words, the controller handles translation and the drives use the physical address for writes).
Regarding claims 2, 9, and 16, taking claim 9 as exemplary, Kimura disclosed the storage system of claim 8 as disclosed hereinabove. Kimura further discloses wherein the write request causes the storage device to store the data at the location (See Kimura Fig. 6 and [0057] “At step S26, the RAID controller 50 performs the process as follows for each of the pieces of data stored in the data buffer 75: The RAID controller 50 determines an SSD 60 into which data to be processed is to be written. After that, the RAID controller 50 writes the data to be processed into the SSD 60 determined at step S26”).
Regarding claims 4, 11, and 18, taking claim 11 as exemplary, Kimura disclosed the storage device of claim 8 as described hereinabove. Kimura further discloses wherein writes to the storage device and the further storage device are performed in parallel (See Kimura, [0082],”indicates the number of stripes that are targets to be simultaneously written in one time of writing”) and wherein the information sent by the storage device to the storage array controller is responsive to the storage array controller detecting addition of the storage device (See Kimura Fig. 8, block S70 and [0062] “the RAID controller 50 obtains information about the specifications (the block number, the block size, and the page size) of the substitute SSD”).
Regarding claims 5, 12, and 19, taking claim 12 as exemplary, Kimura disclosed the storage device of claim 8 as described hereinabove. Kimura further discloses wherein the size of the writeable memory unit in the storage device is less than the size of the erasable memory unit in the storage device (See Kimura, [0005], NAND flash memory is block-erase type device and [0033], a plurality of pages form a storage unit called a block and read/write is performed in a unit of a page, or in other words, the size of a page/write unit is smaller than the size of a block/erase unit as multiple pages form a block).
Regarding claim 6 and 13, taking claim 13 as exemplary, Kimura disclosed the storage device of claim 12 as described hereinabove. Kimura further discloses wherein the write size corresponds to the size of the writeable memory unit in the storage device (See Kimura [0082] “the writing timing controlling unit 71a controls the timing with which the pieces of data and the redundant information are written into the SSDs 60, by managing, within the data buffer 75, a data storing buffer that stores therein the data and the redundant information in units of pages” or in other words, the controller operates in units of pages determined by the SSD page sizes”).
Regarding claims 7, 14, and 20, taking claim 14 as exemplary, Kimura disclosed the storage device of claim 8 as described hereinabove. Kimura further discloses wherein multiple erasable memory units are written in parallel (See Kimura, [0039], disclosing simultaneously selecting the set of blocks constituting an error correction code, assigning an unused stripe number to the blocks, and pieces of data are striped across the pages of the blocks and [0040], the time at which the pieces of data to be used for generating an ECC for one stripe are stored altogether is the time at which the predetermined number of pieces of data are stored altogether, or in other words, parallel).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al (US 2012/0072680 A1, hereinafter Kimura) in view of Hayes et al (US8868825, hereinafter Hayes).
Regarding claims 3, 10, and 17, taking claim 10 as exemplary, Kimura disclosed the storage system of claim 8 as described hereinabove. Kimura does not disclose wherein the physical address refers to the location in the storage device for an entire life of the storage device.
However, Hayes discloses wherein the physical address refers to the location in the storage device for an entire life of the storage device (See Hayes, Col. 1, lines 29-32, disclosing use of nonrepeating addresses which exceed the maximum number of addresses expected to be applied during a lifespan of the storage device).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the storage system of Kimura with the non-repeating addresses of Hayes as storage system performance and data reliability can be improved as it enhances the ability to write to pages in flash memory, and for reading the flash memory to recover a previous version of user data (See Hayes, Col 3, lines 53-56).
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lu (US 20140115427 A1) discloses a data storage system controller determining a common memory page size for a non-volatile memory array.
Maddali et al (US 2007/0067520 A1) discloses a method for detecting the configuration of a storage device including a page size parameter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDMUND H KWONG whose telephone number is (571)272-8691. The examiner can normally be reached Monday-Friday 10-6 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/E.H.K/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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