Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
This action is in response to Applicant’s amendments filed 15 January 2026. Claims 1-20 were previously pending. Claims 1, 4, 8, 11, 15, and 18 have been amended according to Applicant’s amendments. No new claims have been added or cancelled. Accordingly, claims 1-20 remain pending and under consideration.
Response to Arguments
35 USC 103 –
Applicant’s arguments, see remarks page 7, filed 15 January 2026, with respect to the rejection of claims 1, 2, 4-7, 9, 11-16, and 18-20 under 35 USC 103 have been fully considered but they are not persuasive.
Applicant argues none of the prior art discloses the newly amended feature of “wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller”. Examiner respectfully disagrees. Otsuka at [0046] discloses “even if the host apparatus sequentially uses a plurality of memory cards each of which prestores a different writable block size, the host apparatus can properly obtain the writable block size of each memory card and write data into the memory card in units of a proper write block size based on the writable block size”, or in other words, the write sizing for different memory devices is based on the device information which indicates the devices have different write sizes while also implicitly disclosing the devices must be coupled to the controller for obtaining the block size and for data writes to occur. Accordingly, Otsuka teaches the newly amended limitation.
Applicant additionally argues Otsuka is limited to sequential use of memory cards and cannot have additional memory cards coupled to the host apparatus and is limited to a single card being read at a time. However, Otsuka is not cited for what Applicant argues. Otsuka at [0046] discloses the host apparatus may sequentially use a plurality of memory cards each of which prestores a different writable block size, or in other words, the sizing of writes based on information sent by the device to the host/controller. Therefore, it would have been obvious to modify the combination of Borchers, Koseki and Kimura with this additional feature as performance and reliability can be improved by allowing for writes to meet the minimum guaranteed recording rate by ensuring writes are integral multiples of the writable block size of the storage devices (See Otsuka, [0039]-[0042]).
Applicant also argues Borchers is silent as to the newly amended limitation “the information sent by the storage device to the storage array controller is responsive to the storage array controller detecting addition of the storage device. Examiner respectfully disagrees. Borchers at [0058] discloses a configuration detection engine used by host to discover hardware device properties of the data storage device and the configuration detection engine can issue query command to the storage device and in response to the query command the data storage device can return information including the size of each flash chip. Or in other words, the detection engine/controller queries and detects the device, the device responds with information. Accordingly, Borchers discloses the newly amended limitation.
Finally, Applicant argues Otsuka is restricted to sequential reading of differing cards and cannot disclose “write to the storage device and the further storage device are performed in parallel. It is noted that the argument is directed to newly added limitations and are disclosed by Borchers, particularly at least at [0077], “chip striping provides maximum parallelism in read and write operations”).
Therefore, examiner maintains the rejection of claims under 35 USC 103.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 2, 4, 6, 8-9, 11, 13, 15, 16, and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 of U.S. Patent No. 9547441 in view of Otsuka et al (US 2007/0183198 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the instant application are fully disclosed by claims 1-12 of US 9547441 except for the write size is for a single write operation and wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller. However, Otsuka discloses the write size is for a single write operation wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller (See Otsuka, [0046], disclosing obtaining the writable block size from multiple memory cards which may of a different writable block size and writes data taking into account the proper write block size for each memory card in units of writable block size, or in other words, each single write is sized based on the layout of blocks for each of the memory cards as part of the write operation).
It would have been obvious to a person having ordinary skill in the art to combine the claims 1-12 of US 9547441 with the individual device write block size determination of Otsuka as storage system performance and reliability can be improved by allowing for writes to meet the minimum guaranteed recording rate by ensuring writes are integral multiples of the writable block size of the storage devices (See Otsuka, [0039]-[0042]).
Further, many of the dependent claims of the instant application have corresponding dependent claims with identical claim limitation wording.
Claims 3, 10, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, and 9 of U.S. Patent No. 9547441 in view of Otsuka (US 2007/0183198 A1), further in view of Hayes et al (US 8868825). Claims 3, 10 and 17 are fully disclosed by claims 1, 5, and 9 of US Patent 9547441 in view of Otsuka (US 2007/0183198 A1) except for the physical address referring to the location in the storage device for the entire life of the storage device. However, Hayes discloses write address referring to the location in the storage device for the entire life of the storage device (See Hayes, Col. 1, lines 29-32, disclosing use of nonrepeating addresses which exceed the maximum number of addresses expected to be applied during a lifespan of the storage device).
It would have been obvious to a person having ordinary skill to modify US 9547441 and Otsuka with the non-repeating addresses of Hayes as it enhances the ability to write to pages in flash memory, and for reading the flash memory to recover a previous version of user data (See Hayes, Col 3, lines 53-56).
Claims 1, 2, 4, 6, 8-9, 11, 13, 15, 16, and 18 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 10216447 in view of Otsuka et al (US 2007/0183198 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the instant application are fully disclosed by claims 1-18 of US 10216447 except for the write size is for a single write operation wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller. However, Otsuka discloses the write size is for a single write operation wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller (See Otsuka, [0046], disclosing obtaining the writable block size from multiple memory cards which may of a different writable block size and writes data taking into account the proper write block size for each memory card in units of writable block size, or in other words, each single write is sized based on the layout of blocks for each of the memory cards as part of the write operation).
It would have been obvious to a person having ordinary skill in the art to combine claims 1-12 of US 10216447 with the individual device write block size determination of Otsuka as storage system performance and reliability can be improved by allowing for writes to meet the minimum guaranteed recording rate by ensuring writes are integral multiples of the writable block size of the storage devices (See Otsuka, [0039]-[0042]).
Further, many of the dependent claims of the instant application have corresponding dependent claims with identical claim limitation wording.
Claims 3, 10 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, and 13 of U.S. Patent No. 10216447 in view of Otsuka (US 2007/0183198 A1), further in view of Hayes et al (US 8868825). Claims 3, 10 and 17 are fully disclosed by claims 1, 7, and 13 of US Patent 10216447 in view of Otsuka except for the physical address referring to the location in the storage device for the entire life of the storage device. However, Hayes discloses write address referring to the location in the storage device for the entire life of the storage device (See Hayes, Col. 1, lines 29-32, disclosing use of nonrepeating addresses which exceed the maximum number of addresses expected to be applied during a lifespan of the storage device).
It would have been obvious to a person having ordinary skill to modify US 10216447 and Otsuka with the non-repeating addresses of Hayes as it enhances the ability to write to pages in flash memory, and for reading the flash memory to recover a previous version of user data (See Hayes, Col 3, lines 53-56).
Claims 1, 2, 4, 6, 8-9, 11, 13, 15, 16, and 18 are further rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No.10564882 in view of Otsuka. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the instant application are fully disclosed by claims 1-18 of US 10564882 except for the write size is for a single write operation wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller. However, Otsuka discloses the write size is for a single write operation wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller (See Otsuka, [0046], disclosing obtaining the writable block size from multiple memory cards which may of a different writable block size and writes data taking into account the proper write block size for each memory card in units of writable block size, or in other words, each single write is sized based on the layout of blocks for each of the memory cards as part of the write operation).
It would have been obvious to a person having ordinary skill in the art to modify claims 1-18 of US 10564882 with the individual device write block size determination of Otsuka as storage system performance and reliability can be improved by allowing for writes to meet the minimum guaranteed recording rate by ensuring writes are integral multiples of the writable block size of the storage devices (See Otsuka, [0039]-[0042]).
Further, many of the dependent claims of the instant application have corresponding dependent claims with identical claim limitation wording.
Claims 3, 10 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, and 13 of U.S. Patent No. 10564882 in view of Otsuka, further in view of Hayes et al (US 8868825). Claims 3, 10 and 17 are fully disclosed by claims 1, 5, and 9 of US Patent 10564882 in view of Otsuka except for the physical address referring to the location in the storage device for the entire life of the storage device. However, Hayes discloses write address referring to the location in the storage device for the entire life of the storage device (See Hayes, Col. 1, lines 29-32, disclosing use of nonrepeating addresses which exceed the maximum number of addresses expected to be applied during a lifespan of the storage device).
It would have been obvious to a person having ordinary skill to modify US 10564882 with the non-repeating addresses of Hayes as it enhances the ability to write to pages in flash memory, and for reading the flash memory to recover a previous version of user data (See Hayes, Col 3, lines 53-56).
Claims 1-4, 6, 8-11, 13, 15-18 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 11010080 in view of Otsuka. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the instant application are fully disclosed by claims 1-18 of US 11010080 except for the write size is for a single write operation wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller. However, Otsuka discloses the write size is for a single write operation wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller (See Otsuka, [0046], disclosing obtaining the writable block size from multiple memory cards which may of a different writable block size and writes data taking into account the proper write block size for each memory card in units of writable block size, or in other words, each single write is sized based on the layout of blocks for each of the memory cards as part of the write operation).
It would have been obvious to a person having ordinary skill in the art to modify claims 1-18 of US 11010080 with the individual device write block size determination of Otsuka as storage system performance and reliability can be improved by allowing for writes to meet the minimum guaranteed recording rate by ensuring writes are integral multiples of the writable block size of the storage devices (See Otsuka, [0039]-[0042]).
Further, many of the dependent claims of the instant application have corresponding dependent claims with identical claim limitation wording.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-7, 9, 11-14, 15-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Borchers et al (2010/0262773A1, hereinafter Borchers) in view of Koseki et al (US 2013/0205070 A1, hereinafter Koseki), in view of Kimura et al (US 2012/0072680 A1, hereinafter Kimura), and further in view of Otsuka et al (US 20070183198 A1, hereinafter Otsuka).
Regarding claims 1, 8, and 15, taking claim 8 as exemplary, Borchers discloses a storage system, comprising: (See Borchers, Fig. 1 and [0018], disclosing data storage device 100):
a plurality of storage devices (See Borchers Fig. 1 and [0018], “the memory boards 103a and 104b may include multiple flash memory chips 118a and 118b on each of the memory boards”); and
a storage array controller operatively coupled to the plurality of storage device, the storage array controller comprising a processing device, the processing device to (See Borchers, Fig. 1 and [0020], disclosing controller board 102 and [0021] & [0022] disclosing controller board 102 coupled to memory boards 104a and 104b):
determine a write size based on information describing a layout of memory in a storage device of the plurality of storage devices (See Borchers [0078], “determine an appropriate channel chunk size” based on “the page size used to write data to the flash memory chips”) and
send a write request to store data at a location of the storage device, wherein the write request is associated with the determined write size (See Borchers [0040] disclosing the controller handling address translation from host logical to actual physical addresses in the flash memory chips where data is to be written to or read from and [0044] disclosing processing commands include programming a flash page and [0078], “determine an appropriate channel chunk size” based on “the page size used to write data to the flash memory chips” and “determine a first chip chunk size with which to write data to flash memory chips” and [0079], disclosing writing data to the storage device 501 using a chip striping technique where data is segmented in chip chunk size units for writing to the chips)
and wherein the write request includes a physical address of the location in the storage device to store the data (See Borchers, [0040] disclosing the controller handling address translation from host logical to actual physical addresses in the flash memory chips where data is to be written to or read from and [0044] disclosing processing commands include programming a flash page, or in other words, a write request to a storage location and [0062] disclosing translation of logical addresses into a physical address including a particular channel, a particular flash memory chip, and particular physical block address of the specified chip).
Borchers does not disclose receiving information describing a layout of memory in a storage device operatively coupled to a processing device of a storage array controller, the information sent by the storage device to the storage array controller and determining, by the storage array controller, responsive to the storage array controller receiving the information, a write size for a single write operation based on the received information.
However, Koseki discloses receiving information describing a layout of memory in a storage device operatively coupled to a processing device of a storage array controller, the information sent by the storage device to the storage array controller, responsive to the storage array controller receiving the information, a write size based on the received information (See Koseki, [0180] & [0185], disclosing the SSD device notifying and providing the storage controller 100 of internal information including Table Area 23000 having a logical to physical conversion TBL 23100 and statistics information management TBL 23200, the TBL 23100 having a starting position of an LBA, a Chunk #23102, a Block #23103, and Page #23104 and [0224]-[0229], disclosing storage controller 100 receiving internal information 25000 from SSD 700, the storage controller determining whether there is enough dispersion of a write amount between SSDs (a total write amount 13105 being equalized or not) and executing inter-device WL or not, or in other words, sizing the writes, required of wear-leveling, to be zero, or greater than zero, based on the received internal information).
Borchers and Koseki are analogous art as they are both directed to improved storage management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the adjustable storage write of Borchers with the offloading to an array controller of Koseki as host system performance can be improved by allowing the storage array controller to make the determination of the necessity of performing wear leveling and allowing the host processors to perform other functionality.
Neither Borchers nor Koseki expressly disclose wherein the information comprises a size of a writeable memory unit of the storage device and a size of an erasable memory unit of the storage device. Koseki does disclose an SSD flash memory erase is executed in a unit of a block and write is executed in a unit of a page (See Koseki [0067] & [0097]) and the SSD notifying the storage controller of SSD internal information including a start address that is managed by a multiple number of a page size (See Koseki [0185]).
However, Kimura discloses wherein the information comprises a size of a writeable memory unit of the storage device and a size of an erasable memory unit of the storage device (See Kimura, [0052], the RAID controller obtains from each of the SSDs information including a block size, the number of blocks, and the page size).
Borchers, Koseki, and Kimura are analogous art directed to improved storage management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the adjustable write storage system of Borchers and Koseki with the device specification of Kimura as storage system reliability can be improved by ensuring the controller correctly identifies storage drive parameters for operation.
None of Borchers, Koseki, or Kimura disclose determining a write size for a single write operation based on the information describing the layout of memory in the storage device, wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller.
However, Otsuka discloses determining a write size for a single write operation based on the information describing the layout of memory in the storage device, wherein the write size determined for the storage device differs from another write size determined for a further storage device coupled to the storage array controller (See Otsuka, [0046], disclosing obtaining the writable block size from multiple memory cards which may of a different writable block size and writes data taking into account the proper write block size for each memory card in units of writable block size, or in other words, each single write is sized based on the layout of blocks for each of the memory cards as part of the write operation).
Borchers, Koseki, Kimura, and Otsuka are analogous art directed to improved data storage management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the adjustable write storage system of Borchers, Koseki, and Kimura with the individual device block sizes of Otsuka as storage system performance and reliability can be improved by allowing for writes to meet the minimum guaranteed recording rate by ensuring writes are integral multiples of the writable block size of the storage devices (See Otsuka, [0039]-[0042]).
Regarding claims 2, 9, and 16, taking claim 9 as exemplary, Borchers in view of Koseki, in view of Kimura, further in view of Otsuka disclosed the storage system of claim 8 as disclosed hereinabove. Borchers further discloses wherein the write request causes the storage device to store the data at the location (See Borchers [0040] disclosing the controller handling address translation from host logical to actual physical addresses in the flash memory chips where data is to be written to or read from and [0044] disclosing processing commands include programming a flash page and [0078], “determine an appropriate channel chunk size” based on “the page size used to write data to the flash memory chips” and “determine a first chip chunk size with which to write data to flash memory chips” ).
Regarding claims 4, 11, and 18, taking claim 11 as exemplary, Borchers in view of Koseki, in view of Kimura, further view of Otsuka disclosed the storage device of claim 8 as described hereinabove. Borchers further discloses wherein writes to the storage device and the further storage device are performed in parallel (See Borchers, [0077], “chip striping provides maximum parallelism in read and write operations”) and wherein the information sent by the storage device to the storage array controller is responsive to the storage array controller detecting addition of the storage device (See Borchers, [0058], configuration detection engine used by host to discover hardware device properties of the data storage device…the configuration detection engine can issue query command to the storage device and in response to the query command the data storage device can return information including the size of each flash chip).
Regarding claims 5, 12, and 19, taking claim 12 as exemplary, Borchers in view of Koseki, in view of Kimura, further in view of Otsuka disclosed the storage device of claim 8 as described hereinabove. Kimura further discloses wherein the size of the writeable memory unit in the storage device is less than the size of the erasable memory unit in the storage device (See Kimura, [0005], NAND flash memory is block-erase type device and [0033], a plurality of pages form a storage unit called a block and read/write is performed in a unit of a page, or in other words, the size of a page/write unit is smaller than the size of a block/erase unit as multiple pages form a block).
Regarding claim 6 and 13, taking claim 13 as exemplary, Borchers in view of Koseki, in view of Kimura, further in view of Otsuka disclosed the storage device of claim 12 as described hereinabove. Borchers further discloses wherein the write size corresponds to the size of the writeable memory unit in the storage device (See Borchers [0078], “determine an appropriate channel chunk size” based on “the page size used to write data to the flash memory chips” and “determine a first chip chunk size with which to write data to flash memory chips”).
Regarding claims 7, 14, and 20, taking claim 14 as exemplary, Borchers in view of Koseki, in view of Kimura, further in view of Otsuka disclosed the storage device of claim 8 as described hereinabove. Kimura further discloses wherein multiple erasable memory units are written in parallel (See Kimura, [0039], disclosing simultaneously selecting the set of blocks constituting an error correction code, assigning an unused stripe number to the blocks, and pieces of data are striped across the pages of the blocks and [0040], the time at which the pieces of data to be used for generating an ECC for one stripe are stored altogether is the time at which the predetermined number of pieces of data are stored altogether, or in other words, parallel).
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Borchers et al (2010/0262773A1, hereinafter Borchers) in view of Koseki et al (US 2013/0205070 A1, hereinafter Koseki), in view of Kimura et al (US 2012/0072680 A1, hereinafter Kimura), and further in view of Otsuka et al (US 2007/0183198 A1, hereinafter Otsuka), and even further in view of Hayes et al (US8868825, hereinafter Hayes).
Regarding claims 3, 10, and 17, taking claim 10 as exemplary, Borchers in view of Koseki, in view of Kimura, and in view of Otsuka disclosed the storage system of claim 8 as described hereinabove. None of Borchers, Koseki, Kimura, or Otsuka disclose wherein the physical address refers to the location in the storage device for an entire life of the storage device.
However, Hayes discloses wherein the physical address refers to the location in the storage device for an entire life of the storage device (See Hayes, Col. 1, lines 29-32, disclosing use of nonrepeating addresses which exceed the maximum number of addresses expected to be applied during a lifespan of the storage device).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the storage system of Borchers, Koseki, Kimura, and Otsuka with the non-repeating addresses of Hayes as storage system performance and data reliability can be improved as it enhances the ability to write to pages in flash memory, and for reading the flash memory to recover a previous version of user data (See Hayes, Col 3, lines 53-56).
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.H.K/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137