The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim(s) 1 and 3-25 has/have been examined.Claim(s) 1 and 3-25 have been rejected.
Novel Subject Matter
The claims recite novel subject matter while being rejected as lacking enablement, lacking written description, and being directed to non-statutory subject matter. Within each claim as a whole the examiner deems the novel limitation to be using a truncated or less-than-full set of an assignment matrix elements to perform error mitigation.
Response to Arguments
The arguments submitted December 22, 2025 have been fully considered but are not persuasive.
Regarding the 101 rejection, Applicant argues that the claims are directed to a technical solution to a technical problem. Applicant argues that the system provides improvement in the technology related to reduction in system usage and improving noisy data received from a quantum system. The examiner respectfully disagrees.
The MPEP states that “The judicial exception alone cannot provide the improvement.” (See MPEP 2106.05(a).) In this case all the claimed improvements are provided by the judicial exception alone. Performing error mitigation, which entails generating noise-free data, is a result of a process that is may be performed by a human mind with the aid of pen and paper. Applicant has argued unclaimed improvements of performing error mitigation more efficiently, but this too is an aspect of the judicial exception. Neither the algorithm itself nor the improvement to the algorithm (if it can be performed as a mental process) is considered an improvement that integrates the judicial exception into a practical application.
Specification
The specification filed May 7, 2021 is objected to because the title is not descriptive of the claimed invention.
The specification is also objected to because paragraph 059 line 4 includes a grammar error. The incomplete sentence “error mitigation” should be removed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “determination component” in claims 1, and 23, “computation component” in claims 1, 3-7, 22 and 24, “an iterative solver” in claims 1, 6-8,13-15, 20, 21, and 24, “a system” in claims 8-14, “a function evaluator” in claim 5, 12, and 19, and “a preconditioner” in claims 7, 14, and 21.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 and 3-25 is/are rejected under 35 U.S.C. 101 as being directed to an abstract idea without significantly more.
Below is an evaluation using the 2019 Revised Patent Subject Matter Eligibility Guidance.
Regarding claim 1, Step 1 is satisfied because computer executable operations form a processes.
At step 2a prong 1, an abstract idea is recited: steps of the claim could be performed as a mental process. These steps include (processing of a) determination component that obtains, from a quantum system, noisy measurement data comprising observed bitstring data; and (processing of a ) computation component that receives the observed bitstring data; and performs error mitigation employing an iterative solver and employing less than a full set of assignment matrix (A-matrix) elements that are computed employing data from the observed bitstrings.
At step 2a prong 2, additional elements that integrate the judicial exception into a practical application are not recited.
The claim recites use of a memory and processor and a classical system. These are generic components and do not integrate the judicial exception into a practical application because the limitations serve only to implement the abstract idea on a computer or merely uses a computer in its ordinary capacity as a tool to perform an existing process. See MPEP §§ 2106.04(d), 2106.05(f)(2).
The claim recites that the data is received from one or more qubits of a quantum system. This quantum system data source is separate from the performance of the judicial exception (see, for example Figure 4 and paragraph 72 of the application where the quantum processor is separate from the error mitigation system). Because the quantum system is not integrated into to the performance of the judicial exception, the limitation does not integrate the judicial exception into a practical application and instead only generally links the judicial exception to a particular technological environment or field of use. See MPEP §§ 2106.04(d), 2106.05(h).
. At step 2b, additional elements that may amount to significantly more than the judicial exception are not recited.
The claim recites use of a memory and processor and a classical system. These limitations do not amount to significantly more than the judicial exception because they amount to adding the words “apply it” (or an equivalent) with the judicial exception, or merely uses a computer in its ordinary capacity as a tool to perform an existing process. See MPEP § 2106.05(f)(2).
The claim recites that the data is received from one or more qubits of a quantum system. The use of a quantum systems is separate from the performance of the judicial exception (see, for example Figure 4 and paragraph 72 of the application where the quantum processor is separate from the error mitigation system). Because of this separation, the use of the quantum system amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP § 2106.05(g). Furthermore the quantum system is well‐understood, routine, and conventional (see, for example, attached reference Wikipedia’s Quantum Computer which describes how quantum computing began in 1980s, has been in ongoing experimental progress since the late 1990s, and that various quantum computers have been created since then). See MPEP § 2106.05(d).
Regarding claims 3-7, 9-14, 16-21, 23 and 25, these claims recite additional limitations of the mental process but their inclusion does not push the mental process beyond what can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper. See MPEP § 2106.04(a)(2)(III). The claims do not recite additional elements which must be evaluated in step 2a prong 2 or step 2b.
Regarding claim 8, Step 1 is satisfied because a method is a process. At step 2a prong 1, an abstract idea is recited including steps as described for claim 1, above. At step 2a prong 2 and step 2b, additional elements of a processor, a quantum system, and a classical system are recited. These elements do not integrate the judicial exception or amount to significantly more than the judicial exception for the same reasons as described above for claim 1.
Regarding claim 15, Step 1 is satisfied because computer executable operations form a processes. At step 2a prong 1, an abstract idea is recited including steps as described for claim 1, above. At step 2a prong 2 and step 2b, additional elements of a processor, a quantum system, and a classical system are recited. These elements do not integrate the judicial exception or amount to significantly more than the judicial exception for the same reasons as described above for claim 1.
Regarding claim 22, Step 1 is satisfied because computer executable operations form a processes. At step 2a prong 1, an abstract idea is recited including performing error mitigation employing less than a full set of assignment matrix (A-matrix) elements that are computed employing data from observed bitstrings. At step 2a prong 2 and step 2b, additional elements of a memory, a processor, a classical system and one or more qubits are recited. These elements do not integrate the judicial exception or amount to significantly more than the judicial exception for the same reasons as described above for claim 1. The examiner notes that qubits are fundamental elements of quantum computing, and are addressed in steps 2a prong 1 and 2b using the same reasoning as was applied to quantum system in claim 1.
Regarding claim 24, this claim recites very similar limitations to claim 22 and is rejected on the same grounds as claim 22. The examiner notes that an iterative solver is an algorithm function (see paragraphs 66 and 102 of the specification) and can be implemented by the human mind with the aid of pen and paper.
Claim Objections
Claim 1, the last line recites the limitation “the observed bitstrings”. This limitation lacks antecedent basis and should read “the observed bitstring data” to correspond with the language on line 6.Claim 8, the last line, recites the limitation “the observed bitstrings” and should be changed as describe for claim 1, above.Claim 15, the last line, recites the limitation “the observed bitstrings” and should be changed as describe for claim 1, above.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1 and 3-25 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Note that dependent claims not specifically addressed below inherit the deficiency of the parent claim and do not remedy the issue.
Regarding claim 1, the claim recites "performs error mitigation... employing less than a full set of assignment matrix (A-matrix) elements". This "less than a full set of A-matrix elements" which is used in error mitigation is not described in the specification in such a way to enable one skilled in the art to make and/or use the invention.
In generating the less than full set of A-matrix elements, the specification (Figure 9) describes three steps to convert a noisy bitstream to a less than full set of A-Matrix Elements: "employing a renormalization factor", "determine calibration values" and finally "employ a function evaluator to compute the less than full set of A-Matrix elements".
The step of "employing a renormalization factor" is described in paragraph 91. This description is sufficient.
The step of "determine calibration values" is described in paragraph 95. Calibration data can include calibration matrices that can be employed per qubit. This description is vague. One skilled in the art may infer that the calibration values indicate scalars for bits in the bitstream, but the generation of these values in a way that results in a usable truncated A-Matrix would not be clear to one of skill in the art without undue experimentation.
The step of "employ a function evaluator" is described in paragraphs 94 and 112. Paragraph 94 recites that the function evaluator is applied to calculate the truncated set of A-matrix elements. The function eval may be comprised by the A-matrix element model or be stored elsewhere. And the functional eval can be shown by Equation 1: A[i,j] = f(row bits, col bits, cals) (in paragraph 96). Paragraph 112 mentions that the function evaluator "can employ the one or more calibration factors".
The discussion of the function evaluator in the specification provides no detail as to its implementation. The algorithm behind the function evaluator remains a black box. One reasonably skilled in the art would not be able to determine, without undue experimentation, how the function evaluator takes parameters of row bits, column bits, and calibration data, and generates a truncated A-Matrix which is useable for error mitigation.
Because the generation of calibration values is unknown and the function generator which utilizes the calibration values is a black box, the process of generating a usable truncated A-Matrix would not be clear to one of skill in the art. Because the (useable) truncated A-Matrix cannot be generated, the specification does not allow one of skill in the art to make and/or use the invention.
Claims 8, 15 and 22 recite the same limitations that are addressed above for claim 1 and are rejected for the same reason as claim 1.
Claim 24 recites "performs error mitigation on a classical system... using a truncated set of assignment matrix (A-matrix) elements as an initial input". A truncated set has a similar scope to "less than a full set" and this claim is rejected for the same reason as claim 1.
Claims 1 and 3-25 are rejected under 35 U.S.C. 112(a) as lacking written description.
Claims 1, 6-8,13-15, 20, 21, and 24 recite "an iterative solver" which fulfills the 3-prong test for being interpreted as invoking 35 U.S.C. 112(f). See MPEP 2181. The limitation is a generic placeholder that is modified by functional language, and is not further modified in the claim by a definite structure or material for performing the claimed function. The specification does not provide for a particular structure or algorithm that embodies this limitation. The claim therefore lacks written description support for this limitation.
Claims 5, 12 and 19 recite “a function evaluator” which fulfills the 3-prong test for being interpreted as invoking 35 U.S.C. 112(f). See MPEP 2181. The limitation is a generic placeholder that is modified by functional language, and is not further modified in the claim by a definite structure or material for performing the claimed function. The specification does not provide for a particular structure or algorithm that embodies this limitation. The claim therefore lacks written description support for this limitation.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1 and 3-25 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Note that dependent claims not specifically addressed below inherit the deficiency of the parent claim and do not remedy the issue.
Claims 1, 6-8,13-15, 20, 21, and 24 recite "an iterative solver" which invokes 35 U.S.C. 112(f) but lacks support in the specification to limit the interpretation of the term. (See the 35 U.S.C. 112(a) rejection above.) A limiting structure (or algorithm for software) cannot be found to embody this limitation and guide its interpretation when examining the claim. The element is therefore indefinite.
Claims 5, 12 and 19 recite “a function evaluator” which invokes 35 U.S.C. 112(f) but lacks support in the specification to limit the interpretation of the term. (See the 35 U.S.C. 112(a) rejection above.) A limiting structure (or algorithm for software) cannot be found to embody this limitation and guide its interpretation when examining the claim. The element is therefore indefinite.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen teaches analyzing quantum noise using first and second dynamic map eigenspectrum structures based on a correspondence between quantum output states and quantum initial states of first and second circuits having different numbers of noise evolution gates. Van den Berg teaches mitigating readout errors using normalization scalar values determined from calibration data based on a first circuit output and from estimation scalar values based on estimation data from a second readout. Lee teaches error correction of read codewords utilizing a partial sub-matrix structure determined based on multiple symbols.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH SCHELL whose telephone number is (571) 272-8186. The examiner can normally be reached on Monday through Friday 9AM-5:00PM (Pacific Time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. The fax phone number for the examiner is 571-273-8186. The examiner may be e-mailed at joseph.schell@uspto.gov though communications via e-mail are not permitted without a written authorization form (see MPEP 502.03).
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JS/JOSEPH O SCHELL/Primary Examiner, Art Unit 2114