DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because the abstract “…encoding traffic between a host and a DLA.” The first instance of “DLA” as an acronym should be spelled out. Correction is required. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 8-14, 17, and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2,
Claim 2 specifies that “wherein the DLA is further configured to decode the encoded data utilizing the decoder comprising a first artificial neural network (ANN).” However, claim 1, upon which claim 2 depends, also specifies “decode the encoded data utilizing an autoencoder wherein the encoded data is decoded by a decoder of the autoencoder implemented by the DLA to generate decoded data and wherein the decoder of the autoencoder is implemented as an artificial neural network (ANN);” Claim 1 and claim 2 both specify decoding encoding data, where claim 1 specifies the decoding is done using an autoencoder implemented by the DLA as an ANN while claim 2 specifies that the decoding is done utilizing a first ANN. It is unclear if the first ANN of claim 2 is the same ANN as the claimed and specified in claim 1 and if this first ANN is part of the autoencoder of the DLA as specified in claim 1, or if it is a separate and different ANN entirely. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this office action, it is interpreted that “a first ANN” of claim 2 is the same “ANN” described in claim 1.
Dependent claim 3 is rejected for including the same indefinite subject matter of dependent claim 2 upon which claim 3 depends.
Regarding claim 8:
Claim 8 recites the limitation "signaling indicative of first data that comprises the hyperparameters to configure an artificial neural network (ANN)," in lines 3-4 of the claim. There is insufficient antecedent basis for this limitation in the claim. It is unclear to what “the hyperparameters” are for which the claim is specifying, and if they are referring to preexisting hyperparameters of the ANN, previously described and claimed hyperparameters, or if the claim is simply describing that the data comprises hyperparameters. Therefore claim 8 is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this office action the claim is interpreted as specifying that the data comprises hyperparameter’s.
Dependent claims 9-14 are rejected for containing the same indefinite subject matter of claim 8 upon which claim 9-14 depend.
Regarding claim 17:
Claim 17 recites the limitation " a controller of the memory device configured to store the encoded output in the array of the memory device." in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. It is unclear if “the array of the memory device” is the same as the “array of memory cells” as claimed and specified in claim 15 upon which claim 23 depends or if it’s a different and separate memory array. Therefore, claim 17 is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this office action the “the array of the memory device” is interpreted as being the “array of memory cells” as claimed and specified in claim 15.
Regarding claim 23:
Claim 23 recites the limitation "wherein the host is further configured to retrieve the encoded output from the memory array and decode the encoded output utilizing a different decoder," in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. It is unclear if “the memory array” is the same as the “array of memory cells” as claimed and specified in claim 15 upon which claim 23 depends or if it’s a different and separate memory array. Therefore, claim 23 is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this office action the “memory array” is interpreted as being the “array of memory cells” as claimed and specified in claim 15.
Allowable Subject Matter
Claims 1, 4-7, and 15-16, and 18-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
As per claim 1:
Though Mandlekar et al., (US 2022/0055689 A1), part of the prior art made of record, teaches the use of an autoencoder in paragraph [0082] through the use of an autoencoder for states of a model, and the use of an accelerator with a neural network and memory in paragraph [0167] through the use of an accelerator with on-chip memory to accelerate an neural network.
And though Mousavian et al., (US 2020/0361083 A1), part of the prior art made of record, teaches the use of an accelerator with a neural network and memory in paragraph [0192] through the use of an accelerator with on-chip to accelerate a neural network.
The primary reason for marking of allowable subject matter of independent claim 1, in the instant application, is the combination with the inclusion in these claims of the limitations of an apparatus comprising:
“an array of memory cells; a deep learning accelerator (DLA) coupled to the array; and a controller coupled to the array and to the DLA, wherein the controller is configured to: receive encoded data from a host; store the encoded data in the array; and wherein the DLA is configured to: responsive to receiving signals from the controller, access the encoded data from the array; decode the encoded data utilizing an autoencoder wherein the encoded data is decoded by a decoder of the autoencoder implemented by the DLA to generate decoded data and wherein the decoder of the autoencoder is implemented as an artificial neural network (ANN); and perform a plurality of operations on the decoded data.”
The prior art of made of record above neither anticipates nor renders obvious the above-recited combinations. Specifically, though the prior art of made of record does teach the use of an accelerator with a neural network, an autoencoder, and the use of memory with an accelerator and a neural network it does not teach an array of memory cells; a deep learning accelerator (DLA) coupled to the array; and a controller coupled to the array and to the DLA, wherein the controller is configured to: receive encoded data from a host; store the encoded data in the array; and wherein the DLA is configured to: responsive to receiving signals from the controller, access the encoded data from the array; decode the encoded data utilizing an autoencoder wherein the encoded data is decoded by a decoder of the autoencoder implemented by the DLA to generate decoded data and wherein the decoder of the autoencoder is implemented as an artificial neural network (ANN); and perform a plurality of operations on the decoded data.
Dependent claim(s) 4-7 are allowable at least for the reasons recited above as including all of the limitations of the allowable independent base claim 1 upon which claims 4-7 depend.
As per claim 15:
Though Mandlekar et al., (US 2022/0055689 A1), part of the prior art made of record, teaches the use of an autoencoder in paragraph [0082] through the use of an autoencoder for states of a model, and the use of an accelerator with a neural network and memory in paragraph [0167] through the use of an accelerator with on-chip memory to accelerate an neural network.
And though Mousavian et al., (US 2020/0361083 A1), part of the prior art made of record, teaches the use of an accelerator with a neural network and memory in paragraph [0192] through the use of an accelerator with on-chip to accelerate a neural network.
The primary reason for marking of allowable subject matter of independent claim 15, in the instant application, is the combination with the inclusion in these claims of the limitations of an system comprising:
“a host; a memory device comprising a deep learning accelerator (DLA) and an array of memory cells and wherein the DLA comprises a decoder of an autoencoder and an artificial neural network (ANN); wherein the host is configured to: encode a first set of data to generate encoded data, wherein the first set of data is encoded by an encoder of the autoencoder, wherein the encoder is implemented by the host; and provide the encoded data from the host to the DLA of the memory device to cause the DLA to process a second set of data, corresponding to the first set of data, utilizing the ANN; wherein the DLA is configured to: decode the encoded data, utilizing the decoder of the autoencoder, to generate a second set of data that corresponds to the first set of data; and process the second set of data utilizing the ANN.”
The prior art of made of record above neither anticipates nor renders obvious the above-recited combinations. Specifically, though the prior art of made of record does teach the use of an accelerator with a neural network, an autoencoder, and the use of memory with an accelerator and a neural network it does not teach a memory device comprising a deep learning accelerator (DLA) and an array of memory cells and wherein the DLA comprises a decoder of an autoencoder and an artificial neural network (ANN); wherein the host is configured to: encode a first set of data to generate encoded data, wherein the first set of data is encoded by an encoder of the autoencoder, wherein the encoder is implemented by the host; and provide the encoded data from the host to the DLA of the memory device to cause the DLA to process a second set of data, corresponding to the first set of data, utilizing the ANN; wherein the DLA is configured to: decode the encoded data, utilizing the decoder of the autoencoder, to generate a second set of data that corresponds to the first set of data; and process the second set of data utilizing the ANN.
Dependent claim(s) 16, and 18-22 are allowable at least for the reasons recited above as including all of the limitations of the allowable independent base claim 15 upon which claims 16-22 depend.
Would Be Allowable Subject Matter
Claims 2-3 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 8-14 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of would be allowable subject matter:
As per claim 8:
Though Mandlekar et al., (US 2022/0055689 A1), part of the prior art made of record, teaches the use of an autoencoder in paragraph [0082] through the use of an autoencoder for states of a model, and the use of an accelerator with a neural network and memory in paragraph [0167] through the use of an accelerator with on-chip memory to accelerate an neural network.
And though Mousavian et al., (US 2020/0361083 A1), part of the prior art made of record, teaches the use of an accelerator with a neural network and memory in paragraph [0192] through the use of an accelerator with on-chip to accelerate a neural network.
The primary reason for marking of would be allowable subject matter of independent claim 8, in the instant application, is the combination with the inclusion in these claims of the limitations of a method comprising:
“receiving, from a host at a deep learning accelerator (DLA) of a memory device, signaling indicative of first data that comprises the hyperparameters to configure an artificial neural network (ANN), wherein the ANN is implemented by the DLA; receiving encoded second data from the host at the DLA of the memory device, wherein the second data is generated by a plurality of sensors and is encoded by an encoder of an autoencoder implemented by the host; decoding the encoded second data to generate decoded second data, wherein the decoding comprises utilizing a decoder of the autoencoder and wherein the decoder is implemented by the DLA; processing the decoded second data utilizing the ANN; and transmitting, to the host, an encoded output of the ANN.”
The prior art of made of record above neither anticipates nor renders obvious the above-recited combinations. Specifically, though the prior art of made of record does teach the use of an accelerator with a neural network, an autoencoder, and the use of memory with an accelerator and a neural network it does not teach receiving, from a host at a deep learning accelerator (DLA) of a memory device, signaling indicative of first data that comprises the hyperparameters to configure an artificial neural network (ANN), wherein the ANN is implemented by the DLA; receiving encoded second data from the host at the DLA of the memory device, wherein the second data is generated by a plurality of sensors and is encoded by an encoder of an autoencoder implemented by the host; decoding the encoded second data to generate decoded second data, wherein the decoding comprises utilizing a decoder of the autoencoder and wherein the decoder is implemented by the DLA; processing the decoded second data utilizing the ANN; and transmitting, to the host, an encoded output of the ANN.
Dependent claim(s) 9-14 are marked as would be allowable at least for the reasons recited above as including all of the limitations of the would be allowable independent base claim 8 upon which claims 9-14 depend.
Claims 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 23 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Mandlekar et al., (US 2022/0055689 A1), part of the prior art made of record, teaches the use of an autoencoder in paragraph [0082] through the use of an autoencoder for states of a model, and the use of an accelerator with a neural network and memory in paragraph [0167] (of claims 1, 8, and 15 of the instant application) through the use of an accelerator with on-chip memory to accelerate an neural network.
Mousavian et al., (US 2020/0361083 A1), part of the prior art made of record, teaches the use of an accelerator with a neural network and memory in paragraph [0192] (of claims 1, 8, and 15 of the instant application) through the use of an accelerator with on-chip to accelerate a neural network.
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SHANE D. WOOLWINE
Primary Examiner
Art Unit 2124
/SHANE D WOOLWINE/Primary Examiner, Art Unit 2124