Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
First, it is noted that the previous rejection of claim 30 as lacking proper antecedent basis for the limitation “the first layer” is overcome by Applicant’s amendment filed on 1/8/2026. It is further noted that claim 30 remains rejected under 112(b) for different, previously-applied reasons as outlined below:
Claims 1, 3, 5-11 and 27-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, it is first noted that all of these claims refer to “a first modulus” and “a second modulus”. However, the claim does not specify which modulus is intended to be referred to. For purposes of examination, it will be assumed that the claims refer to the Young’s modulus of the material.
Additionally, it is noted that the references to “a first modulus” and “a second modulus” do not provide any context for the temperature at which the moduli are to be measured. It is known that Young’s modulus and other moduli are temperature-dependent measurements, and therefore since the claim lacks a temperature reference by which to understand the particular claimed ranges for the moduli, the scope of the claim is unclear. For purposes of examination, it will be assumed that the moduli can be measured at any temperature.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eliason et al. (US Patent # 8963343) with evidence supporting the determination of anticipation provided by Lee et al. (US Patent Publication 2023/0139299) and Sugawara et al. (US Patent Publication 20050184637).
Regarding claim 1 (As best understood), Fig. 2G of Eliason et al. discloses a packaged semiconductor device, comprising:
a semiconductor die 206 with a component (included in the ICs formed thereon) proximate to a surface of the semiconductor die (Col. 3, Lines 10-40);
the semiconductor die 206 mounted on a substrate (208 paddle/lead frame – see Fig. 2G and Col. 3, Lines 30-35);
the component covered with a first polymer layer 224 with a first modulus (EM-710, 3MPa, as evidenced by [0035] of Lee et al. (US Patent Publication 2023/0139299);
at least a portion of the first polymer layer 224 (die-attach adhesive – Col. 5, Lines 25-40) covered by at least one second polymer layer 216 (Polyimide – Col. 5, Lines 30-31) with a second modulus (3GPa, as evidenced by [0063] of Sugawara et al. (US Patent Publication 20050184637) and the second modulus is greater than the first modulus; and
the semiconductor die 206 and a portion of the substrate (208 paddle/lead frame) covered with mold compound 228 (see Fig. 2G and Col. 5, Lines 1-5).
Regarding claim 3 (As best understood), Fig. 2G of Eliason et al. discloses the PSD of claim 1, where the first polymer layer 224 and the second polymer layer 216 have vertical sidewalls (see Figs. 2G and 2D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Eliason et al.
Regarding claim 5 (As best understood), Eliason et al. discloses the PSD of claim 1, where the first polymer layer 224 covers the component (see Fig. 2G and Col. 4, Lines 49-55 – stress buffer die 218 is attached by die attach layer 224 to overlie integrated circuit 202 which contains components) but fails to disclose that the polymer layer covers the surface of the semiconductor die surrounding the component to a distance of at least 20µm.
It would have been obvious to one of ordinary skill in the art at the time of the invention to ensure that the first polymer layer 224 (and the stress buffer that it attaches) surround the component by a reasonably significant distance in order to ensure that the component is sufficiently isolated from the stress caused by the curing of the encapsulation layer (see Eliason, Background).
Claims 6, 8, 27, 28 and 31-35 are rejected under 35 U.S.C. 103 as being unpatentable over Eliason et al. in view of Katou et al. (US Patent 8975161) with additional evidence for claims 32-35 provided by Zhou et al. (US Patent 9842662).
Regarding claims 6, 8, 27, 28 and 31 (As best understood), Eliason et al. discloses the PSD of claims 1 and 5, wherein the second modulus is between 2 and 4 GPa (3GPa – see rejection above), but fails to teach that the first modulus (of the die-attach film) is between .1 and 1 GPa, and that the first polymer layer is formed of an epoxy material.
Katou et al. teaches a similar die-attach/die bonding epoxy (FH900 – Col. 9, Lines 25-35) having a modulus of between .1 and 1 GPa (as evidenced by [0035] of Lee et al. (US Patent Publication 2023/0139299) – FH900, 200MPa, or .2GPa).
It would have been obvious to substitute the die-attach film taught by Katou et al. for the die attach film of Eliason et al. based on its disclosed suitability for use as a die-bonding film (as taught by Katou et al.). Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding claims 32-35 (As best understood), Eliason et al. discloses that the component includes CMOS circuits, nonvolatile memory and F-RAM devices (Col. 3, Lines 10-30).
It is known in the art that these circuits include devices formed in, on and at the surface of the substrate and further include layers of conductors and insulating dielectric layers. (See evidence provided by Zhou et al., US 9842662, Fig. 1b including Transistor (14, 16, 17, 19))
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Eliason et al. in view of Ye et al. (US Patent 9773766).
Regarding claim 7 (As best understood), Eliason et al. discloses the PSD of claim 5, but fails to disclose wherein the first polymer layer has a thickness of 5-20µm or wherein the second polymer layer has a thickness between 2 and 10 µm. Eliason does not disclose a thickness for the first polymer layer, and for the second polymer layer discloses a range of 1-100µm (Eliason et al., Col. 4, Lines 45-48).
Regarding the second polymer layer, it is noted, however, that because the claimed range lies inside of the disclosed range, a prima facie case of obviousness exists.
Regarding the first polymer layer, Ye et al. discloses a similar die attach film formed of the same material wherein the thickness of the die attach film is disclosed to be between 5 and 20 µm thick. (Ye et al., Col. 6, Lines 38-47).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the thickness taught by Ye et al. into the device of Eliason et al. for the purpose of knowing how thick to form the die attach film.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Eliason et al. and Katou et al. further in view of Ye et al. (US Patent 9773766).
Regarding claim 29 (As best understood), the combination of Eliason et al. and Katou et al. disclose the PSD of claim 27, but fail to disclose wherein the first polymer layer has a thickness of 5-20µm or wherein the second polymer layer has a thickness between 2 and 10 µm. Eliason et al. and Katou et al. do not disclose a thickness for the first polymer layer, and for the second polymer layer Eliason et al. discloses a range of 1-100µm (Eliason et al., Col. 4, Lines 45-48).
Regarding the second polymer layer, it is noted, however, that because the claimed range lies inside of the range disclosed by Eliason et al., a prima facie case of obviousness exists. There is currently no further evidence of criticality for the specific sub-range of 2-10µm.
Regarding the first polymer layer, Ye et al. discloses a similar die attach film formed of the same material wherein the thickness of the die attach film is disclosed to be between 5 and 20 µm thick. (Ye et al., Col. 6, Lines 38-47).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the thickness taught by Ye et al. into the device of Eliason et al. and Katou et al. for the purpose of knowing how thick to form the die attach film.
Claims 9-11 are rejected under 35 USC 103 as being unpatentable over Eliason et al. in view of Theuss et al. (US Patent 7781876)
Regarding claims 9-11 (As best understood), Eliason et al. discloses the PSD of claim 5, but fails to disclose wherein the second polymer layer (polyimide) is a polyimide resin filled with gold/silver/copper coated ceramic nanoparticles having a modulus between 6 and 9 GPa.
Fig. 6 of Theuss et al. teaches a similarly situated polymer layer 120/130 wherein the layer is embedded with gold/silver/copper coated ceramic (Fe2O3 or Fe3O4) nanoparticles 130 (see Col. 5, Lines 20-47).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the nanoparticles of Theuss et al. into the second polymer layer of Eliason et al. The ordinary artisan would have been motivated to modify Eliason et al. for the purpose of further reducing the thermal load applied to the device (see Theuss et al., Background).
The combination of Eliason et al. and Theuss et al. fails to specifically disclose that the amount of nanoparticles embedded in the polyimide layer results in a layer having a modulus between 6 and 9 GPa. However, it is known that the density of metal nanoparticles in a polymer layer is directly proportional to the Young’s modulus of the layer. It is also known that the density of metal nanoparticles in the layer is indirectly proportional to the adhesiveness of the layer. Therefore, the density of the nanoparticles is a result effective variable where the result is a change in the Young’s modulus and adhesiveness of the layer. It is noted that Eliason et al. specifically discloses that the stress buffer substrate 214, of which layer 216 is part, is intended to be formed of a rigid material (Col. 3, Lines 55-60).
Therefore, it would have been obvious to one of ordinary skill in the art to choose a density of nanoparticles in the polyimide layer that result in an ideal balance of adhesiveness and rigidity.
Claim 30 is rejected under 35 USC 103 as being unpatentable over Eliason et al. and Katou et al. further in view of Roshanghias et al. (“Digital Micro-Dispension of Non-Conductive Adhesives (NCA) by Inkjet Printer, 2017 19th Electronics Packaging Technology Conference, Dec. 06-09 2017)
Regarding claim 30 (As best understood), Eliason et al. and Katou et al. disclose the PSD of claim 27, but fail to disclose where in the first polymer layer is inkjet deposited.
Roshanghias et al. (Abstract) discloses wherein a similar polymer die-attach layer is formed by inkjet deposition.
It would have been obvious to one of ordinary skill in the art at the time of filing to use the inkjet method of Roshanghias et al. for the purpose of taking advantage of the improved uniformity, speed and flexibility associated with the inkjet printing method (see Roshanghias et al., Conclusions).
Response to Arguments
Applicant’s arguments have been considered but are not found to be persuasive.
Applicant first argues, regarding the rejection under 35 USC 112(b) of all of the pending claims, that the Examiner’s determination that the term “modulus” is unclear is flawed, specifically arguing that since “semiconductor manufacturing is clearly an engineering activity…one of ordinary skill in the art would understand that “modulus” applies to “Young’s Modulus (E), Sheer [sic] Modulus (G), Bulk Modulus (K) all of which relate to stiffness or resistance to deformation of a specific property or substance”. Applicant continues on to argue that it would be obvious to one of ordinary skill in the art that the modulus referred to in the instant application is Young’s modulus. However, Applicant provides no reasoning or evidence for this assertion, beyond noting that the Examiner chose to make the assumption that the term was intended to be Young’s Modulus. The Examiner maintains that Young’s Modulus, Shear Modulus, Bulk Modulus, Flexural Modulus and the more generic modulus of elasticity are all terms with different scopes and one of ordinary skill in the art would not have clearly understood which of these was intended by the original claim language.
Applicant next argues that the Examiner’s determination that the claim language is further unclear because there is no temperature context provided is flawed, specifically arguing that “moduli can be measured without any context for the temperature at which the moduli are to be measured”. However, Applicant then provides an argument and evidence to the contrary arguing that “a calculation without considering temperature yields a value for only one specific condition, often room temperature as a baseline, but it’s not universally constant”. It is noted that Applicant seems to be making the straw man argument that it is possible to calculate a value for modulus without knowing the temperature, when the argument made by the Examiner is that the scope of the claim is unclear without knowing the temperature at which the modulus is measured. The ability or inability to calculate the modulus is irrelevant. As noted in Applicant’s source shown in the remarks: “while the formula doesn’t specifically have ‘T’ in it, temperature is a critical experimental condition that dictates the numerical value you obtain. You can’t get a single, fixed Young’s modulus for all temperatures; it’s a temperature-sensitive property”. The Examiner further notes that since the claim compares multiple measured moduli without any temperature context for any of the measurements, the claim as written is uniquely unclear in light of Applicant’s arguments.
Applicant next argues that the rejection under 102(a)(1) is “improper on its face as Examiner is reciting a combination of references”. The Examiner notes that the rejection very clearly does not combine the teaching of the applied references, but relies on the Eliason et al. reference alone for the anticipation rejection. The Lee et al. and Sugawara et al. references merely provide evidence supporting the determination of anticipation.
Applicant next argues that the Lee et al. reference (which is, again, only relied on as providing evidenciary support) is an ineligible/improper reference because of its date. Again, the Examiner notes that the Lee et al. reference is only relied upon to provide evidence of a measurable property of the material taught by Eliason et al., and is not relied on to teach any part of the claim. The 102(a)(1) rejection relies entirely upon the Eliason et al. reference to teach the claim limitations.
Regarding the above arguments about evidenciary references, Applicant is directed to MPEP § 2124 which states that “In certain circumstances, references cited to show a universal fact need not be available as prior art before the effective filing date of applicant’s claimed invention”, and continues on to state “Such facts include the characteristics and properties of a material…”. Examiner notes that this is precisely how the Lee et al. reference is utilized throughout the instant rejection.
Applicant next argues that Eliason et al. does not teach the limitation in claim 1 that the semiconductor die has a component “…proximate to a surface of the semiconductor die” where the component is “covered with a first polymer layer…”. The Examiner first notes that the term “proximate” is understood to be a broad and relative term meaning “close”. The Examiner further notes that the instant specification provides some discussion about the use of the term proximate, which indicates that various configurations can be considered proximate, specifically:
The component can be located within die 204 proximate a surface of the semiconductor die 204, on the surface of the semiconductor die, at a surface of the semiconductor die, or, formed at an initial surface of the semiconductor die and then covered by layers of conductors and insulating dielectric layers, so that these layers lie over the initial surface of the semiconductor material of the die, in all of these examples the component is described herein as located "proximate " a surface of the semiconductor die which includes components located on a surface, at a surface or located near a surface of the semiconductor die.
The Examiner notes that the Eliason reference provides a very similar description of the components formed therein, noting that Col. 2, Line 66-Col. 3, Line 1 describes that “the process begins with fabricating one or more integrated circuits 202 in or on a surface of a semiconductor substrate 204”, and Col. 4, Lines 51-53 describe that the “stress buffer die is then attached to the semiconductor die 206 on the lead frame 210 overlying the integrated circuit 202”. Therefore, considering Applicant’s own characterizations of the term “proximate”, it is clear that the components of the integrated circuit of Eliason are formed on or near the surface of the die under the stress buffer layer.
Applicant next argues, in regards to claim 5, that the applied rejection does not teach wherein the first polymer layer “covers the surface of the semiconductor die surrounding the component to a distance of at least 20 µm”, arguing specifically that “Applicants request that Examiner provide a reference(s) that support his determination that it would have been obvious to one having ordinary skill in the art at the time of the invention to “a distance of at least 20 µm wherein the first polymer layer covers the component and covers the surface of the semiconductor die surrounding the component to a distance of a least 20 µm” in order to ensure that the component is sufficiently isolated from the stress caused by the curing of the encapsulation layer”. In the cited portion (Col. 4, Lines 49-55), Eliason provides a teaching that “the stress buffer die 218 is sized and positioned on the semiconductor die to leave a number of contact pads 220…exposed”. In the other cited portion (Background), Eliason provides a teaching that the stress buffer layer and polyimide layers are formed on the surface overlying the circuit in order to reduce the stress on the components in the circuit caused by the curing of the overlying encapsulating layer. Based on these two teachings it would have been obvious to one of ordinary skill in the art to select an optimized value for the distance beyond which the stress buffer and accompanying polyimide layer extends beyond the circuitry in/on the substrate to meet both requirements for a) exposing the contact pads and b) providing sufficient coverage so as to isolate the component from the aforementioned stress.
Applicant makes various arguments that the references utilized for evidenciary support throughout the rejections either a) can’t be included in the rejection heading because the rejections are 1) based under 102, or 2) because the reference date is not applicable as prior art, or contrarily b) are not explicitly cited in the rejection heading as being part of the rejection and therefore cannot be relied upon as part of the rejection. The Examiner argues that these references are merely supplied to provide evidence that the references actually relied upon for the rejections inherently teach the limitations of the claims, by providing, for example evidence that a particular material inherently possesses a particular value of a property. They are noted as being utilized for evidenciary support only, and where not explicitly noted in a particular rejection heading, the rejections cite to the prior rejection in the Office action which makes clear how the reference is relied upon. The Examiner argues that the rejections themselves are not ambiguous about this in any way, and that he has made a very reasonable use of the evidence in making the rejections.
Applicant next argues that the rejections of claims 7 and 29 are deficient because the combination of Ye and Eliason (and Ye, Eliason and Katou for claim 29) fail to teach or suggest “stacking one die attach film onto another die attach film wherein the thickness of one of the die attach films is different than the other die attach film”. Examiner first notes that the claims do not require “stacking one die attach film onto another die attach film wherein the thickness of one of the die attach films is different than the other die attach film” as alleged by Applicant. Instead the claims require a) a first polymer layer having a thickness between 5 and 20µm, a second polymer layer having a thickness between 2 and 10 µm and the sum of said thicknesses being between 10 and 30 µm. Nowhere in the claims are the layers required to be die attach films. The rejection relies upon first polymer layer 224 (which is disclosed by Eliason as being a die attach adhesive), and second polymer layer 216 (whose purpose is defined by Eliason as being to “further enhance the stress buffer effect” (Eliason, Col. 4, Lines 5-10). The rejections of claims 7 and 29 further note that the claimed thickness of the layer 216 lies inside of the disclosed range of the layer as taught by Eliason, and therefore the claimed thickness of the second polymer layer is prima facie obvious. The rejections, therefore, relies upon Ye ONLY for the teaching of the thickness of the die attach adhesive, about which Eliason is silent. Given the disclosed ranges for the two polymer layers, it is clear that the final limitation regarding the sum of said thicknesses is also met by the applied art.
Regarding the rejection of claim 9 and the dependent claims therefrom, Applicant argues that the combination of references fails to teach the particular range of modulus as claimed. The Examiner notes, however, that the rejection of these claims makes a case for optimization of ranges and therefore the failure to teach a specific value in the claimed range does not define a clear flaw in the rejection. Applicant has not provided a clear response to Examiner’s case that the modulus value correlates to the particular density of nanoparticles, and that said density of nanoparticles is understood to be a result effective variable.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Office should be directed to SPE WILLIAM F KRAIG whose telephone number is (571)272-8660.
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/WILLIAM F KRAIG/Supervisory Patent Examiner, Art Unit 2896