DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-15, 17-20 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kambegawa, US PGPub 2016/0125921, in view of Choi et al. US PG Pub 2018/0197599, further in view of Wolford, et al., US PGPub 2007/0047378.
With respect to claim 2, Kambegawa teaches a method at a memory device, comprising:
periodically updating, by the memory device, a mode register of the memory device with an indication of a refresh rate for the memory device based at least in part on measuring, at the memory device, a temperature of the memory device (par. 75, the temperature is measured with temperature sensor 309. As shown in fig. 6 and described in par. 55, the temperature sensor 309 is at the memory device, and measures the internal temperature of the memory. Par. 83 and fig. 10 show that the operation of updating and storing the refresh rate in steps S1008 and S1009 occur after a period of elapsed time in step S1002. As disclosed in par. 52, the refresh rate is stored in the auto refresh rate register, the mode register of the claim);
periodically outputting, from the memory device, the indication of the refresh rate for the memory device from the mode register based at least in part on the periodically updating the mode register (par. 92, the auto-refresh rates are output and stored on the HDD 105);
receiving, at the memory device based at least in part on outputting the indication of the refresh rate for the memory device, a command for a refresh operation associated with a set of refresh events for a memory array of the memory device (par. 92, the auto-refresh commands are dispatched based on the auto-refresh rates),
Kambegawa fails to teach wherein a first refresh event of the set of refresh events is configured to refresh a first row of memory cells of the memory array and a second refresh event of the set of refresh events is configured to refresh a second row of memory cells of the memory array. Choi teaches:
receiving, at the memory device, a command for a refresh operation associated with a set of refresh events for a memory array of the memory device, wherein a first refresh event of the set of refresh events is configured to refresh a first row of memory cells of the memory array and a second refresh event of the set of refresh events is configured to refresh a second row of memory cells of the memory array (pars. 74-75, where the command is the refresh command mREF_CMD, the first refresh event is refreshing the row at the first REF_ADDR, and the second refresh event is the next sequential row address according to the refresh address generator counting operation); and
performing, at the memory device, at least one refresh event of the set of refresh events in response to the command (par. 71, the refresh command is performed with some refresh commands skipped).
Kambegawa appears to disclose that the mode register containing the temperature and refresh rate is stored local to the controller and therefore is not output from the mode register of the memory device to the controller of the memory device. Choi also appears to not disclose this feature. Wolford teaches:
periodically outputting, from the mode register (par. 24, status register 16) of the memory device to a controller of the memory device (par. 24, controller 12), the indication of the refresh rate for the memory device (par. 24, temperature-dependent refresh timing information, such as periodic refresh cycle timing), and an indication of the temperature of the memory device based at least in part on periodically updating the mode register (par. 24, quantized temperature measurements. Par. 26 discloses that the status information may be output either using change-of-state signaling or serially output as clocked data).
It would have been obvious to one of ordinary skill in the art, having the teachings of Kambegawa and Choi before him before the earliest effective filing date, to modify the memory device of Kambegawa with the memory device of Choi, in order to reduce power consumption of a refresh operation by performing the refresh operation differently based on temperature, as taught by Choi in par. 3. Further, it would have been obvious to one of ordinary skill in the art, having the teachings of Kambegawa, Choi and Wolford before him before the earliest effective filing date, to modify the memory device of Kambegawa and Choi with the memory device of Wolford, as having mode and configuration setting registers accessible to the memory controller extends memory module functionality, as taught by Wolford in par. 7.
With respect to claim 3, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 2, wherein performing the at least one refresh event of the set of refresh events comprises: skipping or postponing one or more refresh events included in the set of refresh events (pars. 65-68, where some of the refresh events are skipped, depending on temperature).
With respect to claim 4, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 2, wherein each refresh event of the set of refresh events comprises a refresh of one or more rows of memory cells within the memory array of the memory device (pars. 75-76, which discloses the row refreshes as a result of the mREF_CMD, where row refreshing occurs regardless of skip ratio).
With respect to claim 5, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 2, further comprising determining a quantity of refresh events within the set of refresh events to skip based at least in part on the temperature of the memory device (par. 90, where the command skip ratio is determined the temperature data).
With respect to claim 6, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 2, further comprising determining a quantity of refresh events within the set of refresh events to postpone based at least in part on the temperature of the memory device (pars. 65-68 teach setting skip ratio based on temperature, and par. 73, which discloses skipping a certain number of refresh commands, which corresponds to the postponing of a refresh of the claim).
With respect to claim 7, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 2, further comprising: determining that temperature of the memory device is within a temperature range of a plurality of temperature ranges, wherein the indication of the refresh rate is based at least in part on the temperature range (pars. 65-68, where the temperature sections correspond to the temperate ranges of the claim).
With respect to claim 8, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 2, wherein:
the memory device comprises a first die, the first die and a second die coupled with a command bus (pars. 30-31 and the associated fig. 2, the first and second dies corresponding to the banks of memory, and the command address signal corresponding to the command bus);
the command is received by the first die and the second die via the command bus (pars. 30-31);
the temperature of the memory array comprises a temperature of the first die (par. 35, the temperature sensor detects the internal temperature of the memory); and
performing the at least one refresh event of the set of refresh events comprises performing a different quantity of refresh events at the first die than at the second die in response to the command based at least in part on the temperature of the first die (par. 38, different refresh rates are used for different memory devices).
With respect to claim 9, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 2, wherein:
the memory device comprises a first die, the first die and a second die coupled with a command bus (pars. 30-31 and the associated fig. 2, the first and second dies corresponding to the banks of memory, and the command address signal corresponding to the command bus);
the command is received by the first die and the second die via the command bus (pars. 30-31);
the temperature of the memory device comprises a temperature of the first die (par. 35, the temperature sensor detects the internal temperature of the memory); and
performing the at least one refresh event of the set of refresh events comprises performing one or more refresh events at the first die in accordance with a different timing than a second set of refresh events performed at the second die based at least in part on the temperature of the first die (par. 38, different refresh rates are used for different memory devices).
With respect to claim 10, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 2, further comprising:
receiving, at the memory device, a second command for a second refresh operation associated with a second set of refresh events (par. 173, where there are more than 1 skip ratio);
determining a third set of refresh events based at least in part on a second temperature of the memory device, the third set of refresh events different than the second set of refresh events (par. 173, where there are more than two skip ratios); and
performing the third set of refresh events in response to the second command (par. 173).
With respect to claim 11, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the method of claim 10, wherein:
performing the third set of refresh events comprises skipping or postponing a quantity of one or more refresh events included in the second set of refresh events (pars. 65-68 teach setting skip ratio based on temperature, and where the command skip ratio is determined the temperature data).
With respect to claim 12, Kambegawa teaches a memory device, comprising:
one or more memory arrays (par. 55 and fig. 6, the SDRAM array);
a temperature component configured to measure a temperature of a memory device (par. 55, the temperature sensors);
a mode register configured to be periodically updated with an indication of a refresh rate for the memory device based at least in part on the measured temperature of the memory device and configured to: periodically output the indication of the refresh rate of the memory device from the memory device based at least in part on being periodically updated (par. 75, the temperature is measured with temperature sensor 309. As shown in fig. 6 and described in par. 55, the temperature sensor 309 is at the memory device, and measures the internal temperature of the memory. Par. 83 and fig. 10 show that the operation of updating and storing the refresh rate in steps S1008 and S1009 occur after a period of elapsed time in step S1002. As disclosed in par. 52, the refresh rate is stored in the auto refresh rate register, the mode register of the claim);
a command decoder configured to decode, based at least in part on the indication of the refresh rate, a command received at the memory device for a refresh operation associated with a set of refresh events for a memory array of the one or more memory arrays (par. 92, the auto-refresh commands are dispatched based on the auto-refresh rates stored in the auto refresh rate register),
Kambegawa fails to teach wherein a first refresh event of the set of refresh events is configured to refresh a first row of memory cells of the memory array and a second refresh event of the set of refresh events is configured to refresh a second row of memory cells of the memory array. Choi teaches
a command decoder configured to decode a command for a refresh operation associated with a set of refresh events for a memory array of the one or more memory arrays, wherein a first refresh event of the set of refresh events is configured to refresh a first row of memory cells of the memory array and a second refresh event of the set of refresh events is configured to refresh a second row of memory cells of the memory array (par. 54, which discloses the command decoder for refresh events, and pars. 74-75, where the command is the refresh command mREF_CMD, the first refresh event is refreshing the row at the first REF_ADDR, and the second refresh event is the next sequential row address according to the refresh address generator counting operation);
a refresh control component configured to perform the at least one refresh event of the set of refresh events in response to the command (par. 71, the refresh command is performed with some refresh commands skipped).
Kambegawa appears to disclose that the mode register containing the temperature and refresh rate is stored local to the controller and therefore is not output from the memory device to the controller of the memory device. Choi also appears to not disclose this feature. Wolford teaches:
periodically output, from the memory device (par. 24, memory module 10, containing status register 16) to a controller of the memory device (par. 24, controller 12), the indication of the refresh rate for the memory device (par. 24, temperature-dependent refresh timing information, such as periodic refresh cycle timing) and the temperature of the memory device based at least in part on being periodically updated (par. 24, quantized temperature measurements. Par. 26 discloses that the status information may be output either using change-of-state signaling or serially output as clocked data).
It would have been obvious to one of ordinary skill in the art, having the teachings of Kambegawa and Choi before him before the earliest effective filing date, to modify the memory device of Kambegawa with the memory device of Choi, in order to reduce power consumption of a refresh operation by performing the refresh operation differently based on temperature, as taught by Choi in par. 3. Further, it would have been obvious to one of ordinary skill in the art, having the teachings of Kambegawa, Choi and Wolford before him before the earliest effective filing date, to modify the memory device of Kambegawa and Choi with the memory device of Wolford, as having mode and configuration setting registers accessible to the memory controller extends memory module functionality, as taught by Wolford in par. 7.
With respect to claim 13, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the memory device of claim 12, wherein, to perform the at least one refresh event of the set of refresh events, the refresh control component is configured to skip or postpone one or more refresh events included in the set of refresh events (pars. 65-68, where some of the refresh events are skipped, depending on temperature).
With respect to claim 14, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the memory device of claim 12, wherein each refresh event of the set of refresh events comprises a refresh of one or more rows of memory cells within the memory array (pars. 75-76, which discloses the row refreshes as a result of the mREF_CMD, where row refreshing occurs regardless of skip ratio).
With respect to claim 15, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the memory device of claim 12, further comprising: a refresh logic component configured to determine a quantity of refresh events within the set of refresh events to skip based at least in part on the temperature of the memory array (par. 90, where the command skip ratio is determined based on the temperature data).
With respect to claim 17, Kambegawa teaches a memory device, comprising:
one or more memory arrays (par. 55 and fig. 6, the SDRAM array) and
one or more controllers coupled with the one or more memory arrays (par. 92, memory controllers) and configured to cause the memory device to:
periodically update, by the memory device, a mode register of the memory device with an indication of a refresh rate for the memory device based at least in part on measuring, at the memory device, a temperature of the memory device (par. 75, the temperature is measured with temperature sensor 309. As shown in fig. 6 and described in par. 55, the temperature sensor 309 is at the memory device, and measures the internal temperature of the memory. Par. 83 and fig. 10 show that the operation of updating and storing the refresh rate in steps S1008 and S1009 occur after a period of elapsed time in step S1002. As disclosed in par. 52, the refresh rate is stored in the auto refresh rate register, the mode register of the claim);
periodically output, from the memory device, the indication of the refresh rate for the memory device from the mode register based at least in part on periodically updating the mode register (par. 92, the auto-refresh rates are output and stored on the HDD 105);
receive, at the memory device, based at least in part on outputting the indication of the refresh rate of the memory device, a command for a refresh operation associated with a set of refresh events for at a memory array of the one or more memory arrays (par. 92, the auto-refresh commands are dispatched based on the auto-refresh rates);
Kambegawa fails to teach wherein a first refresh event of the set of refresh events is configured to refresh a first row of memory cells of the memory array and a second refresh event of the set of refresh events is configured to refresh a second row of memory cells of the memory array. Choi teaches:
receive, at the memory device, a command for a refresh operation associated with a set of refresh events for at a memory array of the one or more memory arrays, wherein a first refresh event of the set of refresh events is configured to refresh a first row of memory cells of the memory array and a second refresh event of the set of refresh events is configured to refresh a second row of memory cells of the memory array (pars. 74-75, where the command is the refresh command mREF_CMD, the first refresh event is refreshing the row at the first REF_ADDR, and the second refresh event is the next sequential row address according to the refresh address generator counting operation);
perform, at the memory device, the at least one refresh event of the set of refresh events in response to the command (par. 71, the refresh command is performed with some refresh commands skipped).
Kambegawa appears to disclose that the mode register containing the temperature and refresh rate is stored local to the controller and therefore is not output from the memory device to the controller of the memory device. Choi also appears to not disclose this feature. Wolford teaches:
periodically output, from the mode register (par. 24, status register 16) of the memory device to a controller of the memory device (par. 24, controller 12), the indication of the refresh rate for the memory device (par. 24, temperature-dependent refresh timing information, such as periodic refresh cycle timing) and the temperature of the memory device register (par. 24, quantized temperature measurements).
It would have been obvious to one of ordinary skill in the art, having the teachings of Kambegawa and Choi before him before the earliest effective filing date, to modify the memory device of Kambegawa with the memory device of Choi, in order to reduce power consumption of a refresh operation by performing the refresh operation differently based on temperature, as taught by Choi in par. 3. Further, it would have been obvious to one of ordinary skill in the art, having the teachings of Kambegawa, Choi and Wolford before him before the earliest effective filing date, to modify the memory device of Kambegawa and Choi with the memory device of Wolford, as having mode and configuration setting registers accessible to the memory controller extends memory module functionality, as taught by Wolford in par. 7.
With respect to claim 18, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the memory device of claim 17, wherein, to perform the at least one refresh event of the set of refresh events, the one or more controllers are configured to cause the memory device to: skip or postpone one or more refresh events included in the set of refresh events (pars. 65-68, where some of the refresh events are skipped, depending on temperature).
With respect to claim 19, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the memory device of claim 17 wherein each refresh event of the set of refresh events comprises a refresh of one or more rows of memory cells within the memory array (pars. 75-76, which discloses the row refreshes as a result of the mREF_CMD, where row refreshing occurs regardless of skip ratio).
With respect to claim 20, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Choi further teaches the memory device of claim 17, wherein the one or more controllers are further configured to cause the memory device to: determine a quantity of refresh events within the set of refresh events to skip based at least in part on the temperature of the memory device (par. 90, where the command skip ratio is determined the temperature data).
With respect to claim 25, Kambegawa, Choi and Wolford teach the limitations of the parent claim. Kambegawa further teaches the method of claim 2, further comprising: periodically measuring, as the memory device, the temperature of the memory device (par. 73 and fig. 11, the temperature measurement in step S1108 occurs after a time period elapsed in step S1106. As shown in fig. 6 and described in par. 55, the temperature sensor 309 is at the memory device, and measures the internal temperature of the memory.).
Response to Arguments
Applicant's arguments filed 04/09/26 have been fully considered but they are not persuasive. Applicants arguments, on pages 7-9, with respect to independent claim 2, are directed towards Kambegawa and Wolford failing to teach "periodically outputting, from the mode register of the memory device to a controller of the memory device, the indication of the refresh rate for the memory device and an indication of the temperature of the memory device," as recited in independent claim 2. As evidence of this, Applicant points to Wolford as describing the output from the mode register as asynchronous (e.g. only when an event occurs). However, this is in contrast to the disclosure of Wolford, which discloses in par. 26, “Of course, as explained herein, the memory module 10 may signal status information changes asynchronously or synchronously.” Wolford continues “it may serially output status information as clocked data, or it may simply use change-of-state signaling to indicate status information.” Even if Wolford were only directed towards the asynchronous interrupt-driven embodiment, Wolford would still read on the limitation of the periodic updating. There are two common definitions of periodically- a) at regular intervals of time, and b) from time to time. If something occurs occasionally or intermittently, in response to an event, it may be considered to occur periodically.
Applicant’s arguments on pages 9-10 regarding two structurally distinct registers are also based on Wolford only teaching the asynchronous embodiment, and are similarly unpersuasive, as Wolford teaches a synchronous embodiment as well.
Applicant’s arguments on pages 10-11 are directed towards the combination of Kambegawa and Wolford allegedly being nonobvious. These arguments are directed towards Wolford teaching asynchronous event-driven signaling, as this would allegedly teach away from periodic timer-driven updating. These arguments are unpersuasive for at least the reason that Wolford teaches synchronous signaling. Further, Applicant does not claim “periodic timer-driven updating.” The claims make no mention of a timer at all, and they don’t define “periodically” as only constricted to regular intervals of time. As discussed above, even Wolford’s asynchronous embodiment can be considered as periodic updating. In any case, even if Wolford describes the advantages of the asynchronous embodiment, the fact that Wolford lists the synchronous embodiment as a viable option means it does not teach away from the combination. In any case, at least the synchronous embodiment of Wolford does not change the principal operation of the prior art invention being modified.
Applicant’s arguments regarding the remaining claims are moot, as they are directed towards either containing similar subject matter as claim 2, or depending from claim 2.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Prosecution Insights