DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shinha (US 2012/0326221, cited in previous action) and Makala (US 2014/0353738, cited in previous action) and further in view of Sharangpani et al. (US 2016/0148945, Sharangpani hereinafter).
Regarding claim 1, Sinha (Figs. 3-8) discloses an apparatus comprising:
a memory array ([0014]) including,
multiple tiers of dielectric material (170, 174, 178, 182, [0035]);
multiple tiers of barrier material (Fig. 8, layers between layers 170, 174, 178 and 182) interleaved with the multiple tiers of dielectric material, each tier of barrier material including charge storage structures (460, [0030]), and further including control gates (670, [0035]), each control gate adjacent a respective charge storage structure; and
wherein each control gate is separated from an adjacent charge storage structure by an associated multi-component dielectric structure (652, 654, [0035]) and a dielectric liner (650), and
wherein each control gate and associated multi-component dielectric structure has a vertical dimension which is greater than a vertical dimension of the adjacent charge storage structure (Fig. 8), and
wherein each control gate comprises: a conductive material (control gate material, [0035]) between the first tier of the multiple tiers of dielectric material and the second tier of the multiple tiers of dielectric material;
Sinha, however, does not disclose a conductive liner including a first portion contacting the first tier of the multiple tiers of barrier material and a second portion contacting the second tier of the multiple tiers of barrier material, and the conductive material between and contacting the first portion of the conductive liner and the second portion of the conductive liner.
Makala in the same field of art of NAND memory, teaches an apparatus comprising a control gate (3, Fig. 2A) wherein each control gate comprises:
a conductive liner (8, [0105]) including a first portion contacting a first tier of the multiple tiers of barrier material and a second portion contacting a second tier of the multiple tiers of barrier material (Fig. 13B); and
a conductive material (i.e., control gate material, [0030]) between and contacting the first portion of the conductive liner and the second portion of the conductive liner (Fig. 13B).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the control gates of Sinha by including a conductive liner with the structures and arrangements as set forth above because such conductive liner would prevent the diffusion of the conductive material from the control gate into other portions of the device, as taught by Makala ([0105]).
Sinha and Makala further teach the apparatus wherein the associated multi-component dielectric structure includes a nitride material (Sinha: 652, silicon nitride, [0035]), and a dielectric material (Sinha: 654, silicon oxide, [0035]) between and contacting the nitride material and the conductive material, and wherein the dielectric liner (Sinha: 650, [0035]) is between the nitride material and the charge storage structure.
However, Sinha and Makala do not teach the dielectric material 654 to be high-k dielectric.
Sharangpani, in the same field of art of memory device, teaches a multi-layer dielectric structure between the charge storage structure and the control gate may have an outer layer made of aluminum oxide (a high-k dielectric) adjacent to the control gate.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric material 654 of Sinha to a high-k dielectric material based on the teaching of Sharangpani, resulting a high-k dielectric material between and contacting the nitride material and the conductive liner.
Sinha, Makala, and Sharangpani are in the same field of endeavor and teach similar devices, where both dielectric layers serve the same functions in the respective devices. A person having ordinary skill in the art at the time of invention would have readily recognized the equivalent substitution of the same element, by substituting Sinha’s dielectric layer 654 with Sharangpani’s high-k dielectric layer, and would obtain predictable results. Thus, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR).
Regarding claims 2 and 6, Sinha, Makala, and Sharangpani teache the apparatus of claim 1, where the vertical dimension of each control gate and associated dielectric structure is greater than the vertical dimension of the barrier tier in which it is formed (Sinha: Figs. 3-8 and process steps in Figs. 4 and 5); and the conductive material (670) comprises tungsten ([0035]).
Regarding claim 5, Sinha, Makala, and Sharangpani teach the apparatus of claim 1 where the conductive liner 8 comprises titanium nitride (TiN), tungsten nitride, or tantalum nitride (Makala Figs. 14A-14E [0105]).
Regarding claim 7, Sinha (Figs. 3-8) discloses an apparatus comprising:
tiers of dielectric materials (170, 174, 178, 182) ([0035]);
recesses (320) adjacent the tiers of dielectric materials (Fig. 3), such that each of the recesses is adjacent two adjacent tiers of the tiers of dielectric materials;
memory cells ([0014]) including charge storage structures (460 [0030]) located in the recesses (Fig. 4), each of the memory cells including a charge storage structure (460) located in a respective recess of the recesses between a first tier of the tiers of dielectric materials (170, 174, 178, 182) and a second tier of the tiers of dielectric materials (170, 174, 178, 182), the charge storage structure 460 contacting the first tier of the tiers of dielectric materials and the second tier of the tiers of dielectric materials;
control gates (670 [0035]) associated with the memory cells, wherein each control gate (670) is separated from an adjacent charge storage structure (460) by a dielectric structure (652, 654, [0035]) and a dielectric liner (650 [0035]), and each control gate and the dielectric structure has a vertical dimension which is greater than a vertical dimension of an adjacent charge storage structure (460) of the charge storage structures;
wherein each control gate comprises: a conductive material (670 [0035]) between the first tier of the tiers of dielectric material and the second tier of the tiers of dielectric material.
Sinha, however, does not disclose a conductive liner including a first portion contacting the first tier of the multiple tiers of barrier material and a second portion contacting the second tier of the multiple tiers of barrier material, and the conductive material between and contacting the first portion of the conductive liner and the second portion of the conductive liner.
Makala in the same field of art of NAND memory, teaches an apparatus comprising a control gate (3, Fig. 2A) wherein each control gate comprises:
a conductive liner (8, [0105]) including a first portion contacting a first tier of the multiple tiers of barrier material and a second portion contacting a second tier of the multiple tiers of barrier material (Fig. 13B); and
a conductive material (i.e., control gate material, [0030]) between and contacting the first portion of the conductive liner and the second portion of the conductive liner (Fig. 13B).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the control gates of Sinha by including a conductive liner with the structures and arrangements as set forth above because such conductive liner would prevent the diffusion of the conductive material from the control gate into other portions of the device, as taught by Makala ([0105]).
Sinha and Makala further teach the apparatus wherein the dielectric structure includes a nitride material (Sinha: 652, silicon nitride, [0035]), and a dielectric material (Sinha: 654, silicon oxide, [0035]) between and contacting the nitride material and the conductive material, and wherein the dielectric liner (Sinha: 650, [0035]) is between the nitride material and the charge storage structure.
However, Sinha and Makala do not teach the dielectric material (Sinha 654) to be high-k dielectric.
Sharangpani, in the same field of art of memory device, teaches a dielectric structure between the charge storage structure and the control gate may have an outer layer made of aluminum oxide (a high-k dielectric) adjacent to the control gate.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric material 654 of Sinha to a high-k dielectric material based on the teaching of Sharangpani, resulting a high-k dielectric material between and contacting the nitride material and the conductive liner.
Sinha, Makala, and Sharangpani are in the same field of endeavor and teach similar devices, where both dielectric layers serve the same functions in the respective devices. A person having ordinary skill in the art at the time of invention would have readily recognized the equivalent substitution of the same element, by substituting Sinha’s dielectric layer 654 with Sharangpani’s high-k dielectric layer, and would obtain predictable results. Thus, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR).
Regarding claims 8-9, Sinha, Makala, and Sharangpani teach the apparatus of claim 7, where each of the first tier and the second tier (Sinha: Figs. 3-8 170, 174, 178, 182) includes a silicon dioxide material ([0021]), and the charge storage structure 460 located in the respective recess of the recesses between the first tier of the tiers of dielectric materials and the second tier of the tiers of dielectric materials includes polysilicon ([0030]) contacting the silicon dioxide material of each of the first and second tiers; each of the first tier and the second tier (170, 174, 178, 182) includes a silicon dioxide material ([0021]), and the charge storage structure 460 located in the respective recess of the recesses between the first tier of the tiers of dielectric materials and the second tier of the tiers of dielectric materials includes a dielectric material contacting the silicon dioxide material ([0021]) of each of the first and second tiers.
Regarding claim 12, Sinha, Makala, and Sharangpani teach the apparatus of claim 7, where the conductive liner material 8 contains nitrogen (Makala: Figs. 14A-14E [0105]).
Claims 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Makala in view of Sharangpani and Sinha.
Regarding claim 15, Makala (Figs. 4A-4E and 12A) discloses an apparatus comprising: tiers of silicon dioxide materials (19; paragraph 38); recesses (Figure 4B and 4D: 62 and 64) adjacent the tiers of silicon dioxide materials, such that each of the recesses is adjacent two adjacent tiers of the tiers of silicon dioxide materials; memory cells including charge storage structures 9 ([0032]) located in respective recesses of the recess, each of memory cells including a charge storage structure located in a recess (Fig. 4C) between a first tier of the tiers of silicon dioxide materials and a second tier of the tiers of silicon dioxide materials, the charge storage structure 9 contacting the first tier of the tiers of silicon dioxide materials and the second tier of the tiers of silicon dioxide materials (Figure 4C); a select gate material (301; Figure 12A) located below the memory cells (memory cells associated with control gates CG0, CG1, CG2): a silicon dioxide tunnel structure (11; paragraph 38) extending through the memory cell and contacting the select gate material (301); a pillar channel 1 ([0025]) extending through the memory cells and contacting the silicon dioxide tunnel structure (11); and control gates 3 ([0030]) associated with the memory cells, the control gates 3 located between the memory cells and the select gate material (301), wherein each control gate 3 is separated from an adjacent charge storage structure 9 by a dielectric structure 7 (ONO [0055]) and a dielectric liner (insulating capping layer, SiN, [0035]), and each control gate 3 comprises: a conductive material (control gate material ([0030]) contacting the dielectric structure 7; and the dielectric structure 7 includes a nitride material (SiN of ONO [0055]) and a dielectric material (i.e. silicon oxide of ONO [0055]) between and contacting the nitride material and the conductive material 3, and wherein the dielectric liner (insulating capping layer, SiN) is between the nitride material (SiN of ONO [0055]) and the charge storage structure (9).
Makala’s Fig. 12A does not disclose a conductive liner including the first and second portions contacting the dielectric structure, the conductive material between and contacting the first portion of the conductive liner and the second portion of the conductive liner.
However, Makala further discloses another embodiment of a memory array (Figs. 14A-14E) comprising each control gate including: a conductive liner 8 ([0105]) including the first and second portions contacting the dielectric structure 7, the conductive material 3 ([0030]) between and contacting the first portion of the conductive liner 8 and the second portion of the conductive liner 8, and the dielectric material (silicon nitride of ONO [0055]) between and contacting the nitride material and the conductive liner 8.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each control gate in Fig. 12A of Makala by including a conductive liner with the structures and arrangements as set forth in Fig. 14E because such conductive liner would prevent the diffusion of the conductive material from the control gate into other portions of the device (see Makala, ([0105]).
Furthermore, Makala do not teach the dielectric material (i.e. silicon oxide of ONO [0055]) to be a high-k dielectric.
Sharangpani, in the same field of art of memory device, teaches a dielectric structure between the charge storage structure and the control gate may have an outer layer made of aluminum oxide (a high-k dielectric) adjacent to the control gate.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric material 654 of Sinha to a high-k dielectric material based on the teaching of Sharangpani, resulting a high-k dielectric material between and contacting the nitride material and the conductive liner.
Sinha, Makala, and Sharangpani are in the same field of endeavor and teach similar devices, where both dielectric layers serve the same functions in the respective devices. A person having ordinary skill in the art at the time of invention would have readily recognized the equivalent substitution of the same element, by substituting Sinha’s dielectric layer 654 with Sharangpani’s high-k dielectric layer, and would obtain predictable results. Thus, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR).
Makala in view of Sharangpani does not disclose each control gate and the dielectric structure has a vertical dimension which is greater than a vertical dimension of the charge storage structure.
However, Sinha (Fig. 6) teaches a memory array including each control gate 670 and associated dielectric structure (650, 652, 654) has a vertical dimension which is greater than a vertical dimension of a charge storage structure 460 (labeled in Fig. 5). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Makala and Sharangpani by forming each control gate and associated dielectric structure having a vertical dimension which is greater than a vertical dimension of the charge storage structure in order to increase the vertical dimension of the associated dielectric layer (i.e., blocking dielectric layer), and the increasing in the vertical dimension of the associated dielectric layer would reduce an operating voltage of the each control gate, as taught by Sinha ([0034]).
Regarding claim 18, Makala, Sharangpani, and Sinha teach the apparatus of claim 15, wherein the conductive liner material 8 contains nitrogen (Makala: (Figs. 4A-4E and 12A) [0105]).
Response to Arguments
Applicant's arguments filed 10/08/25 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to claims 1, 7, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See noticed of reference cited.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eva Yan Montalvo whose telephone number is (571)270-3829. The examiner can normally be reached M-TH 9AM-7PM ET.
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/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818
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