DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-10, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication to Aygun 2020/0203293US in view of the US Patent Application Publication to Liao 2020/0098736US.
In regards to Claim 1, Aygun teaches a microelectronic device package interposer (Figure 2d), comprising: metallization features (Figure 2d: 216a which are solder balls wherein consider balls are made of metal materials) comprising first interfaces on a first side of a glass substrate (Figure 2d: 100 made of dielectric material 120 of which is silicon dioxide which the examiner considers to be a glass material [0037]), a plurality of electrical through-vias extending through the glass substrate (Figure 2d: 260a), and second interfaces (Figure 2d: 262a of which are solder balls wherein solder balls of metal base materials) on a second side of the glass substrate (Figure 2d: 100/216a/262a/260a), wherein the first interfaces (216a) are to couple with an integrated circuit (IC) chip (Figure 2d: See 210A) through first-level interconnect features (216a), and wherein the second interfaces (262a) are to couple with a host component through second- level interconnect features ([0046]); wherein a silicon base waveguide (Figure 2d: 110; [0033]) is used to couple to a plurality of IC chips (Figure 2d: 110 and 210a/220).
Aygun does not teach and photonic features comprising one or more optical waveguides; wherein the optical waveguides are on the first side of the substrate and are to couple with the IC chip.
Liao does teach photonic features (Figure 8: 2100) comprising one or more optical waveguides (Figure 8: PW5; [0089]), wherein the optical waveguides are on the first side of the glass substrate and are to couple with the IC chip (Figure 8: 200e and 200d). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the waveguide of Aygun to be an optical waveguide since optical waveguide are capable of having it’s the optical signal being multiplexed which allows for greater bandwidth of transmission. Further optical signals are less vulnerable to EMI crosstalk effects produce by the wiring components of the package thus producing less crosstalk or EMI interference.
As for claim 2, Aygun / Liao teaches the package interposer of claim 1, wherein Aygun teaches the metallization features 216 comprise: one or more first metallization features embedded within a first material (240) on the first side of the interposer (abstract and [0102]), wherein the first metallization features (216a) are in contact with the electrical through-vias (Figure 2d: 260a) and the first material, one or more second metallization features (bottom portion of 262a) embedded within a second material (abstract) on the second side of the interposer (bottom side of 100), wherein the second metallization features are in contact with the electrical through-vias (260a); and the waveguides route around the electrical through-vias (Figure 2d: 110 is disposed on the outside edge of vias 260a).
Aygun does not teach wherein the 1st or 2nd material is a dielectric comprising at least one of oxygen or nitrogen.
Liao does teach dielectric materials layers (Figure 1a: 116a; wherein the dielectric material contains silicon oxide or oxygen [0015]) used with embedded metal materials (Figure 1a: within 116a) for routing electrical transmission ([0015]) while the dielectric materials are used to isolate the different electrical channels (Figure 1a: 214a/14a are coupled to 116 and 118 with dielectric materials in between each coupling connections). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the of Aygun wherein the 1st and 2nd materials are made from silicon oxide in order to provide electrical isolation along the electrical transmission lines.
As for claim 3, Aygun / Liao teaches the package interposer of claim 2 wherein Aygun teaches the first material (120 or voids or other dielectric materials making up a portion of 120 [0037-0039]) is also between the waveguides (110) and the glass substrate (See Figure 1a: 100 which also includes 120).
Aygun does not teach wherein 110 and 240 are made of the same material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric materials of 110 and 240 to be made of same material in or ensure proper electrical isolation / insulating between the different electrical transmission lines, further the dielectric materials of 110 is disclosed to be made from silicon ([0037-0039]) which is a well-known and readily available materials in the semiconductor art. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. that a mere reversal of the working parts of the essential working parts of a device involves only routine skill in the art. In re Leshin, 125 USPQ 146.
As for claim 4, Aygun / Liao teaches the package interposer of claim 3, wherein Liao teaches the first dielectric comprises silicon oxide or Silicon nitride ([0015]).
Aygun and Liao does not teach wherein the 1st dielectric and 2nd dielectric materials are made of different materials.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric materials of the first and 2nd dielectric to be made of different materials in order to address the different degrees of EMI interference that exist due to high. Having different materials allows the inventor to balance cost vs isolation properties that are needed for different degrees of EMI interference. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. that a mere reversal of the working parts of the essential working parts of a device involves only routine skill in the art. In re Leshin, 125 USPQ 146.
In terms of claim 9, Aygun / Liao teaches IC device package comprising: the package interposer of claim 1; a first IC chip (210) coupled to a first one of the first interfaces (216a) through the first level interconnection features (top area of 260a); and a material over the interposers and adjacent to at least an edge of the first IC chip (Figure 1a, layer over 120 or layer 240).
Aygun does not teach wherein 2nd material is a dielectric material.
Liao does teach dielectric materials layers (Figure 1a: 114a and 214a; wherein the dielectric material contains silicon oxide or oxygen [0015]) used with embedded metal materials (Figure 1a: 114a and 214a) for routing electrical transmission ([0015]) while the dielectric materials are used to isolate the different electrical channels (Figure 1a: 214a/14a are coupled to 116 and 118 with dielectric materials in between each coupling connections). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the of Aygun wherein the 1st and 2nd materials are made from silicon oxide in order to provide electrical isolation along the electrical transmission lines.
As for claim 10, Aygun / Liao teaches IC package of claim 9, wherein Aygun teaches the package further comprises a second IC chip (220) adjacent to the first IC chip (210), the second IC chip coupled to the second ones of the first interfaces through the first level interconnect features (Figure 2d: top of 260a); and a one or more waveguides (110) optically coupling the first chip to the second IC chip (see 110).
In terms of Claim 13, Aygun / Liao teaches the system comprising the IC device package of claim 9, wherein Aygun teaches and a host component electrically coupled to the second interfaces through the second level interconnect features (Figure 2d: 234/232a; [0046]).
As for claim 14, Aygun / Liao teaches the system package of claim 13, wherein Aygun teaches the first IC chip comprises microprocessor circuitry to execute instructions ([0066]).
As for claim 15, Aygun / Liao teaches the system package of claim 14, wherein Aygun teaches the second IC chip comprises memory circuitry to store bits values ([0049]).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Aygun 2020/0203293US / Liao 2020/0098736US as applied to claim 2 above, and in view of US Patent Application Publication to Block 2020/0035560US, and further in view of Kinghorn 20160291265US.
In regards to claims 5-7, Aygun teaches wherein the interposer has a core that is made silicon.
Aygun does not teach wherein the silicon is monocrystalline or polycrystalline.
Block teaches an optical device wherein having a layer 215 that can be monocrystalline ([0112]) and wherein polysilicon can also be used ([0190]). The choice of using monocrystalline pertains to one desire to have better performance ([0104]), while polysilicon is used for high K application or to reduce cost of the device. As for the limitation of a cladding layer in contact with the waveguide, this feature is present in all waveguide as the cladding layer must be contact with the waveguide in order for the waveguide to function as a waveguide to guide light. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device to use either monocrystalline silicon or polycrystalline silicone base on the cost and application (high K) or to designed the device for purely performance purposes. One would be motivated to adjust the material application for different goals and objectives in designed choices.
Aygun / Block do not teach wherein the waveguide is made of silicon and oxygen.
Kinghorn teaches an optical waveguide on a substrate wherein the waveguide comprises a cladding layer made of silicon and oxygen Figure 16c: various cladding layers and ([0105] and [0061]). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the device of Aygun to include a cladding that is made of silicon and oxygen in order to provide efficient confinement and increase the efficiency of the signal transmission
Claims 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication to Aygun 2020/0203293US / Liao 2020/0098736US in view of the US Patent Application Publication to Kinghorn 20160291265US.
In terms of Claim 16, Aygun teaches the method of fabricating an integrated circuit package interposer (Figure 2d), the method comprising receiving a glass substrate (120, is made of silicon dioxide glass [0037]) comprising a plurality of electrical through-vias (260a) extending through a thickness of the glass substrate (Figure 2d: 260a and 100); forming over a first of the glass substrate (120/100; [0037]); one more waveguide (Figure 2d: 110) comprising polycrystalline or monocrystalline silicon ([0033]); forming first metallization features (Figure 2d: 216a) through the first material (Figure 2d: 216a); wherein at least one of the first metallization features (216a) contacts at least one of the through vias (top portion of 260a and vias 260a) and terminates at a first interface (top portion of 260a); and forming, over a second side of the glass substrate (120/100; [0037] wherein silicon dioxide is considered to be a type of glass); at least two levels of second metallization features (262a and 234a/232a or 232a/234a) within the second material (abstract) comprising other than a silicon base ([262a/234a/232a are made of metal and not silicon base materials]); wherein at least one of second metallization features contacts at least one of the through vias and terminates (262a/232a contacts 260a) at a second interface ([0024] and bottom portion of 260a).
Aygun does not teach and photonic features comprising one or more optical waveguides; wherein the optical waveguides are on the first side of the substrate and are to couple with the IC chip and wherein the first and 2nd interfaces making up the first metallization and 2nd metallization are disposed within dielectric materials.
Liao does teach photonic features (Figure 8: 2100) comprising one or more optical waveguides (Figure 8: PW5; [0089]), wherein the optical waveguides are on the first side of the glass substrate and are to couple with the IC chip (Figure 8: 200e and 200d), wherein metallization materials in 116a are disposed within a dielectric material ((Figure 1a: 116a; wherein the dielectric material contains silicon oxide or oxygen [0015]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the waveguide of Aygun to be an optical waveguide since optical waveguide are capable of having it’s the optical signal being multiplexed which allows for greater bandwidth of transmission. Further optical signals are less vulnerable to EMI crosstalk effects produce by the wiring components of the package thus producing less crosstalk or EMI interference. Further, one of ordinary skill in the art before the effective filing date would modify the materials of 230/240 to be made dielectric materials in order to properly protect individual electrical transmission lines from crosstalk or EMI interference with each other.
Aygun does not teach wherein the waveguide is made of silicon and oxygen.
Kinghorn teaches an optical waveguide on a substrate wherein the waveguide comprises a cladding layer made of silicon and oxygen Figure 16c: various cladding layers and ([0105] and [0061]). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the device of Aygun to include a cladding that is made of silicon and oxygen in order to provide efficient confinement and increase the efficiency of the signal transmission.
As for Claim 17, Aygun / Liao / Kinghorn teaches the method of claim 16, Aygun further teaches comprising: attaching a first chip (Figure 2d: 210) comprising an integrated circuit (IC) to first ones of the first interfaces (Figure 2d: top portion of 260a and 210a); attaching a second chip (Figure 220) comprising an IC to second ones of the first interfaces; and forming a dielectric material over the interposer and between the first and second chips (Figure 2d: 110 and 210/220).
As for Claim 19, Aygun / Liao / Kinghorn teaches the method of claim 16, further Aygun teaches comprising attaching the second interfaces to a host component with second level interconnect features (232a and [0046]).
Claims 8, 11, 12, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Aygun 2020/0203293US / Liao 2020/0098736US as applied to claims 1, and 9 above, and further in view of US Patent Application Publication to Liff 20200286871US.
In regards to claims 8, 11 and 12, Aygun/ Liao teaches the device of claims 1 and 9, Aygun does not teach further comprising a micro-ring resonator or optical modulator; a photodetector or laser attached to the waveguides, wherein the terminals of the photodetector or the laser are coupled to the first IC chip or second IC through one more of the first metallization features.
Liff does teach an optical package having metallization features with IC packages further comprising a micro-ring resonator ([0127]) or optical modulator ([0127]); a photodetector or laser (Figure 13: 1861 and [0127]) attached to the waveguides (Figure 13: 1862), wherein the terminals of the photodetector or the laser are coupled to the first IC chip or second IC through one more of the first metallization features ([0127]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Aygun to include a photodetector or laser along with other components such as an optical modulator or ring resonator in order to create an integrated optical package that is capable of both transmitting and receiving while the modulator or ring resonator allows the device to be tuned for specific applications. These integrated components will reduce the need of different packages and thus will reduce the overall package size of the device.
In regards to claim 18, Aygun / Liao / Kinghorn teaches the device of claims 17.
Aygun does not teach attaching a photodetector or laser to at least one of the optical waveguides; forming a first dielectric material over the photodetector or the laser; and forming at least one first metallization features to a terminal of the photodetector or laser.
Liff does teach an optical package having metallization features (Figure 13: 1815) with IC packages further comprising a photodetector or laser (Figure 13: 1861 and [0127]) attached to at least one of the waveguides (Figure 13: 1862), forming a first dielectric material (Figure 13: 1819) over the photodetector or the laser (Figure 13: 1861); and forming at least one first metallization features to a terminal of the photodetector or laser (Figure 13: 1815 and 1861)., It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Aygun to include a photodetector or laser along with other components such that is connected via the metallization features wherein a dielectric covers the components. The application of a dielectric over the electrical components is to prevent shorting between various components and provide proper electronic isolation, the metallization is used in a similar as Aygun to provide electrical connects to various electronics within the package.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Aygun to include a photodetector or laser along with other components allows the device to be both an optical transmitter and receiver. These integrated components will reduce the need of different packages and thus will reduce the overall package size of the device.
Response to Arguments
Applicant’s arguments, see Appeal Brief, filed 11/19/2025, with respect to claims 1 and 16, have been fully considered and are persuasive. The FINAL Rejection of 3/06/2025 has been withdrawn.
New grounds of rejection were made in view of Liao as detailed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent to Na (9,028,157US) teaches metallization electrical interconnect layers used in optical packages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOANG Q TRAN whose telephone number is (571)272-5049. The examiner can normally be reached 9:30 am - 5:30pm Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 5712722397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HOANG Q TRAN/ Examiner, Art Unit 2874
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