DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending and examined herein.
Claims 1-6, 8-13, and 15-19 are rejected under 35 U.S.C. 102.
Claims 7, 13, and 20 are rejected under 35 U.S.C. 103.
Response to Arguments
Applicant's arguments filed 02/10/2026 have been fully considered but they are not persuasive.
Applicant argues, see pages 8-9 that "Nandakumar's AD conversion is not the same as "... converting, by one or more computer processors, the first output and the second output into a format having less precision than a format of the first output and a format of the second output...," as claimed in claimed 1, 8, and 15.".
Examiner respectfully disagrees. As stated in the previous office action, see pages 4-5, the outputs are interpreted as the output of the forward propagation (first output) and the output of the backward propagation (second output). The caption of Figure 1 in Nandakumar states "The crossbar arrays perform the weighted summations during the forward and backward propagations. The resulting
x
and δ values are used to determine the weight updates,
∆
W
, in the digital unit." Therefore, the outputs include the forward and backward propagation outputs. Page 3 states "For the forward propagation, the neuron activations,
x
i
, are converted to voltages,
V
x
i
, and applied to the crossbar rows. Currents will flow through individual devices based on their conductance and the total current through any column,
I
j
=
∑
i
G
j
i
V
x
i
, will correspond to
∑
i
G
j
i
V
x
i
, that becomes the input for the next neuron layer." This is interpreted as the first output. From the view of the “next neuron layer”, the first output is from the last layer. Page 3 further states "Similarly, for the backward propagation through the same layer, the voltages
V
δ
j
corresponding to the error
δ
j
are applied to the columns of the same crossbar array and the weighted sum obtained along the rows,
∑
j
W
i
j
δ
j
, can be used to determine the error
δ
i
of the preceding layer." Therefore, for the “preceding layer”, the error, interpreted as the second output, would be from the next layer. Therefore, the outputs are in the form of voltages. Page 12 of Nandakumar states "For reading a PCM device, the selected BL is biased to a constant voltage of 300 mV by a voltage regulator via a voltage
V
read
generated off-chip. The sensed current,
I
read
, is integrated by a capacitor, and the resulting voltage is then digitized by the on-chip 8-bit cyclic ADC." Therefore, the outputs (voltages) are digitized by the ADC, meaning that they are converted into a format having less precision, as explained on page 5 of the previous office action.
Further, Applicant argues that "However, the claimed first and second outputs "are produced by their respective analog RPU arrays by converting analog computation results to digital via an analog to digital (AD) converter" (Application, ¶0045) before they are converted to the lower precision format (as claimed in independent claims 1, 8, and 15 … The first and second (digital) outputs are then converted to the lower precision format, as discussed e.g., at ¶ 0046-0048 and 0079 Id."
However, the claims as written do not require that the outputs of the RPU are digital. Thus, Nandakumar teaches this limitation "... converting, by one or more computer processors, the first output and the second output into a format having less precision than a format of the first output and a format of the second output...”
Applicant further argues, see page 9, "The independent claims also recite "... initiating, by one or more computer processors, a calculation of an update parameter for a first step update pass of the layer, the calculation utilizing the converted first output and the converted second output...," whereas Nandakumar computes a rank update digitally with high precision."
Though Examiner agrees that Nandakumar computes a rank update digitally with high precision, Examiner respectfully disagrees that Nandakumar does not teach this limitation. Fig. 1B of Nandakumar shows that the outputs of the RPU for the forward propagation (
∑
i
W
j
i
δ
i
)
and backward propagation (
∑
j
W
i
j
δ
j
) are sent to the high-precision digital unit, which is then used to calculate the rank update. In order for the high-precision digital unit to receive the output voltages, the output voltages must be converted using the ADC converter. Therefore, when the high-precision digital unit calculates the update parameter, it utilizes the converted first output (the RPU output of the forward propagation sent through the ADC) and the converted second output (the RPU output of the backward propagation sent through the ADC).
Applicant further argues, see page 9, that "Further, the independent claims recite an asynchronous pipeline in which the initiating the calculation of the update parameter for the first step update pass is followed by "receiving... outputs pertaining to a second step... ; and based, at least in part, on the receiving of the outputs pertaining to the second step..., applying... the update parameter for the first step update pass."
Page 5 of Nandakumar states "The resulting weight updates are accumulated in the variable χ. When the magnitude of χ exceeds
ϵ
(= 0.096 corresponding to an average conductance change of 0.77
μ
S per programming pulse), a 50 ns pulse with an amplitude of 90
μ
A is applied to
G
p
to increase the weight if
χ
<
0
;
|
χ
|
is then reduced by
ϵ
.” As the weight updates are accumulated, when the first step of the update pass is less than χ, the receiving of the next step’s weight updates (receiving the outputs pertaining to a second step) will be used in the applying of the update parameter for the first step update pass of the layer. Thus, Nandakumar teaches the asynchronous pipeline as claimed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-13, and 15-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nandakumar (“Mixed-Precision Deep Learning Based on Computational Memory”, May 2020, made available by the applicant via IDS).
Regarding claim 1, Nandakumar teaches
A computer-implemented method comprising: (Page 3 states "A schematic illustration of the MCA for training DNNs is shown in Figure 1. It consists of a computational memory unit comprising several memristive crossbar arrays, and a high-precision digital computing unit." The MCA (mixed-precision computational memory architecture is interpreted as the computer that implements the method.)
receiving, by one or more computer processors, outputs pertaining to a first step of a training process being performed on an analog resistive processing unit (RPU) array, (Page 1 states "A schematic illustration of the MCA for training DNNs is shown in Figure 1. It consists of a computational memory unit comprising several memristive crossbar arrays, and a high-precision digital computing unit." Therefore, the memristive crossbar array is interpreted as the RPU array. The caption of Figure 1 states "The crossbar arrays perform the weighted summations during the forward and backward propagations. The resulting
x
and δ values are used to determine the weight updates,
∆
W
, in the digital unit." Therefore, the digital unit, interpreted as part of the computer processor, receives the two outputs
x
and δ, interpreted as the outputs.) the analog RPU array corresponding to a layer of a deep neural network (DNN), (Page 3 states "If the weights
W
i
j
in any layer of a DNN (Figure 1A) are mapped to the device conductance values
G
j
i
in the computational memory with an optional scaling factor, then the desired weighted summation operation during the data-propagation stages of DNN training can be implemented as follows.” As the weights from a layer of a DNN are mapped to the device conductance values given by the analog RPU array, the analog RPU array corresponds to that layer of the DNN." the outputs including: (i) a first output of a first step forward pass of a previous layer, and (ii) a second output of a first step backward pass of a next layer; (The caption of Figure 1 states "The crossbar arrays perform the weighted summations during the forward and backward propagations. The resulting
x
and δ values are used to determine the weight updates,
∆
W
, in the digital unit." Therefore, the outputs include the forward and backward propagation outputs. Page 3 states "For the forward propagation, the neuron activations,
x
i
, are converted to voltages,
V
x
i
, and applied to the crossbar rows. Currents will flow through individual devices based on their conductance and the total current through any column,
I
j
=
∑
i
G
j
i
V
x
i
, will correspond to
∑
i
G
j
i
V
x
i
, that becomes the input for the next neuron layer." This is interpreted as the first output. From the view of the “next neuron layer”, the first output is from the last layer. Page 3 further states "Similarly, for the backward propagation through the same layer, the voltages
V
δ
j
corresponding to the error
δ
j
are applied to the columns of the same crossbar array and the weighted sum obtained along the rows,
∑
j
W
i
j
δ
j
, can be used to determine the error
δ
i
of the preceding layer." Therefore, for the “preceding layer”, the error, interpreted as the second output, would be from the next layer.)
converting, by one or more computer processors, the first output and the second output into a format having less precision than the first output and a format of the second output, yielding a converted first output and a converted second output; (As established above, the first output and second output are received by the computer processor from the analog RPU. Page 12 states "For reading a PCM device, the selected BL is biased to a constant voltage of 300 mV by a voltage regulator via a voltage
V
read
generated off-chip. The sensed current,
I
read
, is integrated by a capacitor, and the resulting voltage is then digitized by the on-chip 8-bit cyclic ADC." Therefore, the ADC, interpreted as part of the computer processor, is used to convert the first output and second output into a digital format, interpreted as the converted first and second outputs. Though Nandakumar is silent on this fact, it is inherent that the converted/digital first and second outputs will have less precision than the analog first and second components. See Wikipedia, “Analog-to-digital converter” which states, on the first page, that “An ADC converts a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal. The conversion involves quantization of the input, so it necessarily introduces a small amount of error or noise. Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, sampling the input, limiting the allowable bandwidth of the input signal.” Therefore, as the first and second outputs are converted into a digital format by the ADC in order to be received by the high-precision digital unit, the converted first and second outputs have less precision than the first output and second output.)
initiating, by one or more computer processors, a calculation of an update parameter for a first step update pass of the layer, the calculation utilizing the converted first output and the converted second output; (Page 3 states "The desired weight updates are determined as
∆
W
j
i
=
η
δ
j
x
i
, where
η
is the learning rate. We accumulate these updates in a variable in the high-precision digital unit. The accumulated weight updates are transferred to the devices by applying single-shot programming pulses, without using an iterative write-verify scheme." The weight update is interpreted as the update parameter. The caption of Figure 1 states "The resulting x and δ values are used to determine the weight updates,
∆
W
, in the digital unit." As the calculation is performed, it must have been initiated. As the calculation is performed by the digital unit, which receives the converted outputs, the calculation uses the converted outputs.)
receiving, by one or more computer processors, outputs pertaining to a second step of the training process being performed on the analog RPU array; and (Page 5 states "Each weight of the network,
W
, is realized using two PCM devices in a differential configuration (
W
∝
(
G
p
-
G
n
)
). The 198,760 weights in the network are mapped to 397,520 PCM devices in the hardware platform (see section A.2). The network is trained using 60,000 training images from the MNIST dataset for 30 epochs. The devices are initialized to a conductance distribution with mean 1.6μS and standard deviation of 0.83μS. These device conductance values are read from hardware, scaled to the network weights, and used for the data-propagation stages. The resulting weight updates are accumulated in the variable χ." One of ordinary skill in the art would realize that a step of the training process happens for each training image multiplied by the number of training epochs. Therefore, outputs for a second step will be received while training.)
based, at least in part, on the receiving of the outputs pertaining to the second step of the training process being performed on the analog RPU array, applying, by one or more computer processors, the update parameter for the first step update pass of the layer to the analog RPU array. (Page 5 states "The resulting weight updates are accumulated in the variable χ. When the magnitude of χ exceeds
ϵ
(= 0.096 corresponding to an average conductance change of 0.77
μ
S per programming pulse), a 50 ns pulse with an amplitude of 90
μ
A is applied to
G
p
to increase the weight if
χ
<
0
;
|
χ
|
is then reduced by
ϵ
.” As the weight updates are accumulated, when the first step of the update pass is less than χ, the receiving of the next step’s weight updates will be used in the applying of the update parameter for the first step update pass of the layer. As the update is applied to
G
p
, the update is applied to the PCM/analog RPU array.)
Regarding claim 2, the rejection of claim 1 is incorporated herein. Nandakumar teaches
wherein the training process utilizes stochastic gradient descent. (Page 13 states "The network was trained by minimizing the mean square error loss function with stochastic gradient descent (SGD).")
Regarding claim 3, the rejection of claim 1 is incorporated herein. Nandakumar teaches
subsequent to receiving the outputs pertaining to the first step of the training process being performed on the analog RPU array, and prior to receiving the outputs pertaining to the second step of the training process being performed on the analog RPU array: (Pages 5-6 state "Since the continuous SET programming could cause some of the devices to saturate during training, a weight refresh operation is performed every 100 training images to detect and reprogram the saturated synapses. After each training example involving a device update, all the devices in the second layer and 785 pairs of devices from the first layer are read along with the updated conductance values to use for the subsequent data-propagation step (see section A.2.2)." The first step is interpreted to correspond to a training example involving a device update. Therefore, the subsequent data-propagation step is interpreted as the second step.)
receiving, by one or more computer processors, outputs pertaining to the first step of the training process being performed on a next analog RPU array, the next analog RPU array corresponding to the next layer; and (Pages 5-6 state "Since the continuous SET programming could cause some of the devices to saturate during training, a weight refresh operation is performed every 100 training images to detect and reprogram the saturated synapses. After each training example involving a device update, all the devices in the second layer and 785 pairs of devices from the first layer are read along with the updated conductance values to use for the subsequent data-propagation step (see section A.2.2)." The devices in the second layer are interpreted as the next analog RPU array. As the devices are read, the outputs will be received.)
receiving, by one or more computer processors, outputs pertaining to the second step of the training process being performed on the next analog RPU array. (Pages 5-6 state "Since the continuous SET programming could cause some of the devices to saturate during training, a weight refresh operation is performed every 100 training images to detect and reprogram the saturated synapses. After each training example involving a device update, all the devices in the second layer and 785 pairs of devices from the first layer are read along with the updated conductance values to use for the subsequent data-propagation step (see section A.2.2)." The devices in the second layer are interpreted as the next analog RPU array. As the updated conductance values are read for the subsequent data-propagation step for the second layer, the outputs are for the next array for the next step are received.)
Regarding claim 4, the rejection of claim 1 is incorporated herein. Nandakumar teaches
wherein the converted first output and the converted second output are vectors of integers. (Page 15 states "In order to model the peripheral analog to digital conversion, the matrix-vector multiplication results are quantized back to 8-bit fixed-point." One of ordinary skill in the art would realize that fixed-point numbers are integers, and that the result of matrix-vector multiplication is a matrix, which is composed of vectors.)
Regarding claim 5, the rejection of claim 4 is incorporated herein. Nandakumar teaches
wherein integers in the vectors of integers are eight bits or less. (Page 15 states "In order to model the peripheral analog to digital conversion, the matrix-vector multiplication results are quantized back to 8-bit fixed-point.")
Regarding claim 6, the rejection of claim 1 is incorporated herein. Nandakumar teaches
wherein the applying of the update parameter for the first step update pass to the analog RPU array utilizes a learning rate and bin-widths associated with the outputs pertaining to the second step of the training process being performed on the analog RPU array. (Page 3 states “The desired weight updates are determined as
∆
W
j
i
=
η
δ
j
x
i
, where
η
is the learning rate. We accumulate these updates in a variable in the high-precision digital unit. The accumulated weight updates are transferred to the devices by applying single-shot programming pulses, without using an iterative write-verify scheme.” Thus, as the learning rate is also for the second step and the weight is calculated using the learning rate, the first step update Is based on the learning rate. Page 15 states “In order to model the peripheral analog to digital conversion, the matrix-vector multiplication results are quantized back to 8-bit fixed-point.” As the values are quantized (as they are by the ADC), they have a bin-width (i.e. the width of the range of continuous values that map to an 8-bit discrete value. As the quantization is applied uniformly, the second step and the first step bin-widths will be the same. Thus, as the first step weight updates are quantized, they utilize the second step bin-width.)
Regarding claim 8, Nandakumar teaches
A computer program product comprising one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media, the program instructions executable by one or more computer processors to cause the one or more computer processors to perform a method comprising: (Page 3 states "A schematic illustration of the MCA for training DNNs is shown in Figure 1. It consists of a computational memory unit comprising several memristive crossbar arrays, and a high-precision digital computing unit." The MCA (mixed-precision computational memory architecture is interpreted as the computer that implements the method. One of ordinary skill in the art would realize that a computer readable storage medium that stores the method and a processor that executes the method are necessary for the computer to perform the method.)
The remainder of claim 8 recites substantially similar subject matter to claim 1 and is rejected with the same rationale, mutatis mutandis.
Claims 9-13 recite substantially similar subject matter to claims 2-6 respectively and are rejected with the same rationale, mutatis mutandis.
Regarding claim 15, Nandakumar teaches
A computer system comprising: (Page 3, Fig. 1B shows the computer system, comprising several memristive crossbar arrays, and a high precision digital computing unit.)
one or more analog resistive processing unit (RPU) arrays; (Page 3 states "It consists of a computational memory unit comprising several memristive crossbar arrays, and a high precision digital computing unit." The memristive crossbar arrays are interpreted as the RPU arrays.)
one or more computer processors; and one or more computer readable storage media; wherein: (Page 3 states "A schematic illustration of the MCA for training DNNs is shown in Figure 1. It consists of a computational memory unit comprising several memristive crossbar arrays, and a high-precision digital computing unit." The MCA (mixed-precision computational memory architecture is interpreted as the computer that implements the method. One of ordinary skill in the art would realize that a computer readable storage medium that stores the method and a processor that executes the method are necessary for the computer to perform the method.)
the one or more computer processors are structured, located, connected and/or programmed to execute program instructions collectively stored on the one or more computer readable storage media; and the program instructions, when executed by the one or more computer processors, cause the one or more computer processors to perform a method comprising: (One of ordinary skill in the art would realize that a computer readable storage medium that stores the method and a processor that executes the method, connected to the computer readable storage medium, are necessary for the computer to perform the method. Program instructions, executed by the processor, to perform the method are also required for the method to be implemented by a computer.)
The remainder of claim 15 recites substantially similar subject matter to claim 1 and is rejected with the same rationale, mutatis mutandis.
Claims 16-19 recite substantially similar subject matter to claims 2-5 respectively and are rejected with the same rationale, mutatis mutandis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nandakumar (“Mixed-Precision Deep Learning Based on Computational Memory”, May 2020, made available by the applicant via IDS) as applied to claims 1, 8, and 15 above, and further in view of Zahedi (“Efficient Organization of Digital Periphery to Support Integer Datatype for Memristor-Based CIM”, 2020).
Regarding claim 7, the rejection of claim 1 is incorporated herein. Nandakumar teaches
wherein the initiating of the calculation of the update parameter for the first step update pass of the layer includes sending the converted first output and the converted second output to a set of digital processing units, (Page 3 states "The desired weight updates are determined as
∆
W
j
i
=
η
δ
j
x
i
, where
η
is the learning rate. We accumulate these updates in a variable in the high-precision digital unit. The accumulated weight updates are transferred to the devices by applying single-shot programming pulses, without using an iterative write-verify scheme." The weight update is interpreted as the update parameter. The caption of Figure 1 states "The resulting x and δ values are used to determine the weight updates,
∆
W
, in the digital unit." As the calculation is performed, it must have been initiated. As the calculation is performed by the digital unit, which receives the sent converted outputs, the calculation uses the converted first and second outputs, x and δ.)
Nandakumar does not appear to explicitly teach
the set of digital processing units having, for each analog tile of the analog RPU array, a corresponding digital processing unit.
However, Zahedi—directed to analogous art—teaches
the set of digital processing units having, for each analog tile of the analog RPU array, a corresponding digital processing unit. (Page 4, Fig. 5 shows the organization of digital units required per ADC. The part of the diagram after the ADC is interpreted as the corresponding digital processing unit. Fig. 5 shows that an analog tile is attached to each ADC, meaning that the output, converted via the ADC, is processed by a corresponding digital processing unit. Therefore, for each ADC, a tile of the analog RPU array is present, and corresponds to the digital processing unit.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Nandakumar and Zahedi because, as stated by Zahedi on page 3"Essentially, the addition in this stage is performed in an analog manner-using Kirchhoff’s Law-if and only if (1) the analog-to-digital converter (ADC) is capable of distinguishing between all the possible current levels and (2) all the necessary rows (related to the multiplier) can be activated at the same time-this is dictated by the utilized technology. If either (or both) of the mentioned conditions is (are) not met, the addition needs to be broken down to only adding those number of rows that can be supported by the ADC accuracy or technology. This means that the analog addition is only performed among a smaller number of rows and the resulting intermediate results need to be summed up together in the digital domain."
Claim 14 recites substantially similar subject matter to claim 7 and is rejected with the same rationale, mutatis mutandis.
Regarding claim 20, the rejection of claim 15 is incorporated herein. Nandakumar teaches
the one or more computer processors include a plurality of computer processors; (Page 3, Figure 1 shows that there is a computational memory unit and a high-precision digital unit. As they perform computations, they are interpreted as the plurality of computer processors.)
the initiating of the calculation of the update parameter for the first step update pass of the layer includes sending the converted first output and the converted second output to the [processors] (Page 3 states "The desired weight updates are determined as
∆
W
j
i
=
η
δ
j
x
i
, where
η
is the learning rate. We accumulate these updates in a variable in the high-precision digital unit. The accumulated weight updates are transferred to the devices by applying single-shot programming pulses, without using an iterative write-verify scheme." The weight update is interpreted as the update parameter. The caption of Figure 1 states "The resulting x and δ values are used to determine the weight updates,
∆
W
, in the digital unit." As the calculation is performed, it must have been initiated. As the calculation is performed by the digital unit, which receives the sent converted outputs, the calculation uses the converted first and second outputs, x and δ.)
Nandakumar does not appear to explicitly teach
the plurality of computer processors includes a subset of dedicated computer processors having corresponding computer processors for each analog tile of the analog RPU array; and
However, Zahedi—directed to analogous art—teaches
the plurality of computer processors includes a subset of dedicated computer processors having corresponding computer processors for each analog tile of the analog RPU array; and (Page 4, Fig. 5 shows the organization of digital units required per ADC. The part of the diagram after the ADC is interpreted as the corresponding digital processing unit. Fig. 5 shows that an analog tile is attached to each ADC, meaning that the output, converted via the ADC, is processed by a corresponding digital processing unit. Therefore, for each ADC, a tile of the analog RPU array is present, and corresponds to the digital processing unit.)
the subset of dedicated computer processors (See above limitation.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Nandakumar and Zahedi because, as stated by Zahedi on page 3"Essentially, the addition in this stage is performed in an analog manner-using Kirchhoff’s Law-if and only if (1) the analog-to-digital converter (ADC) is capable of distinguishing between all the possible current levels and (2) all the necessary rows (related to the multiplier) can be activated at the same time-this is dictated by the utilized technology. If either (or both) of the mentioned conditions is (are) not met, the addition needs to be broken down to only adding those number of rows that can be supported by the ADC accuracy or technology. This means that the analog addition is only performed among a smaller number of rows and the resulting intermediate results need to be summed up together in the digital domain."
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.T.P./Examiner, Art Unit 2121
/Li B. Zhen/Supervisory Patent Examiner, Art Unit 2121
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