Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 24, 2026 has been entered.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-10, 12-19, and 23-26 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding Claim 1,
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 1 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“determining … based on the synchronization information, a time to run the first ML model on a first processing core of the processing cores”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are mere instructions to apply an exception (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)).
The limitations:
“by the runtime controller”
“running the first ML model on the first processing core at the time”
As drafted, are additional elements that amount to no more than mere instructions to apply an exception for the abstract ideas. See MPEP 2106.05(f).
The limitations:
“receiving an indication to run a first machine learning (ML) model”
“receiving, by a runtime controller, synchronization information that orders running of ML models relative to each other in a pattern, the ML models to be run on processing cores, the ML models including the first ML model”
As drafted, are additional elements that amount to no more than insignificant extra-solution activity. See MPEP 2106.05(g).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements are “mere instructions to apply” and “insignificant extra-solution activity”. Further, the receiving an indication limitation recites the well-understood, routine, and conventional activity of receiving or transmitting data over a network. MPEP 2106.05(d)(II); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network). Additionally, the receiving synchronization information limitations recite the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Mere instructions to apply an exception and insignificant extra-solution activity cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 4,
Claim 4 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 4 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 24.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are additional details that do not apply the exception in a meaningful way (See MPEP 2106.05(e)).
The limitations:
“wherein the delay is based on a callback function or a parallel thread”
As drafted, are additional elements that do not apply an exception for the abstract ideas in a meaningful way. See MPEP 2106.05(e).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements do not apply the exception in a meaningful way. The claim is not patent eligible.
Regarding Claim 5,
Claim 5 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 5 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the determining the time to run the first ML model comprises determining whether to insert a delay between layers of the first ML model”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 1.
Step 2B Analysis: See corresponding analysis of claim 1.
Regarding Claim 6,
Claim 6 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 6 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“determining the time to run the first ML model comprises determining a difference between an expected time to run a second ML model and a current time, the time to run the first ML model being based on the difference”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 1.
Step 2B Analysis: See corresponding analysis of claim 1.
Regarding Claim 7,
Claim 7 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 7 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the determining the time to run the first ML model comprises determining a difference between an expected time to run the first ML model and a current time”
“adjusting a next expected time to run a subsequent ML model of the ML models based on the difference”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 1.
Step 2B Analysis: See corresponding analysis of claim 1.
Regarding Claim 8,
Claim 8 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 8 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 7.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are mere instructions to apply an exception (See MPEP 2106.05(f)).
The limitations:
“removing a delay of the running of the first ML model based on the difference”
As drafted, are additional elements that amount to no more than mere instructions to apply an exception. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements are “mere instructions to apply”. The claim is not patent eligible.
Regarding Claim 9,
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 9 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“simulate running the set of ML models …to determine resources utilized by running the ML models of the set of ML models and to determine execution resources for running the ML models”
“determine, based on the simulation, to delay running a ML model of the set of ML models based on the simulation”
“generate synchronization information to run the ML models of the set of ML models based on the determined delay, the synchronization information ordering running of the ML models of the set of ML models relative to each other in a pattern”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are mere instructions to apply an exception (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)).
The limitations:
“A non-transitory program storage device comprising instructions stored thereon to cause one or more processors to”
“on a target hardware”
As drafted, are additional elements that amount to no more than mere instructions to apply an exception for the abstract ideas. See MPEP 2106.05(f).
The limitations:
“receive a set of machine learning (ML) models”
As drafted, are additional elements that amount to no more than insignificant extra-solution activity. See MPEP 2106.05(g).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements are “mere instructions to apply” and “insignificant extra-solution activity”. Additionally, the receiving limitation recites the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Mere instructions to apply an exception and insignificant extra-solution activity cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 10,
Claim 10 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 10 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 9.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are additional details that do not apply the exception in a meaningful way (See MPEP 2106.05(e)).
The limitations:
“wherein the target hardware includes at least two cores for executing the set of ML models”
As drafted, are additional elements that do not apply an exception for the abstract ideas in a meaningful way. See MPEP 2106.05(e).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements do not apply the exception in a meaningful way. The claim is not patent eligible.
Regarding Claim 12,
Claim 12 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 12 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 25.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are additional details that do not apply the exception in a meaningful way (See MPEP 2106.05(e)).
The limitations:
“wherein the synchronization information is organized in a lookup table”
As drafted, are additional elements that do not apply an exception for the abstract ideas in a meaningful way. See MPEP 2106.05(e).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements do not apply the exception in a meaningful way. The claim is not patent eligible.
Regarding Claim 13,
Claim 13 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 13 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 9.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are mere instructions to apply an exception (See MPEP 2106.05(f)).
The limitations:
“wherein delaying running of the ML model of the set of ML models includes inserting a delay before beginning to run the ML model”
As drafted, are additional elements that amount to no more than mere instructions to apply an exception. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements are “mere instructions to apply”. The claim is not patent eligible.
Regarding Claim 14,
Claim 14 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 14 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 9.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are mere instructions to apply an exception (See MPEP 2106.05(f)).
The limitations:
“wherein delaying running of the ML model comprises inserting a delay between layers of the ML model”
As drafted, are additional elements that amount to no more than mere instructions to apply an exception. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements are “mere instructions to apply”. The claim is not patent eligible.
Regarding Claim 15,
Claim 15 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 15 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 9.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are additional details that do not apply the exception in a meaningful way (See MPEP 2106.05(e)).
The limitations:
“wherein determining to delay the running the ML model is based on one or more cost functions”
As drafted, are additional elements that do not apply an exception for the abstract ideas in a meaningful way. See MPEP 2106.05(e).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements do not apply the exception in a meaningful way. The claim is not patent eligible.
Regarding Claim 16,
Claim 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 16 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 15.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are additional details that do not apply the exception in a meaningful way (See MPEP 2106.05(e)).
The limitations:
“wherein a cost function of the one or more cost functions is based on at least one of a memory bandwidth, an amount of power consumed, and a size of available memory”
As drafted, are additional elements that do not apply an exception for the abstract ideas in a meaningful way. See MPEP 2106.05(e).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements do not apply the exception in a meaningful way. The claim is not patent eligible.
Regarding Claim 17,
Claim 17 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 17 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 15.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are additional details that do not apply the exception in a meaningful way (See MPEP 2106.05(e)).
The limitations:
“wherein a cost function of the one or more cost functions is based on an amount of delays added to the set of ML models”
As drafted, are additional elements that do not apply an exception for the abstract ideas in a meaningful way. See MPEP 2106.05(e).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements do not apply the exception in a meaningful way. The claim is not patent eligible.
Regarding Claim 18,
Claim 18 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 18 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“determining at least an amount of memory bandwidth, power, and memory size used when executing the set of ML models on the target hardware”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 9.
Step 2B Analysis: See corresponding analysis of claim 9.
Regarding Claim 19,
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 19 is directed to an electronic device, comprising: a memory; and one or more processors operatively coupled to the memory, wherein the one or more processors are configured to execute instructions, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“determine, based on the synchronization information, a time to run the first ML model”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are mere instructions to apply an exception (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)).
The limitations:
“An electronic device, comprising: a memory; and one or more processors operatively coupled to the memory, wherein the one or more processors are configured to execute instructions”
“run the first ML model at the time”
As drafted, are additional elements that amount to no more than mere instructions to apply an exception for the abstract ideas. See MPEP 2106.05(f).
The limitations:
“receive an indication to run a first machine learning (ML) model”
“receive synchronization information that orders running of ML models relative to each other in a pattern, the ML models including the first ML model”
As drafted, are additional elements that amount to no more than insignificant extra-solution activity. See MPEP 2106.05(g).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements are “mere instructions to apply” and “insignificant extra-solution activity”. Further, the receiving an indication limitation recites the well-understood, routine, and conventional activity of receiving or transmitting data over a network. MPEP 2106.05(d)(II); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network). Additionally, the receiving synchronization information limitations recite the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Mere instructions to apply an exception and insignificant extra-solution activity cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 23,
Claim 23 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 23 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 1.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are additional details that do not apply the exception in a meaningful way (See MPEP 2106.05(e)).
The limitations:
“wherein the synchronization information includes: time values in an ordered pattern; and for each time value of the time values: a corresponding ML model of the ML models; and a corresponding processing core of the processing cores on which the corresponding ML model is to be run.”
As drafted, are additional elements that do not apply an exception for the abstract ideas in a meaningful way. See MPEP 2106.05(e).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements do not apply the exception in a meaningful way. The claim is not patent eligible.
Regarding Claim 24,
Claim 24 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 24 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 1.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are mere instructions to apply an exception (See MPEP 2106.05(f)).
The limitations:
“wherein running the first ML model at the time comprises inserting a delay before beginning running the first ML model”
As drafted, are additional elements that amount to no more than mere instructions to apply an exception. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements are “mere instructions to apply”. The claim is not patent eligible.
Regarding Claim 25,
Claim 25 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 25 is directed to a non-transitory program storage device comprising instructions stored thereon, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 9.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are additional details that do not apply the exception in a meaningful way (See MPEP 2106.05(e)).
The limitations:
“wherein the synchronization information includes: time values in an ordered pattern; and for each time value of the time values: a corresponding ML model of the set of ML models; and a corresponding processing core on which the corresponding ML model is to be run”
As drafted, are additional elements that do not apply an exception for the abstract ideas in a meaningful way. See MPEP 2106.05(e).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements do not apply the exception in a meaningful way. The claim is not patent eligible.
Regarding Claim 26,
Claim 26 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 26 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations
“updating a subsequent time value of the time values of the synchronization information that immediately follows the time value pointed to by the current context index based on a difference between the time value pointed to by the current context index and the current time”
“updating the current context index”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recited additional elements that are mere instructions to apply an exception (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)).
The limitations:
“iteratively: delaying running of a respective corresponding ML model of the ML models that corresponds to a time value of the time values of the synchronization information pointed to by the current context index when the time value pointed to by the current context index is less than a current time”
“when the time value pointed to by the current context index is not less than the current time: running the respective corresponding ML model of the ML models that corresponds to the time value pointed to by the current context index, the respective corresponding ML model being run on the respective corresponding processing core”
As drafted, are additional elements that amount to no more than mere instructions to apply an exception for the abstract ideas. See MPEP 2106.05(f).
The limitations:
“receiving synchronization information that orders running of ML models relative to each other in a pattern, the synchronization information including time values in an ordered pattern and, for each time value of the time values, a corresponding ML model of the ML models and a corresponding processing core on which the corresponding ML model is to be run”
“obtaining a current context index”
As drafted, are additional elements that amount to no more than insignificant extra-solution activity. See MPEP 2106.05(g).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract ideas into a practical application, all of the additional elements are “mere instructions to apply” and “insignificant extra-solution activity”. Additionally, the receiving synchronization information and obtaining a current context index limitations recite the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Mere instructions to apply an exception and insignificant extra-solution activity cannot provide an inventive concept. The claim is not patent eligible.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-10 and 13-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chandra et al. (U.S. Patent Publication No. 2019/0266015) (“Chandra”).
Regarding claim 9, Chandra teaches a non-transitory program storage device comprising instructions stored thereon (Chandra [0144] “In an example, a computer-readable storage media or machine-readable storage media may include any medium that is capable of storing, encoding, or carrying instructions for execution by the computing device 1200 and that cause the computing device 1200 to perform any one or more of the techniques of the present disclosure… The computer-readable storage media is non-transitory in that the storage media does not consist of transitory propagating signals.” Chandra teaches a non-transitory program storage device comprising instructions.) to cause one or more processors to: receive a set of machine learning (ML) models (Chandra [0032] “FIG. 1 is a system diagram of a framework 100 that supports DNN workloads on an edge device in accordance with respective examples. The framework 100 includes one or more cameras 102A, 102B,102C that provide image data, e.g., streams, to DNN models 112A, 112B, and 112C. The DNN models 112A-112C may then be ran on various streams to create DNN workloads.”’ [0033] “Each DNN model 112A-112C has a given architecture and framework 114. After the DNN model has been downloaded to a local device available to the edge device, the framework 100 determines the DNN model's resource requirements using a profiler 110.” Chandra teaches receiving a set of ML models, such as DNN models 112A-112C.); simulate running the set of ML models on a target hardware to determine resources utilized by running the ML models of the set of ML models and to determine execution resources for running the ML models (Chandra [0033] “The resource requirements may include how much how much time the DNN model takes to run on a number of CPU cores or GPU cores under different utilizations. In an example, the profiler 110 uses a machine learning technique for estimating the resource requirements of each DNN model to avoid profiling running all possible scenarios.”; [0134] “In an experiment, the core allocator was run using a virtual machine with twelve cores and five DNN workloads of various architectures. The resource utilization of cores were varied. FIG. 8 illustrates the runtime of DNN workloads processing one minute of streaming data at 30 fps in accordance with respective examples.” Chandra teaches simulating the DNN models on a virtual machine to determine resources used when executing the machine learning models.); determine, based on the simulation, to delay running a ML model of the set of ML models based on the simulation (Chandra [0117] “Based on output from the profiler 110, the scheduler 108 calculates how much time for each of the above DNN workloads to finish the computation for each layer. In an example, it may take TC1 and TC2 time to finish the convolutional layers computations and TF1 and TF2 to finish the fully connected layers computations for DNN1 and DNN2 respectively.”; [0118] “In contrast, the scheduler 108 may start DNN1 first and then DNN2 after TC1 time [a delay] so that while DNN1 uses more memory and less CPU resources DNN2 is ran while DNN2 uses more CPU resources but less memory resources. Thus, system resources or better utilized and used more efficiently leading to better throughput. The same scheduling may be extended to accommodate more than two DNN workloads.” Chandra teaches scheduler 108 including a delay TC1 before running a model, which is based on the results of the profiler, which includes the simulation.); and generate synchronization information to run the ML models of the set of ML models based on the determined delay (Chandra [0117] “Based on output from the profiler 110, the scheduler 108 calculates how much time for each of the above DNN workloads to finish the computation for each layer. In an example, it may take TC1 and TC2 time to finish the convolutional layers computations and TF1 and TF2 to finish the fully connected layers computations for DNN1 and DNN2 respectively.” Chandra teaches calculating how much time for each of the above DNN workloads to finish the computation for each layer, corresponding to the generation of synchronization information to run the models, which includes delay TC1.), the synchronization information ordering running of the ML models of the set of ML models relative to each other in a pattern (Chandra [0118] “In contrast, the scheduler 108 may start DNN1 first and then DNN2 after TC1 time so that while DNN1 uses more memory and less CPU resources DNN2 is ran while DNN2 uses more CPU resources but less memory resources. Thus, system resources or better utilized and used more efficiently leading to better throughput. The same scheduling may be extended to accommodate more than two DNN workloads.” Chandra teaches starting DNN1 first and then DNN2 after a determined delay, corresponding to the ordering of running of the ML models relative to each other in a pattern.).
Regarding claim 10, Chandra teaches wherein the target hardware includes at least two cores for executing the set of ML models ([Chandra 0134] “In an experiment, the core allocator was run using a virtual machine with twelve cores and five DNN workloads of various architectures. The resource utilization of cores were varied. FIG. 8 illustrates the runtime of DNN workloads processing one minute of streaming data at 30 fps in accordance with respective examples.” Chandra teaches a virtual machine corresponding to target hardware, which includes twelve cores, thus including at least two cores.).
Regarding claim 13, Chandra teaches wherein delaying running of the ML model of the set of ML models includes inserting a delay before beginning to run the ML model (Chandra [0117] “Based on output from the profiler 110, the scheduler 108 calculates how much time for each of the above DNN workloads to finish the computation for each layer. In an example, it may take TC1 and TC2 time to finish the convolutional layers computations and TF1 and TF2 to finish the fully connected layers computations for DNN1 and DNN2 respectively.”; [0118] “In contrast, the scheduler 108 may start DNN1 first and then DNN2 after TC1 time [a delay] so that while DNN1 uses more memory and less CPU resources DNN2 is ran while DNN2 uses more CPU resources but less memory resources. Thus, system resources or better utilized and used more efficiently leading to better throughput. The same scheduling may be extended to accommodate more than two DNN workloads.” Chandra teaches scheduler 108 including delay TC1 before running a model.).
Regarding claim 14, Chandra teaches wherein delaying running of the ML model comprises inserting a delay between layers of the ML model (Chandra [0115] “The majority of architectures for CNNs have a number of convolutional layers followed by fully connected layers that only occur at the end. The scheduler 108 takes advantage of the fact that core and RAM requirements of convolutional layers and fully connected layers are orthogonal to each other. The scheduler 108 schedules multiple DNN workloads in such way a way that one DNN workload starts at the convolution layers when another DNN workload reaches the fully connected layer processing stage. The schedule 108 may do this by determining the time a first DNN workload will reach its fully connected computation. When this time is reached, a second DNN workload may be started that starts by processing convolutional layers.” Chandra teaches scheduler 108 inserting a delay between layers of a ML model.).
Regarding claim 15, Chandra teaches wherein determining to delay the running the ML model is based on one or more cost functions (Chandra [0055] “In an example, the mathematical model used by the allocator 108 is defined as: Let c.sub.i,j be the cost of assigning the ith core to the jth DNN workload. The cost matrix is defined to be the n×m matrix where n is the number of cores and m is number of DNN workloads. An assignment is a set of n entry positions in the cost matrix, no two of which lie in the same row or column. The sum of the n entries of an assignment is its cost. An assignment with the smallest possible cost is called an optimal assignment.”; [0061] “min total cost function” Chandra teaches a cost function to determine model scheduling and allocation.).
Regarding claim 16, Chandra teaches wherein a cost function of the one or more cost functions is based on at least one of a memory bandwidth, an amount of power consumed, and a size of available memory (Chandra [0041] “The profiler 110 keeps track of various system resources such as CPU, GPU and memory usage while varying various DNN parameters which are described below.” Chandra teaches memory cost functions including keeping track of memory usage, corresponding to memory bandwidth and available memory.).
Regarding claim 17, Chandra teaches wherein a cost function of the one or more cost functions is based on an amount of delays added to the set of ML models (Chandra [0055] “An assignment is a set of n entry positions in the cost matrix, no two of which lie in the same row or column. The sum of the n entries of an assignment is its cost. An assignment with the smallest possible cost is called an optimal assignment.”; [0117] “Based on output from the profiler 110, the scheduler 108 calculates how much time for each of the above DNN workloads to finish the computation for each layer. In an example, it may take TC1 and TC2 time to finish the convolutional layers computations and TF1 and TF2 to finish the fully connected layers computations for DNN1 and DNN2 respectively.”; [0118] “In contrast, the scheduler 108 may start DNN1 first and then DNN2 after TC1 time so that while DNN1 uses more memory and less CPU resources DNN2 is ran while DNN2 uses more CPU resources but less memory resources. Thus, system resources or better utilized and used more efficiently leading to better throughput. The same scheduling may be extended to accommodate more than two DNN workloads.” Chandra teaches at least one delay for DNN resource usage, such as TC1 and TC2, including a cost matrix for determining a cost function.).
Regarding claim 18, Chandra teaches wherein simulating running the set of ML models on the target hardware comprises determining at least an amount of memory bandwidth, power, and memory size used when executing the set of ML models on the target hardware (Chandra [0138] “At 1130, the DNN workloads are assigned to processing cores. The assignment may be based on current processing core utilization [power], current available memory [memory bandwidth], and the profiled amount of processing core utilization and memory the DNN workloads need [memory size]” Chandra teaches at least an amount of memory bandwidth, power, and memory size used when executing the set of ML models on the target hardware).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-8, 12, 19, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2022/0374274) (“Chen”) in view of Chandra et al. (U.S. Patent Publication No. 2019/0266015) (“Chandra”).
Regarding claim 1, Chen teaches a method, comprising: receiving an indication to run a first machine learning (ML) model (Chen [0072] “As mentioned previously, machine learning models may have various execution frequencies with which each runs. For example, one machine learning model may execute weekly, while another machine learning model may execute monthly. When both of these machine learning models are deployed to a production environment, timer 402 can determine whether a machine learning model is to run and/or when the machine learning model is to run.” Chen teaches a timer 402, which provides indications to run a plurality of machine learning models.); receiving, by a runtime controller, synchronization information that orders running of ML models relative to each other in a pattern (Chen [0072] “In some embodiments, timer 402 [a runtime controller] is configured to track an amount of time that has elapsed since a machine learning model has executed [synchronization information], an amount of time that has elapsed since production data has been retrieved, or other time periods. As mentioned previously, machine learning models may have various execution frequencies with which each runs. For example, one machine learning model may execute weekly, while another machine learning model may execute monthly. [a pattern]” Chen teaches timer 402, corresponding to a runtime controller, which receives model timing information, corresponding to synchronization information, which allows for various execution frequencies, such as one model executing weekly, while another executes monthly, which is a running of ML models relative to each other in a pattern.), the ML models to be run on processing cores, the ML models including the first ML model (Chen [0018] “In particular, in multi-thread environments, multiple machine learning models may be executed in parallel or substantially in parallel. For instance, while one processing core is used to execute one machine learning model, a different processing core can be used to execute another machine learning model.” Chen teaches the various ML models to be run on processing cores, which includes a first model.);
Chen fails to explicitly teach determining, by the runtime controller and based on the synchronization information, a time to run the first ML model on a first processing core of the processing cores; and running the first ML model on the first processing core at the time.
However, Chandra teaches determining, by the runtime controller and based on the synchronization information, a time to run the first ML model on a first processing core of the processing cores (Chandra [0035] “The allocator 106 includes two subcomponents: a core allocator and a DNN parameter allocator. The core allocator allocates of one or more cores 116A-116D to each DNN workload based on resource requirement of a DNN workload and current system utilization. [synchronization information]”; [0036] “The output of the allocator 106 is then fed into a scheduler 108 that decides the execution scheme for each of the DNN workloads.”; [0037] “The scheduler 108 [runtime controller] leverages the insights about DNN structures to determine when and how to run each DNN workload.” Chandra teaches allocating a DNN workload to a first processing core, which includes a scheduler 108 to determine a time to run that DNN workload on the processing core.); and running the first ML model on the first processing core at the time (Chandra [0138] “At 1130, the DNN workloads are assigned to processing cores. The assignment may be based on current processing core utilization, current available memory, and the profiled amount of processing core utilization and memory the DNN workloads need. At 1140, image streams are received. The image streams are mapped to DNN workloads. At 1150, the DNN workloads are scheduled to be executed. At 1160, the DNN workloads are executed at the scheduled time on the assigned processing core.” Chandra teaches the DNN workloads are executed at the scheduled time on the assigned processing core, corresponding to running a first ML model on a first processing core at the time.).
Chen and Chandra are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically applied to multi-core machine learning model execution. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen with the above teachings of Chandra. Doing so would ensure that no model workload is starved, even when the overall workload increases (Chandra [0018] “In addition, the DNN workloads are scheduled to ensure that no DNN workload is starved, even when the overall workload increases.”).
Regarding claim 4, Chen in view of Chandra teaches the method of claim 24, as discussed below in the rejection of claim 24, wherein the delay is based on a callback function or a parallel thread (Chen [0018] “In particular, in multi-thread environments, multiple machine learning models may be executed in parallel or substantially in parallel. For instance, while one processing core is used to execute one machine learning model, a different processing core can be used to execute another machine learning model. When it is determined that executing some machine learning models on the data will cause issues (e.g., running on one or more processing cores), based on the results of other machine learning models executing on that data (e.g., running on different processing cores), preventative actions may be initiated to conserve computing resources and ensure that those models are not executed.” Chen teaches parallel-threads including preventative actions such as not executing models, corresponding to a delay.).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen in view of Chandra for the same reasons disclosed below in the rejection of claim 24.
Regarding claim 5, Chen in view of Chandra teaches wherein the determining the time to run the first ML model comprises determining whether to insert a delay between layers of the first ML model (Chandra [0115] “The majority of architectures for CNNs have a number of convolutional layers followed by fully connected layers that only occur at the end. The scheduler 108 takes advantage of the fact that core and RAM requirements of convolutional layers and fully connected layers are orthogonal to each other. The scheduler 108 schedules multiple DNN workloads in such way a way that one DNN workload starts at the convolution layers when another DNN workload reaches the fully connected layer processing stage. The schedule 108 may do this by determining the time a first DNN workload will reach its fully connected computation. When this time is reached, a second DNN workload may be started that starts by processing convolutional layers.” Chandra teaches scheduler 108 inserting a delay between layers of a ML model.).
Chen and Chandra are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically applied to multi-core machine learning model execution. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen with the above teachings of Chandra. Doing so would ensure that no model workload is starved, even when the overall workload increases (Chandra [0018] “In addition, the DNN workloads are scheduled to ensure that no DNN workload is starved, even when the overall workload increases.”).
Regarding claim 6, Chen in view of Chandra teaches wherein: determining the time to run the first ML model comprises determining a difference between an expected time to run a second ML model and a current time (Chandra [0048] “The generated training data, as described above, may be used to learn a performance model for each DNN model. In an example, the performance model is learned by formulating a regression problem where given a DNN model and parameters Sr, Ci, Bs, and Pc the performance model predicts the run time and peak RAM usage of a given DNN model”; [0117] “Based on output from the profiler 110, the scheduler 108 calculates how much time for each of the above DNN workloads to finish the computation for each layer. In an example, it may take TC1 and TC2 time to finish the convolutional layers computations and TF1 and TF2 to finish the fully connected layers computations for DNN1 and DNN2 respectively.” Chandra teaches determining TC1 and TC2, which are expected/calculated time for running a first and second ML model DNN1 and DNN2.), the time to run the first ML model being based on the difference (Chandra [0117] “Based on output from the profiler 110, the scheduler 108 calculates how much time for each of the above DNN workloads to finish the computation for each layer. In an example, it may take TC1 and TC2 time to finish the convolutional layers computations and TF1 and TF2 to finish the fully connected layers computations for DNN1 and DNN2 respectively.”; [0118] “In contrast, the scheduler 108 may start DNN1 first and then DNN2 after TC1 time so that while DNN1 uses more memory and less CPU resources DNN2 is ran while DNN2 uses more CPU resources but less memory resources.” Chandra teaches running a first ML model based on the calculation of TC1 and TC2.).
Chen and Chandra are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically applied to multi-core machine learning model execution. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen with the above teachings of Chandra. Doing so would ensure that no model workload is starved, even when the overall workload increases (Chandra [0018] “In addition, the DNN workloads are scheduled to ensure that no DNN workload is starved, even when the overall workload increases.”).
Regarding claim 7, Chen in view of Chandra teaches wherein the determining the time to run the first ML model comprises determining a difference between an expected time to run the first ML model and a current time (Chandra [0048] “The generated training data, as described above, may be used to learn a performance model for each DNN model. In an example, the performance model is learned by formulating a regression problem where given a DNN model and parameters Sr, Ci, Bs, and Pc the performance model predicts the run time and peak RAM usage of a given DNN model”; [0117] “Based on output from the profiler 110, the scheduler 108 calculates how much time for each of the above DNN workloads to finish the computation for each layer. In an example, it may take TC1 and TC2 time to finish the convolutional layers computations and TF1 and TF2 to finish the fully connected layers computations for DNN1 and DNN2 respectively.” Chandra teaches determining TC1 and TC2, which are expected/calculated time for running a first and second ML model DNN1 and DNN2.), and further comprising adjusting a next expected time to run a subsequent ML model of the ML models based on the difference (Chandra [0118] “In contrast, the scheduler 108 may start DNN1 first and then DNN2 after TC1 time so that while DNN1 uses more memory and less CPU resources DNN2 is ran while DNN2 uses more CPU resources but less memory resources. Thus, system resources or better utilized and used more efficiently leading to better throughput. The same scheduling may be extended to accommodate more than two DNN workloads.”).
Chen and Chandra are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically applied to multi-core machine learning model execution. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen with the above teachings of Chandra. Doing so would ensure that no model workload is starved, even when the overall workload increases (Chandra [0018] “In addition, the DNN workloads are scheduled to ensure that no DNN workload is starved, even when the overall workload increases.”).
Regarding claim 8, Chen in view of Chandra teaches wherein the determining the time to run the first ML model further comprises removing a delay of the running of the first ML model based on the difference (Chandra [0118] “In contrast, the scheduler 108 may start DNN1 first and then DNN2 after TC1 time so that while DNN1 uses more memory and less CPU resources DNN2 is ran while DNN2 uses more CPU resources but less memory resources” Chandra teaches starting a first ML model after TC1, thus removing a delay based the difference TC1, wherein starting the model is being interpreted as removing the delay.).
Chen and Chandra are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically applied to multi-core machine learning model execution. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen with the above teachings of Chandra. Doing so would ensure that no model workload is starved, even when the overall workload increases (Chandra [0018] “In addition, the DNN workloads are scheduled to ensure that no DNN workload is starved, even when the overall workload increases.”).
Regarding claim 12, Chen in view of Chandra teaches the method of claim 25, as discussed below in the rejection of claim 25, wherein the synchronization information is organized in a lookup table (Chandra [0128] “The data shown in Tables 1 and 2 indicate that the described profiler 110 is able to accurately predict DNN memory usage and run times across various architectures.” Chandra teaches organizing model timing information in Tables 1 and 2, corresponding to synchronization information organized in a lookup table.).
Chen and Chandra are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically applied to multi-core machine learning model execution. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen with the above teachings of Chandra. Doing so would ensure that no model workload is starved, even when the overall workload increases (Chandra [0018] “In addition, the DNN workloads are scheduled to ensure that no DNN workload is starved, even when the overall workload increases.”).
Regarding claim 19, it is the electronic device embodiment of claim 1 with similar limitations to claim 1 and is rejected using the same reasoning found above in the rejection of claim 1. Further, Chen teaches an electronic device, comprising: a memory; and one or more processors operatively coupled to the memory, wherein the one or more processors are configured to execute instructions (Chen [0071] “Model execution subsystem 114 may include a set of modules, including a timer 402, a model selector 404, data duplication 406, data distribution 408, other modules, or other components. Each module of model execution subsystem 114 may be implemented by one or more processors executing computer program instructions stored in memory of computer system 102.”).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen in view of Chandra for the same reasons disclosed below in the rejection of claim 1.
Regarding claim 23, Chen in view of Chandra teaches wherein the synchronization information includes: time values in an ordered pattern (Chen [0072] “In some embodiments, timer 402 [a runtime controller] is configured to track an amount of time that has elapsed since a machine learning model has executed [synchronization information], an amount of time that has elapsed since production data has been retrieved, or other time periods. As mentioned previously, machine learning models may have various execution frequencies with which each runs. For example, one machine learning model may execute weekly, while another machine learning model may execute monthly. [a pattern]” Chen teaches timer 402, corresponding to a runtime controller, which receives model timing information, corresponding to synchronization information, which allows for various execution frequencies, such as one model executing weekly, while another executes monthly, which is a running of ML models relative to each other in a pattern.); and for each time value of the time values: a corresponding ML model of the ML models (Chen [0072] “In some embodiments, timer 402 [a runtime controller] is configured to track an amount of time that has elapsed since a machine learning model has executed [synchronization information], an amount of time that has elapsed since production data has been retrieved, or other time periods.); and a corresponding processing core of the processing cores on which the corresponding ML model is to be run (Chen [0018] “In particular, in multi-thread environments, multiple machine learning models may be executed in parallel or substantially in parallel. For instance, while one processing core is used to execute one machine learning model, a different processing core can be used to execute another machine learning model.”).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen in view of Chandra for the same reasons disclosed below in the rejection of claim 1.
Regarding claim 24, Chen in view of Chandra teaches wherein running the first ML model at the time comprises inserting a delay before beginning running the first ML model (Chandra [0117] “Based on output from the profiler 110, the scheduler 108 calculates how much time for each of the above DNN workloads to finish the computation for each layer. In an example, it may take TC1 and TC2 time to finish the convolutional layers computations and TF1 and TF2 to finish the fully connected layers computations for DNN1 and DNN2 respectively.”; [0118] “In contrast, the scheduler 108 may start DNN1 first and then DNN2 after TC1 time [a delay] so that while DNN1 uses more memory and less CPU resources DNN2 is ran while DNN2 uses more CPU resources but less memory resources. Thus, system resources or better utilized and used more efficiently leading to better throughput. The same scheduling may be extended to accommodate more than two DNN workloads.” Chandra teaches scheduler 108 including delay TC1 before running a model.).
Chen and Chandra are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically applied to multi-core machine learning model execution. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen with the above teachings of Chandra. Doing so would ensure that no model workload is starved, even when the overall workload increases (Chandra [0018] “In addition, the DNN workloads are scheduled to ensure that no DNN workload is starved, even when the overall workload increases.”).
Regarding claim 25, the rejection of claim 9 is incorporated herein. Further, the limitations in this claim are taught by Chen in view of Chandra for the same reasons disclosed above in the rejection of claim 23.
Claims 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2022/0374274) (“Chen”) in view of Dirac et al. (U.S. Patent Publication No. 2015/0379430) (“Dirac”).
Regarding claim 26, Chen teaches a method comprising: receiving synchronization information that orders running of ML models relative to each other in a pattern, the synchronization information including time values in an ordered pattern (Chen [0072] “In some embodiments, timer 402 is configured to track an amount of time that has elapsed since a machine learning model has executed [synchronization information], an amount of time that has elapsed since production data has been retrieved, or other time periods. As mentioned previously, machine learning models may have various execution frequencies with which each runs. For example, one machine learning model may execute weekly, while another machine learning model may execute monthly. [a pattern]” Chen teaches timer 402, corresponding to a runtime controller, which receives model timing information, corresponding to synchronization information, which allows for various execution frequencies, such as one model executing weekly, while another executes monthly, which is a running of ML models relative to each other in a pattern.) and, for each time value of the time values, a corresponding ML model of the ML models and a corresponding processing core on which the corresponding ML model is to be run (Chen [0018] “In particular, in multi-thread environments, multiple machine learning models may be executed in parallel or substantially in parallel. For instance, while one processing core is used to execute one machine learning model, a different processing core can be used to execute another machine learning model.” Chen teaches a corresponding ML model of the ML models and a corresponding processing core on which the corresponding ML model is to be run.) …the respective corresponding ML model being run on the respective corresponding processing core (Chen [0018] “In particular, in multi-thread environments, multiple machine learning models may be executed in parallel or substantially in parallel. For instance, while one processing core is used to execute one machine learning model, a different processing core can be used to execute another machine learning model.” Chen teaches a corresponding ML model of the ML models and a corresponding processing core on which the corresponding ML model is to be run.);
Chen fails to explicitly teach obtaining a current context index; iteratively: delaying running of a respective corresponding ML model of the ML models that corresponds to a time value of the time values of the synchronization information pointed to by the current context index when the time value pointed to by the current context index is less than a current time; when the time value pointed to by the current context index is not less than the current time: running the respective corresponding ML model of the ML models that corresponds to the time value pointed to by the current context index, …and updating a subsequent time value of the time values of the synchronization information that immediately follows the time value pointed to by the current context index based on a difference between the time value pointed to by the current context index and the current time; and updating the current context index.
However, Dirac teaches obtaining a current context index (Dirac [0111] “As indicated on client timeline TL1, API1 through API4 may be invoked within the time period t0 to t1”; [0121] “In some embodiments, the MLS may support recurring scheduling of related jobs. For example, a client may create an artifact such as a model, and may want that same model to be re-trained and/or re-executed for different input data sets (e.g., using the same configuration of resources for each of the training or prediction iterations) at specified points in time.” Dirac teaches executing a model at specified points in time t0, t1, t2, etc., wherein a specified point in time corresponds to a current context index, as shown in Figure 5.); iteratively: delaying running of a respective corresponding ML model of the ML models that corresponds to a time value of the time values of the synchronization information pointed to by the current context index when the time value pointed to by the current context index is less than a current time (Dirac [0112] “As shown in the job scheduler timeline TL3, job J1 may be scheduled for execution at time t2. The delay [delaying running] between the insertion of J1 in queue 142 (shortly after t0) and the scheduling of J1 may occur for a number of reasons in the depicted embodiment—e.g., because there may have been other jobs ahead of J1 in the queue 142, or because it takes some time to generate a processing plan for J1 and identify the resources to be used for J1, or because enough resources were not available until t2. J1's execution lasts until t3.”; [0121] “In some embodiments, the MLS may support recurring scheduling of related jobs. For example, a client may create an artifact such as a model, and may want that same model to be re-trained and/or re-executed for different input data sets (e.g., using the same configuration of resources for each of the training or prediction iterations) at specified points in time. In some cases the points in time may be specified explicitly (e.g., by the client requesting the equivalent of “re-run model M1 on the currently available data set at data source DS1 at 11:00, 15:00 and 19:00 every day”)” Dirac teaches scheduling daily (iterative) model execution, as shown in Fig. 5, wherein the model execution is delayed until the scheduled execution time is reached, corresponding to iteratively delaying a model while a time value (e.g., 11:00) is less than a current time.); when the time value pointed to by the current context index is not less than the current time: running the respective corresponding ML model of the ML models that corresponds to the time value pointed to by the current context index (Dirac [0121] “In some embodiments, the MLS may support recurring scheduling of related jobs. For example, a client may create an artifact such as a model, and may want that same model to be re-trained and/or re-executed for different input data sets (e.g., using the same configuration of resources for each of the training or prediction iterations) at specified points in time. In some cases the points in time may be specified explicitly (e.g., by the client requesting the equivalent of “re-run model M1 on the currently available data set at data source DS1 at 11:00, 15:00 and 19:00 every day”)” Dirac teaches running the model when a current time is equal to the scheduled model execution time, corresponding to running the model when the specified time value is not less than a current time.) …and updating a subsequent time value of the time values of the synchronization information that immediately follows the time value pointed to by the current context index based on a difference between the time value pointed to by the current context index and the current time (Dirac [0114] “At t5, the portion of J3 on which J4 depends may be complete, and the client may be notified accordingly. However, J4 also depends on the completion of J2, so J4 cannot be started until J2 completes at t6. J3 continues execution until t8. J4 completes at t7, earlier than t8. The client is notified regarding the completion of each of the jobs corresponding to the respective API invocations API1-API4 in the depicted example scenario. In some embodiments, partial dependencies between jobs may not be supported—instead, as mentioned earlier, in some cases such dependencies may be converted into full dependencies by splitting multi-phase jobs into smaller jobs.” Dirac teaches updating time values t0-t8 based on the differing execution times, as shown in Fig 5, which includes differences between the time values and a current time.); and updating the current context index (Dirac [0111] “As indicated on client timeline TL1, API1 through API4 may be invoked within the time period t0 to t1”; [0121] “In some cases the points in time may be specified explicitly (e.g., by the client requesting the equivalent of “re-run model M1 on the currently available data set at data source DS1 at 11:00, 15:00 and 19:00 every day”). In other cases the client may indicate the conditions under which the iterations are to be scheduled (e.g., by the client requesting the equivalent of “re-run model M1 whenever the next set of 1000000 new records becomes available from data source DS1”). A respective job may be placed in the MLS job queue for each recurring training or execution iteration.” Dirac teaches executing a model at the next context index t1, t2, t3, corresponding to updating the current context index.).
Chen and Dirac are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically applied to machine learning model execution. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen with the above teachings of Dirac. Doing so would may improve the quality of predictions made by a machine learning model (Dirac [0186] “FIG. 26 illustrates an example of an iterative procedure that may be used to improve the quality of predictions made by a machine learning model, according to at least some embodiments.”).
Response to Arguments
Regarding the rejection applied under 35 U.S.C. 101, Applicant firstly asserts that independent claim 1 does not recite any abstract ideas (“Remarks”, Pages 1-2). Applicant further asserts that even if claim 1 were deemed to recite abstract ideas, the claim provides an improvement in computer capabilities by enabling balancing of resource requirements for running a machine learning model (“Remarks”, Page 2).
However, Claim 1 recites at least the abstract idea of “determining … based on the synchronization information, a time to run the first ML model on a first processing core of the processing cores”. The recitation of a “runtime controller” to perform the determining corresponds to mere instructions to apply an exception for the abstract ideas, consistent with MPEP 2106.05(f). For example, one can mentally “determine” a time to run a machine learning model, with or without the assistance of pen and paper by, for example, making a determination of a time based on available data. Therefore, the claim recites at least an abstract idea. Regarding the asserted improvement, even assuming the claims did recite an improvement, it would be in the abstract idea of determining a time to run the model. The MPEP notes that it is important to keep in mind that an improvement in the abstract idea itself is not an improvement in technology. MPEP 2106.05(a)(II).
Applicant further asserts that independent claim 9 does not recite any abstract ideas (“Remarks”, Page 3). Regarding independent claim 19, applicant asserts the claim recites a “processor” to perform the “determining” and therefore the claim does not recite a mental process (“Remarks”, Page 4).
However, for similar reasons discussed above regarding claim 1 reciting abstract ideas, claims 9 and 19 similarly recites abstract ideas (i.e., determinations of time). Further, the use of a “processor” to perform the determining corresponds to mere instructions to apply an exception for the abstract ideas, consistent with MPEP 2106.05(f). Therefore, the claims as written remain rejected under 35 U.S.C. 101.
Regarding the rejection applied under 35 U.S.C. 102/103, Applicant asserts that Chen fails to teach running models relative to each other in a pattern (“Remarks”, Pages 5-6). Applicant further asserts that the model execution frequency of Chen does not teach a pattern because the timing of execution of a ML may vary from a corresponding frequency, which may change any ordering of execution of the ML models which would not be a pattern (“Remarks”, Page 6).
However, Chen does teach running models relative to each other in a pattern. For example, as disclosed in paragraph [0072] of Chen discloses “machine learning models may have various execution frequencies with which each runs. For example, one machine learning model may execute weekly, while another machine learning model may execute monthly”. This is a “pattern” because a pattern, in this context, is merely a repeated arrangement of actions. Some models executing weekly while others execute monthly is repeated arrangement of actions for the machine learning models, which is therefore a running of models relative to each other in a pattern. Therefore, Chen teaches the limitation, as written.
Conclusion
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/KURT NICHOLAS PRESSLY/Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
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