Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 14 November 2025 has been entered. Claims 1-10 remain pending in the application.
Response to Arguments
Rejections under 35 U.S.C. 103
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Nevertheless, Examiner notes that Martin discloses the amended language as detailed below.
Claim Rejections – 35 USC § 103
Claims 1, 2, 3, 7, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Fishel et. al. (US 20190340488 A1), hereinafter known as Fishel, in view of Martin (US 20190147327 A1), hereinafter known as Martin.
Regarding claim 1, Fishel teaches a device comprising:
one or more memories for holding a plurality of pixel values and j compressed weighting factors (Fishel, Fig. 3 element 230);
a first DMA (Direct Memory Access) controller for transferring the j compressed weighting factors read from the memories to the decompressor (Fishel, Fig. 3 element 324);
n (n > k) accumulators for multiplying the plurality of pixel values and the k uncompressed weighting factors, and for adding cumulatively the multiplication result to a time series (Fishel, Fig. 3 elements 314A-N; ¶ [0046]); and…
Fishel does not teach:
a decompressor for restoring the j compressed weighting factors to k (k
≥
j) uncompressed weighting factors, wherein each of the j compressed weighting factors include map data representing locations of non-zero coefficients, and wherein the decompressor restores the j compressed weighting factors to the k uncompressed weighting factors based on the included map data;
a first switch circuit provided between the decompressor and the n accumulators, for transferring the k uncompressed weighting factors to the n accumulators based on a first correspondence represented by a first identifier included in each of the compressed weighting factors, wherein the correspondence is defined by a switch control circuit based on the first identifier such that the first switch is dynamically configured at runtime to optimize resource utilization of the n accumulators,
wherein at least one of the k uncompressed weighting factors is transferred to two or more of the n accumulators by the first switch circuit in accordance with the first correspondence.
However, Martin teaches:
a decompressor for restoring the j compressed weighting factors to k (k
≥
j) uncompressed weighting factors (Martin, Fig. 2 element 240 and ¶ [0194]), wherein each of the j compressed weighting factors include map data representing locations of non-zero coefficients (Martin Fig. 4 elements 407 and ¶ [0144], [0197]-[0210], and wherein the decompressor restores the j compressed weighting factors to the k uncompressed weighting factors based on the included map data (Martin, ¶ [0199]-[0204]);
a first switch circuit provided between the decompressor and the n accumulators (Martin, Fig. 2 element 242), for transferring the k uncompressed weighting factors to the n accumulators based on a first correspondence represented by a first identifier included in each of the compressed weighting factors (Martin, Fig. 4 element 411 as first correspondence, elements 405 as first identifiers included with weights; ¶ [0208]-[0209]), wherein the correspondence is defined by a switch control circuit based on the first identifier (Martin, Fig. 3 element 304 as switch control circuit; ¶ [0150]-[0151], [0195]) such that the first switch is dynamically configured at runtime to optimize resource utilization of the n accumulators (Martin, ¶ [0173], [0195], [0208]),
wherein at least one of the k uncompressed weighting factors is transferred to two or more of the n accumulators by the first switch circuit in accordance with the first correspondence (Martin, Figs. 2-4 and ¶ [0166], [0172]-[0175], [0194]-[0196]; the same set of weights, identified by a filter index, are provided to multiple neuron engines as shown in Fig. 4; “different neuron engines working on the same filter may be restricted to operate on the same portion of the weights of a filter” [0195]).
Fishel and Martin are both considered to be analogous to the claimed invention because they are in the same field of convolution neural networks. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Fishel to include the weight buffer and crossbar switch of Martin. This modification would have been obvious because decompressing the weights external to the neuron engines and providing a crossbar switch to interconnect the neuron engines to the weight buffer allows each of the neuron engines to access data in any of the weight buffers (Martin, ¶ [0099]).
Regarding claim 2, the combination of Fishel in view of Martin teaches the invention substantially as claimed. See the rejection of claim 1 above. Fishel further teaches:
wherein the memories hold the j compressed weighting factors as a weighting factor data set along with the first identifier (Fishel, ¶ [0094]),
wherein the first DMA controller reads the weighting factor data set from the memories and transfers the j compressed weighting factors included in the weighting factor data set to the decompressor (Fishel, Fig. 3 element 324), and…
Fishel does not teach:
wherein the switch control circuit controls the first correspondence in the first switch circuit based on the first identifier included in the weighting factor data set read by the first DMA controller.
However, Martin teaches:
wherein the switch control circuit controls the first correspondence in the first switch circuit based on the first identifier included in the weighting factor data set read by the first DMA controller (Martin, ¶ [0173]).
Regarding claim 3, the combination of Fishel in view of Martin teaches the invention substantially as claimed. See the rejection of claim 1 above. Martin further teaches:
wherein the first switch circuit transfers at least one of the k uncompressed weighting factors to two or more of the n accumulators (Martin, ¶ [0213]).
Regarding claim 7, Fishel teaches:
a neural network engine for executing neural network processing (Fishel, Fig. 2 element 218);
one or more memories for holding a plurality of pixel values and j compressed weighting factors (Fishel, Fig. 2 element 230);
a processor (Fishel, Fig. 2 element 208); and
a bus for connecting the neural network engine, the memories and the processor to each other (Fishel, Fig. 2 element 232), wherein the neural network engine further comprising…
a first DMA (Direct Memory Access) controller for transferring the j compressed weighting factors read from the memories to the decompressor (Fishel, Fig. 3 element 324);
n (n
≥
k) accumulators for multiplying the plurality of pixel values and the k uncompressed weighting factors, and adding cumulatively the multiplication result to time series (Fishel, Fig. 3 elements 314A-N; ¶ [0046]);
Fishel does not teach:
a decompressor for restoring the j compressed weighting factors to k (k
≥
j) uncompressed weighting factors, wherein each of the j compressed weighting factors includes map data representing locations of non-zero coefficients, and wherein the decompressor restores the j compressed weighting factors to the k uncompressed weighting factors based on the map data included in the respective compressed weighting factors;
a first switch circuit provided between the decompressor and the n accumulator for transferring the k uncompressed weighting factors to the n accumulators, based on a first correspondence represented by a first identifier included in each of the compressed weighting identifiers, wherein the correspondence is defined by a switch control circuit based on the first identifier such that the first switch circuit is dynamically configured at runtime to optimize resource utilization of the n accumulators; and
the switch control circuit for controlling the first correspondence in the first switch circuit based on the first identifier, wherein the switch control circuit generates a switch control signal based on the first identifier included in the compressed weighting factors,
wherein at least one of the k uncompressed weighting factors is transferred to two or more of the n accumulators by the first switch circuit in accordance with the first correspondence.
However, Martin teaches:
a decompressor for restoring the j compressed weighting factors to k (k
≥
j) uncompressed weighting factors (Martin, Fig. 2 element 240 and ¶ [0194]), wherein each of the j compressed weighting factors includes map data representing locations of non-zero coefficients (Martin, Fig. 4 element 407 and ¶ [0144], [0197]-[0210]), and wherein the decompressor restores the j compressed weighting factors to the k uncompressed weighting factors based on the map data included in the respective compressed weighting factors (Martin, ¶ [0199]-[0204]);
a first switch circuit provided between the decompressor and the n accumulator (Martin, Fig. 2 element 242) for transferring the k uncompressed weighting factors to the n accumulators, based on a first correspondence represented by a first identifier included in each of the compressed weighting identifiers (Martin, Fig. 4 element 411 as first correspondence, elements 405 as first identifiers included with weights; ¶ [0208]-[0209]), wherein the correspondence is defined by a switch control circuit based on the first identifier (Martin, Fig. 3 element 304 as switch control circuit; ¶ [0150]-[0151], [0195]) such that the first switch circuit is dynamically configured at runtime to optimize resource utilization of the n accumulators (Martin, ¶ [0173], [0195], [0208]); and
the switch control circuit (Martin, Fig. 3 element 304) for controlling the first correspondence in the first switch circuit based on the first identifier, wherein the switch control circuit generates a switch control signal based on the first identifier included in the compressed weighting factors (Martin, ¶ [0208]),
wherein at least one of the k uncompressed weighting factors is transferred to two or more of the n accumulators by the first switch circuit in accordance with the first correspondence (Martin, Figs. 2-4 and ¶ [0166], [0172]-[0175], [0194]-[0196]; the same set of weights, identified by a filter index, are provided to multiple neuron engines as shown in Fig. 4; “different neuron engines working on the same filter may be restricted to operate on the same portion of the weights of a filter” [0195]).
Regarding claim 8, the combination of Fishel in view of Martin teaches the invention substantially as claimed. See the rejection of claim 7 above. Fishel further teaches:
wherein the processor outputs the first identifier… …when the first DMA controller transfers the j compressed weighting factors to the decompressor (Fishel, ¶ [0047] and [0061]).
Fishel does not teach:
…to the switch control circuit…
However, Martin teaches:
…to the switch control circuit… (Martin, Fig. 3 element 304 as switch control circuit; [0133]).
Regarding claim 9, the combination of Fishel in view of Martin teaches the invention substantially as claimed. See the rejection of claim 7 above. Martin further teaches:
wherein the first switch circuit transfers at least one of the k uncompressed weighting factors to two or more of the n accumulators (Martin, ¶ [0213]).
Claims 4, 5, and 10 are rejected under 35 U.S.C. as being unpatentable over Fishel, in view of Martin, and further in view of Fujii et. al. (US 202101173532 A1), hereinafter known as Fujii.
Regarding claim 4, the combination of Fishel in view of Martin teaches the invention substantially as claimed. See the rejection of claim 1 above. The combination of Fishel and Martin do not teach:
a second DMA controller for transferring the output of the n accumulators to the memories;
and a second switch circuit provided between the n accumulators and the second DMA controller for transferring the output of the n accumulators to a plurality of channels in the second DMA controller based on a second correspondence represented by a second identifier.
However, Fujii does teach:
a second DMA controller for transferring the output of the n accumulators to the memories (Fujii, Fig. 27 element 61 and ¶ [0205]);
and a second switch circuit provided between the n accumulators and the second DMA controller for transferring the output of the n accumulators to a plurality of channels in the second DMA controller based on a second correspondence represented by a second identifier (Fujii, Fig. 27 the programmable switch situated between the plurality of computing units and the DMAC 61; ¶ [0081], [0206], and [0221]).
Fujii is considered to be analogous to the claimed invention because it is in the same field of convolution neural networks. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fishel in view of Martin to include the output DMA controller and switch circuit of Fujii. This modification would have been obvious because this allows the resulting data to be transferred to the external memories (Fujii, ¶ [0217]).
Regarding claim 5, the combination of Fishel, Martin, and Fujii teaches the invention substantially as claimed. See the rejection of claim 4 above. Martin further teaches:
a switch control circuit (Martin, Fig. 3 element 304 as switch control circuit; [0133]),
wherein the memories hold the j compressed weighting factors as a weighting factor data set along with the first identifier and the second identifier (Martin, Fig. 4 element 404; Fig. 4 elements 405 and 407 as identifiers; ¶ [0197]),
wherein the switch control circuit controls the first correspondence in the first switch circuit and the second correspondence in the second switch circuit respectively based on the first identifier and the second identifier included in the weighting factor data set read by the first DMA controller (Martin, Fig. 3 element 304 as switch control circuit; Fig. 2 element 242 as first and second switch circuits, a crossbar contains multiple switches; ¶ [0133]) .
Regarding claim 10, the combination of Fishel in view of Martin teaches the invention substantially as claimed. See the rejection of claim 7 above. The combination of Fishel and Martin do not teach:
a second DMA controller for transferring the output of the n accumulators to the memories;
and a second switch circuit provided between the n accumulators and the second DMA controller for transferring an output of the n accumulators to the second DMA controller based on a second correspondence represented by a second identifier.
However, Fujii does teach:
a second DMA controller for transferring the output of the n accumulators to the memories (Fujii, Fig. 27 element 61 and ¶ [0205]);
and a second switch circuit provided between the n accumulators and the second DMA controller for transferring the output of the n accumulators to the second DMA controller based on a second correspondence represented by a second identifier (Fujii, Fig. 27 the programmable switch situated between the plurality of computing units and the DMAC 61; ¶ [0081], [0206], and [0221]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Fishel, in view of Martin, and further in view of Wang (US 20220121551 A1), hereinafter known as Wang.
Regarding claim 6, the combination of Fishel and Martin teaches the invention substantially as claimed. See the rejection of claim 1 above.
The combination of Fishel in view of Martin does not teach further comprising:
a third DMA controller for transferring the plurality of pixel values read from the memories to the n accumulators.
However, Wang teaches further comprising:
a third DMA controller for transferring the plurality of pixel values read from the memories to the n accumulators (Wang, Fig. 3 element EIDMA; ¶ [0046] and [0145]-[0146]).
Wang is considered to be analogous to the claimed invention because it is in the same field of convolution neural networks. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Fishel in view of Martin to include the input DMA of Wang. This modification would have been obvious because implementing separate DMAs for input data and weight data allows the data retrieval to be performed synchronously in parallel, thereby improving the processing performance of the device (Wang, [0233]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN DAVID WARNER whose telephone number is (703)756-5956. The examiner can normally be reached M-F: 9-5.
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/J.D.W./
Jonathan David WarnerExaminer, Art Unit 2182
(703) 756-5956
/NICHOLAS KLICOS/Primary Examiner, Art Unit 2118