Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on March 16, 2026 has been received and entered. Claims 1, 11, and 16-20 have been amended. Claims 2-4, 6-7, and 12 have been cancelled. Claims 1, 5, 8-11, and 13-20 are pending for examination.
Rejections and/or objections not reiterated from previous office actions are hereby withdrawn. The following rejections and/or objections are either reiterated or newly applied. They constitute the complete set presently being applied to the instant application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/16/2026 has been considered by the examiner. Please see attached PTO-1449.
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5, 8 , 10, 11, 13, 16, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jess et al. (U.S. Pat. No. 9,170,756) in view of Kamalavannan (U.S. Pat. No. 9,268,493).
Referring to claim 1, Jess et al. teaches an apparatus comprising:
a memory (a computer memory, see Jess et al., Para. 41) system comprising:
a first storage medium associated with a first performance characteristic, and a second storage medium associated with a second performance characteristic (In order to enhance overall system performance, it may be desirable to allocate data having a high activity level (e.g. 1/0 requests are addressed to the data at a high frequency) to high-performance storage pools and/or allocating data with a low activity levels (e.g. 1/0 requests are addressed to the data at a low frequency) to lower-performance storage pools. To affect an efficient DST solution, the size of the data blocks moved between storage pools may be smaller than a complete SCSI logical unit {LU}, see Jess et al., Para. 14), and
logic circuitry (The foregoing detailed description may include set forth various embodiments of the devices and/or processes via the use of block diagrams, flowcharts, and/or examples. Insofar as such block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood by those within the art that each function and/or operation within such block diagrams, flowcharts, or examples may be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. In one embodiment, several portions of the subject matter described herein may be implemented via Application Specific Integrated Circuits (AS/Cs), Field Programmable Gate Arrays {FPGAs), digital signal processors {DSPs}, or other integrated formats, see Jess et al., Para. 44. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein, in whole or in part, may be equivalently implemented in integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g., as one or more programs running on one or more microprocessors), as firmware, or as virtually any combination thereat and that designing the circuitry and/or writing the code for the software and or firmware would be well within the skill of one of skill in the art in light of this disclosure) configured to:
However, Jess et al. does not explicitly teach
receive, using a unified access protocol, a first user data write request associated with first data, wherein the first user data write request indicates the first storage medium,
route, using a first medium specific protocol, based on the first user data write request, the first data to the first storage medium,
receive, using the unified access protocol, a second user data write request associated with second data, wherein the second user data write request indicates the second storage medium,
translate between the unified access protocol and a second medium specific protocol, and
route, using the second medium specific protocol, based on the second user data write request, the second data to the second storage medium.
Kamalavannan teaches
receive, using a unified access protocol, a first user data write request associated with first data, wherein the first user data write request indicates the first storage medium (receives the write request from SAN I/O port 108A and analyzes the write request with a logical block addressing (LBA) table to determine how the data contained in the write request should be distributed among HDDs 106A, 106B, 106C, and 106D within RAID volume 118, see Kamalavannan, Col. 4, line 65-Col. 5, line 3),
route, using a first medium specific protocol, based on the first user data write request, the first data to the first storage medium (RAID engine 104A determines what portion of the data of the write request should be written to HDD 106D on storage subsystem 102B, an iSCSI-based subsystem. RAID engine 104 passes the write request to initiator port 112A, from which the write request is transmitted to switch 130 with instructions to transmit the write request to storage subsystem 102B, see Kamalavannan, Col. 5, lines 4-10),
receive, using the unified access protocol, a second user data write request associated with second data, wherein the second user data write request indicates the second storage medium (receives the write request from SAN I/O port 108A and analyzes the write request with a logical block addressing (LBA) table to determine how the data contained in the write request should be distributed among HDDs 106A, 106B, 106C, and 106D within RAID volume 118, see Kamalavannan, Col. 4, line 65-Col. 5, line 3),
translate between the unified access protocol and a second medium specific protocol (send a first protocol write request to the back-end switch through the first configurable back-end port operating in the initiator mode; and wherein the back-end switch is configured to convert the first protocol write request to a second protocol write request and send the second protocol write request to the second storage subsystem, see Kamalavannan, Col. 11, lines 10-15), and
route, using the second medium specific protocol, based on the second user data write request, the second data to the second storage medium (configure the second configurable back-end port to a target mode; receive the second protocol write request and, in response, write data to the second storage drive; configure the second configurable back-end port to an initiator mode; and send a second protocol write acknowledgement to the back-end switch through the second configurable backend port operated in the initiator mode, see Kamalavannan, Col. 11, lines 19-27).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jess et al., to have receive, using a unified access protocol, a first user data write request associated with first data, wherein the first user data write request indicates the first storage medium, route, using a first medium specific protocol, based on the first user data write request, the first data to the first storage medium, receive, using the unified access protocol, a second user data write request associated with second data, wherein the second user data write request indicates the second storage medium, translate between the unified access protocol and a second medium specific protocol, and route, using the second medium specific protocol, based on the second user data write request, the second data to the second storage medium, as taught by Kamalavannan, to prevent the sharing of storage resources across different subsystems, thus increasing costs and effort in maintaining heterogeneous storage environments (Kamalavannan, Col. 1, lines 43-45).
As to claim 5, Jess et al. teaches
the first storage medium comprises volatile storage medium (Referring to FIG. 2, one or more physical drives (e.g. drive 0-drive n) may be logically partitioned into one or more virtual drives ( e.g. virtual drive 104A-virtua/ drive 1040 of RAID 103). Portions of one or more virtual drives may be further partitioned into storage pools (e.g. storage pool 105A, storage pool 1058, etc.). A storage pool may be defined as one or more physical drives (or one or more logical partitions of the one or more physical drives) which have similar performance characteristics. For example, storage pool 105A (i.e. drive OJ may include high-performance Solid State Drives {SSDs) whereas storage pool 1058 (i.e. drive 1 and drive 2) may include lower performance devices such as Serial ATA {SATA) Hard Disk Drives {HDDs). Factors which may distinguish higher-performance storage pools from lower-performance storage pools may include numbers of 1/0 operations processed per unit time, number of bytes read or written per unit time, and/or average response time for an 1/0 request, see Jess et al., Para. 13), and the second storage medium comprises non-volatile storage medium (Referring to FIG. 2, one or more physical drives (e.g. drive 0-drive n) may be logically partitioned into one or more virtual drives (e.g. virtual drive 104A-virtua/ drive 1040 of RAID 103). Portions of one or more virtual drives may be further partitioned into storage pools (e.g. storage pool 105A, storage pool 1058, etc.). A storage pool may be defined as one or more physical drives (or one or more logical partitions of the one or more physical drives) which have similar performance characteristics. For example, storage pool 105A (i.e. drive OJ may include high-performance Solid State Drives {SSDs) whereas storage pool 1058 (i.e. drive 1 and drive 2) may include lower performance devices such as Serial ATA {SATA) Hard Disk Drives {HDDs). Factors which may distinguish higher-performance storage pools from lower performance storage pools may include numbers of 1/0 operations processed per unit time, number of bytes read or written per unit time, and/or average response time for an 1/0 request, see Jess et al., Para. 16, Such a methodology takes advantage of the fact that the LBAs to be written to the PTVV may already be present in the RAID controller 102 cache due to the host read operation. The read LBAs corresponding to the hot-spot LBAs missing from the destination PTVV may not be released for further use until the additional write operation completes. The controller firmware may support a special type of write operation where the source of the write data is not a host but data blocks that are already in controller cache, see Jess et al., Para. 36).
As to claim 8, Jess et al. teaches to organize the first storage medium and the second storage medium into a hierarchy based, at least in part, on the first performance characteristic and the second performance characteristic (Higher Performance vs. Lower Performance, see Jess et al., Para. 16 and 31-32).
As to claim 10, Jess et al. teaches wherein the logic circuitry is configured to organize the hierarchy based, at least in part, on a trigger (A hot-spot may be identified by the RAID controller 102 by monitoring the address locations for I/O requests received from the host 101. Upon exceeding a I/O request threshold (e.g. exceeding a specified request rate, number of requests, etc.), for a particular segment of LBAs in a given storage pool those LBAs may be designated as a hot-spot and subject to relocation to a storage pool having alternate performance characteristics, see Jess et al., Para. 17).
Referring to claim 11, Jess et al. teaches a method, which recites the corresponding limitations as set forth in claim 1 above; therefore, it is rejected under the same subject matter.
Claim 13 is rejected under the same rationale as stated in the claim 8 rejection.
Referring to claim 16, Jess et al. teaches an apparatus comprising
select, based on the second user data write request and a second category of the second data, the second performance characteristic (A storage pool in which hot-spot currently exists may be referred to as a source storage pool. A storage pool that a hot-spot may be moved to may be referred to as a destination storage pool. It should be noted that hot-spots may refer data which is accessed frequently and may be moved to a higher-performance storage pool or data which is accessed infrequently and may be moved to a lower-performance storage pool. Alternately, data that is accessed infrequently may be referred to as a cold-spot and may be moved to a lower-performance storage pool utilizing the same systems and methods as described herein with respect to hot-spot movement, see Jess et al., Para. 16. If the write request activity level of the hot-spot should decrease to a level where use of a higher performance storage pool is no longer necessary, the PiT associated with the active PTVV may be deleted and the contents of the active PTVV may be reintegrated into the previous PTVV. For example, if the activity in PTVV.sub.2 decreases below a threshold level, the contents of PTVV.sub.2 may be reintegrated into PTVV.sub.1. see Jess et al., Para. 31. Further, it is possible that the write hot-spot activity does not actually decrease but instead moves to a different LBA range. In this case, the hot-spot LBAs may still be located in the faster destination storage pool but there may be PTVV LBA segments in the PTVV that no longer qualify as hot-spots and should be transferred to a lower-performance storage pool, see Jess et al., Para. 32), which recites the corresponding limitations as set forth in claim 1 above; therefore, it is rejected under the same subject matter.
As to claim 17, Jess et al. teaches at least one accelerator processor configured to assist the logic circuitry to route the first data from the interface to the first storage medium interface (The foregoing detailed description may include set forth various embodiments of the devices and/or processes via the use of block diagrams, flowcharts, and/or examples. Insofar as such block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood by those within the art that each function and/or operation within such block diagrams, flowcharts, or examples may be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof In one embodiment, several portions of the subject matter described herein may be implemented via Application Specific Integrated Circuits {AS/Cs}, Field Programmable Gate Arrays {FPGAs), digital signal processors {DSPs}, or other integrated formats. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein, in whole or in part, may be equivalently implemented in integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g., as one or more programs running on one or more microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and or firmware would be well within the skill of one of skill in the art in light of this disclosure, see , Jess et al., Col. 7, lines 8-32).
As to claim 19, Jess et al. as modified teaches a protocol translation circuit configured to translate the second data from a first communication the unified access protocol to a second communication the second medium specific protocol (switch 130 may provide conversion between storage protocols, see Kamalavannan, Col. 4, lines 7-8).
Claims 9, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jess et al. (U.S. Pat. No. 9,170,756) in view of Kamalavannan (U.S. Pat. No. 9,268,493) as applied to claims 1, 5, 8 , 10, 11, 13, 16, 17 and 19 above, and in further view of Lee et al. (U.S. Pat. Pub. 2022/0253380).
As to claim 9, Jess et al. as modified does not explicitly teach to organize the hierarchy into a layered caching memory system.
However, Lee et al. teaches to organize the hierarchy into a layered caching memory system (In certain embodiments, the HVDIMM 200 is configured to provide a very large, configurable, expandable, dynamic random access system memory to a computer system. The HVDIMM 200 incorporates novel memory cache layer techniques, i.e., the Memory Window techniques, where the HV-DRAM 210 holds contiguous and complete sections of HV-Flash 220 for dynamic access by the computer system, see Lee et al., Para. 142).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jess et al. as modified, to have to organize the hierarchy into a layered caching memory system, as taught by Lee et al., to improve performance by distributing writes and erases across a larger population (Lee et al., Para. 65).
As to claim 14, Jess et al. as modified does not explicitly teach the organizing comprises organizing the first storage medium and the second storage medium into a layered caching memory system based, at least in part, on monitoring a first data access of the first storage medium and a second data access of the second storage medium.
However, Lee et al. teaches the organizing comprises organizing the first storage medium and the second storage medium into a layered caching memory system based, at least in part, on monitoring a first data access of the first storage medium and a second data access of the second storage medium (Traditionally, a computing device has had several generalized levels within the memory hierarchy. The first and fastest level is the processor's registers and instruction/data cache close to execution units (traditionally comprised of static random access memory (SRAM)). The second and next fastest level may be a unified instruction and data cache with a size much larger than the previous level of cache. This level is usually shared among one or more CPU and other execution or processing units such as Graphics Processing Unit (GPU), Digital Signal Processing (DSP), etc. Outside integrated circuits, some or all of the main or system memory which is traditionally comprised of dynamic RAM (DRAM), may be used as cache. The next level of the memory hierarchy is often very slow compared to the prior levels. It generally comprises magnetic or solid-state memory (e.g., a hard drive or NANO flash Technology, etc.) and is known as "secondary storage". The next level is the slowest, and traditionally comprises large bulk medium (e.g., optical discs, tape back-ups, etc., see Lee et al., Para. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jess et al. as modified, to have the organizing comprises organizing the first storage medium and the second storage medium into a layered caching memory system based, at least in part, on monitoring a first data access of the first storage medium and a second data access of the second storage medium, as taught by Lee et al., to improve performance by distributing writes and erases across a larger population (Lee et al., Para. 65).
As to claim 20, Jess et al. as modified teaches organize the memory system into a layered caching memory system (see Lee et al., Para. 4), store an inventory of the layered caching memory system (see Lee et al., Para. 4), and provide information regarding the layered caching memory system to the logic circuitry (see Lee et al., Para. 4), wherein the logic circuitry is configured to use the first storage medium interface based, at least in part, on the information regarding the layered caching memory system (see Lee et al., Para. 4).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jess et al. (U.S. Pat. No. 9,170,756) in view of Kamalavannan (U.S. Pat. No. 9,268,493) as applied to claims 1, 5, 8 , 10, 11, 13, 16, 17 and 19 above, and in further view of Tremaine (U.S. Pat. Pub. 2007/0288707).
As to claim 18, Jess et al. as modified does not explicitly teach the at least one accelerator processor comprises an encryption circuit configured to encrypt at least a data portion of the first data.
However, Tremaine teaches the at least one accelerator processor comprises an encryption circuit configured to encrypt at least a data portion of the first data (Additional functions that may reside local to the memory subsystem include write and/or read buffers, one or more levels of memory cache, local pre-fetch logic, data encryption/decryption, compression/decompression, protocol translation, command prioritization logic, voltage and/or level translation, error detection and/or correction circuitry, data scrubbing, local power management circuitry and/or reporting, operational and/or status registers, initialization circuitry, performance monitoring and/or control, one or more co-processors, search engine(s) and other functions that may have previously resided in other memory subsystems. By placing a function local to the memory subsystem, added performance may be obtained as related to the specific function, often while making use of unused circuits within the subsystem, see Tremaine, Para. 74).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Jess et al. as modified, to have the at least one accelerator processor comprises an encryption circuit configured to encrypt at least a data portion of the first data, as taught by Tremaine, improve overall memory subsystem performance (Tremaine, Para. 54).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAU SHYA MENG whose telephone number is (571)270-1634. The examiner can normally be reached 9AM-5PM EST M-F.
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/JAU SHYA MENG/ Primary Examiner, Art Unit 2168
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