Prosecution Insights
Last updated: April 19, 2026
Application No. 17/350,747

RECURRENT NEURAL NETWORK CELL ACTIVATION TO PERFORM A PLURALITY OF OPERATIONS IN A SINGLE INVOCATION

Non-Final OA §103§112
Filed
Jun 17, 2021
Examiner
PELLETT, DANIEL T
Art Unit
2121
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
3y 8m
To Grant
91%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
350 granted / 451 resolved
+22.6% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
7 currently pending
Career history
458
Total Applications
across all art units

Statute-Specific Performance

§101
23.7%
-16.3% vs TC avg
§103
33.5%
-6.5% vs TC avg
§102
16.6%
-23.4% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 451 resolved cases

Office Action

§103 §112
DETAILED ACTION This office action is in response to amendments and RCE filed July 29, 2025 and the arguments filed June 30, 2025. Claims 1-6, 9-13, 15-18, and 20-29 are pending. Claims 1, 11, 16, 21, and 26 have been amended. Claims 7, 8, 14, and 19 have been previously cancelled. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 29, 2025 has been entered. Information Disclosure Statement The information disclosure statements filed on July 7, 2025, August 8, 2025, September 5, 2025, October 17, 2025, and March 3, 2026 have been considered. Claim Rejections - 35 USC § 112 The previous rejection of claims 1-6, 9-13, 15-18, and 20-29 under 35 U.S.C. 112(b) are withdrawn in view of Applicant’s amendments and arguments. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-6, 9-13, 15-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fowers et al., “A configurable cloud-scale DNN processor for real-time AI”, in view of Staudemeyer et al., “Understanding LSTM – a tutorial into Long Short-Term Memory Recurrent Neural Networks” (Staudemeyer), in further view of Cammarota et al., U.S. Patent Application Publication 2019/0325289 (Cammarota). Regarding Claim 1, Fowers teaches A computer program product (“the architecture and microarchitecture of the BW NPU”, Page 1 Introduction (I) paragraph 5) for facilitating processing within a computing environment, the computer program product comprising: one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media (“This paper details the architecture and microarchitecture of the BW NPU, which is at the heart of the BW system. In its current form, the BW NPU is a DNN-optimized “soft processor” synthesized onto FPGAs”, Page 1 Introduction (I) paragraph 5) to perform a method comprising: executing an instruction that implements a recurrent neural network cell activation, (“The BW NPU architecture also exposes specialized instructions, datatypes, and memory abstractions that are optimized for low-latency DNN serving” Page 4 Architecture (IV.A) paragraph 2), Fowers does not explicitly disclose: the recurrent neural network cell activation being a long short-term memory cell activation, and the instruction including an operation code identifying the instruction and specifying a function code identifying a function to be performed based on executing the instruction, the function being the long short-term memory cell activation, the executing the instruction comprising: performing, based on executing the instruction, a plurality of activations and operations of the recurrent neural network cell activation, the performing the plurality of activations and operations providing a result of performing the recurrent neural network cell activation, the plurality of activations and operations performed in a single invocation of the instruction. However, Staudemeyer teaches: performing, based on executing the instruction, a plurality of activations and operations of the recurrent neural network cell activation (The second paragraph of section 9 teaches that, during the forward pass, the output/activation of all units (i.e. a plurality) are calculated.), the performing the plurality of activations and operations providing a result of performing the recurrent neural network cell activation (The second paragraph of section 9 teaches that, during the forward pass, the output/activation of all units (i.e. a plurality) are calculated. Additionally, section 9.1 of Staudemeyer details the forward pass that includes performing activations on a plurality of memory cells which generate outputs.), the plurality of activations and operations performed in a single invocation of the instruction Fowers and Staudemeyer are analogous art directed towards agent neural networks. Fowers teaches implementation of DNN on cloud servers (noting in the abstract that such methods could be applied to RNNs) and Staudemeyer teaches LSTM RNNs. It would have been obvious for one of ordinary skill in reinforcement learning to implement Staudemeyer’s disclosed LSTM details into Fowers’ disclosed system before the filing date of the claimed invention. It would have been obvious because one of ordinary skill would be motivated to implement powerful dynamic classifiers, as discussed in the abstract of Staudemeyer. Fowers and Staudemeyer do not explicitly disclose: the recurrent neural network cell activation being a long short-term memory cell activation, and the instruction including an operation code identifying the instruction and specifying a function code identifying a function to be performed based on executing the instruction, the function being the long short-term memory cell activation the plurality of activations and operations performed in a single invocation of the instruction However, Cammarota teaches this limitation: the recurrent neural network cell activation being a long short-term memory cell activation (Cammarota teaches RNNs may be configured as a long short-term memory in [0037] and RNN activation functions in [0039].), and the instruction including an operation code identifying the instruction and specifying a function code identifying a function to be performed based on executing the instruction, the function being the long short-term memory cell activation (In [0039], Cammarota teaches that an activation function may be implanted via a lookup table. A lookup table would function similarly to the claimed “operation code” that identifies an instruction. Additionally, Figure 6C and paragraphs detailing the NNPA (such as [00143], indicate that the NNPA functions may be called using the function code when considering the table in figure 6C.) the plurality of activations and operations performed in a single invocation of the instruction (Cammarota teaches that an activation function may be implanted via a lookup table in [0039]. A call to a lookup table is considered a single invocation of an instruction. Cammarota teaches that the activation function may transform a combination of inputs, weights, and biases to produce an input for a node of a subsequent layer of the network in [0039]. The transformations are a plurality of operations.) Fowers, Staudemeyer, and Cammarota are analogous art directed towards agent neural networks. Fowers teaches implementation of DNN on cloud servers (noting in the abstract that such methods could be applied to RNNs), Staudemeyer teaches LSTM RNNs, and Cammarota teaches optimization methods for neural networks that includes computing different nonlinear functions at the same time. It would have been obvious for one of ordinary skill in reinforcement learning to implement Cammarota’s disclosed activation function details into Fowers’ disclosed system before the filing date of the claimed invention. It would have been obvious because one of ordinary skill would be motivated to optimize processing and reduce memory bandwidth, as discussed in [0028]. Regarding Claim 2, Fowers teaches The computer program product of claim 1, wherein the plurality of activations and operations includes one or more sigmoid functions (“Table II gives a sampling of frequently used BW NPU instructions, discussed in greater detail below”, Page 5 Architecture (IV.C) paragraph 1; “v_sigm PWV sigmoid”) and one or more tangent functions. (“Table II gives a sampling of frequently used BW NPU instructions, discussed in greater detail below”, Page 5 Architecture (IV.C) paragraph 1; Page 5; “v_tanh PWV hyperbolic tangent” Table II, Page 5) Regarding Claim 3, Fowers teaches The computer program product of claim 1, wherein the plurality of activations and operations incudes tensor element-wise add (“Table II gives a sampling of frequently used BW NPU instructions, discussed in greater detail below” Page 5 Architecture (IV.C) paragraph 1; “vv_add PWV addition”, Table II, Page 5) and tensor element-wise multiplication operations. (“Table II gives a sampling of frequently used BW NPU instructions, discussed in greater detail below” Page 5 Architecture (IV.C) paragraph 1; “mv_mul Matrix-vector multiply”, Table II, Page 5) Regarding Claim 4, it comprises limitations similar to those of claims 2 and 3, and is therefore rejected for similar rationale. Regarding Claim 5, Fowers teaches The computer program product of claim 1, wherein one or more inputs to the instruction include one or more concatenated tensors. (“Figure 3 gives a high-level view of the BW NPU microarchitecture. The primary goal is to map and execute instruction chains (described in Section IV) to a continuous, uninterrupted stream of vector elements flowing through the function units”, Page 6 Microarchitecture full paragraph 2) Regarding Claim 6, Fowers teaches The computer program product of claim 1, wherein the result is an output tensor, the output tensor being an input to another invocation of the instruction. (“A fundamental feature of the BW NPU ISA is explicit instruction chaining, in which sequences of dependent instructions pass values directly from one operation to the next”, Page 5 Architecture (IV.C subsection “Instruction Chaining”) Full paragraph 1) Claims 7 and 8 have been cancelled by Applicant. Regarding Claim 9, Fowers teaches The computer program product of claim 1, wherein the performing the plurality of activations and operations of the recurrent neural network cell activation is performed by an accelerator (“The vector arbitration network manages data movement”, Page 6 Microarchitecture (V) paragraph 2) and produces intermediate computation data, and wherein the method further comprises storing the intermediate computation data in the accelerator. (“The vector arbitration network manages data movement among the memory components: pipeline register files (MRF and VRFs), DRAM, and network I/O queues.”, Page 6 Microarchitecture (V) paragraph 2) Regarding Claim 10, Fowers teaches The computer program product of claim 1, wherein the performing the plurality of activations and operations includes performing the plurality of activations and operations on spatially close input data. (“Other instructions in the chain are also scaled appropriately, e.g., the v_rd operation that feeds the mv_mul will read 5 contiguous VRF entries to provide sufficient input, and any v_wr at the end of the chain will write 4 contiguous VRF entries”, Page 5 Architecture (IV.C subsection “Mega-SMID execution”) Regarding Claim 11, it comprises limitations similar to those of claim 1 and is therefore rejected for similar rationale. Regarding Claim 12, it comprises limitations similar to those of claims 2 and 3 and is therefore rejected for similar rationale. Regarding Claim 13, it comprises limitations similar to those of claim 5 and is therefore rejected for similar rationale. Claim 14 has been cancelled by Applicant. Regarding Claim 15, it comprises limitations similar to those of claim 9 and is therefore rejected for similar rationale. Regarding Claim 16, it comprises limitations similar to those of claim 1 and is therefore rejected for similar rationale. Regarding Claim 17, it comprises limitations similar to those of claims 2 and 3 and is therefore rejected for similar rationale. Regarding Claim 18, it comprises limitations similar to those of claim 5 and is therefore rejected for similar rationale. Claim 19 has been cancelled by Applicant. Regarding Claim 20, it comprises limitations similar to those of claim 9 and is therefore rejected for similar rationale. Claim(s) 21-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fowers et al., “A configurable cloud-scale DNN processor for real-time AI” (Fowers), in view of Bahdanau et al., “Neural Machine Translation by Jointly Learning to Align and Translate” (Bahdanau), in further view of Cammarota et al., U.S. Patent Application Publication 2019/0325289 (Cammarota).. Regarding Claim 21, Fowers teaches A computer program product (“the architecture and microarchitecture of the BW NPU”, Page 1 Introduction (I) paragraph 5) for facilitating processing within a computing environment, the computer program product comprising: one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media (“This paper details the architecture and microarchitecture of the BW NPU, which is at the heart of the BW system. In its current form, the BW NPU is a DNN-optimized “soft processor” synthesized onto FPGAs”, Page 1 Introduction (I) paragraph 5) to perform a method comprising: executing an instruction that implements a recurrent neural network cell activation, (“The BW NPU architecture also exposes specialized instructions, datatypes, and memory abstractions that are optimized for low-latency DNN serving” Page 4 Architecture (IV.A) paragraph 2), Fowers does not explicitly disclose: the recurrent neural network cell activation being a gated recurrent unit cell activation, and the instruction including an operation code identifying the instruction and specifying a function code of a function to be performed based on executing the instruction, the function being the gated recurrent unit cell activation, the executing comprising: performing a plurality of activations and operations of the recurrent neural network cell activation, the performing the plurality of activations and operations providing a result of performing the recurrent neural network cell activation, the plurality of activations and operations performed in a single invocation of the instruction. However, Bahdanau teaches these limitations: Performing, based on executing the instruction, a plurality of activations and operations of the recurrent neural network cell activation (Bahdanau teaches activation functions, f, used by gated hidden units and performing activations at each step; see sections 3 and 3.3.1.), the performing the plurality of activations and operations providing a result of performing the recurrent neural network cell activation, Fowers and Bahdanau are analogous art directed towards neural networks. Fowers teaches implementation of DNN on cloud servers (noting in the abstract that such methods could be applied to RNNs) and Bahdanau teaches performing translation using RNNs and introduces gated hidden units. It would have been obvious for one of ordinary skill in reinforcement learning to implement Bahdanau’s disclosed gated unit details into Fowers’ disclosed system before the filing date of the claimed invention. It would have been obvious because one of ordinary skill would be motivated to improve the performance and reduce bottlenecks, as disclosed in the abstract of Bahdanau. Fowers and Bahdanau do not explicitly disclose: the recurrent neural network cell activation being a long short-term memory cell activation, and the instruction including an operation code identifying the instruction and specifying a function code identifying a function to be performed based on executing the instruction, the function being the long short-term memory cell activation the plurality of activations and operations performed in a single invocation of the instruction However, Cammarota teaches this limitation: the recurrent neural network cell activation being a long short-term memory cell activation (Cammarota teaches RNNs may be configured as a long short-term memory in [0037] and RNN activation functions in [0039].), and the instruction including an operation code identifying the instruction and specifying a function code identifying a function to be performed based on executing the instruction, the function being the long short-term memory cell activation (In [0039], Cammarota teaches that an activation function may be implanted via a lookup table. A lookup table would function similarly to the claimed “operation code” that identifies an instruction. Additionally, Figure 6C and paragraphs detailing the NNPA (such as [00143], indicate that the NNPA functions may be called using the function code when considering the table in figure 6C.) the plurality of activations and operations performed in a single invocation of the instruction (Cammarota teaches that an activation function may be implanted via a lookup table in [0039]. A call to a lookup table is considered a single invocation of an instruction. Cammarota teaches that the activation function may transform a combination of inputs, weights, and biases to produce an input for a node of a subsequent layer of the network in [0039]. The transformations are a plurality of operations.) Fowers, Bahdanau, and Cammarota are analogous art directed towards agent neural networks. Fowers teaches implementation of DNN on cloud servers (noting in the abstract that such methods could be applied to RNNs), Bahdanau teaches performing translation using RNNs and introduces gated hidden units, and Cammarota teaches optimization methods for neural networks that includes computing different nonlinear functions at the same time. It would have been obvious for one of ordinary skill in reinforcement learning to implement Cammarota’s disclosed activation function details into Fowers’ disclosed system before the filing date of the claimed invention. It would have been obvious because one of ordinary skill would be motivated to optimize processing and reduce memory bandwidth, as discussed in [0028]. Regarding Claim 22, Fowers teaches The computer program product of claim 21, wherein the plurality of activations and operations includes one or more sigmoid functions (“Table II gives a sampling of frequently used BW NPU instructions, discussed in greater detail below”, Page 5 Architecture (IV.C) paragraph 1; “v_sigm PWV sigmoid”) and one or more tangent functions. (“Table II gives a sampling of frequently used BW NPU instructions, discussed in greater detail below”, Page 5 Architecture (IV.C) paragraph 1; Page 5; “v_tanh PWV hyperbolic tangent” Table II, Page 5) Regarding Claim 23, Fowers teaches The computer program product of claim 21, wherein the plurality of activations and operations incudes tensor element-wise add (“Table II gives a sampling of frequently used BW NPU instructions, discussed in greater detail below” Page 5 Architecture (IV.C) paragraph 1; “vv_add PWV addition”, Table II, Page 5) and tensor element-wise multiplication operations. (“Table II gives a sampling of frequently used BW NPU instructions, discussed in greater detail below” Page 5 Architecture (IV.C) paragraph 1; “mv_mul Matrix-vector multiply”, Table II, Page 5) Regarding Claim 24, it comprises limitations similar to those of claims 22 and 23, and is therefore rejected for similar rationale. Regarding Claim 25, Fowers teaches The computer program product of claim 21, wherein the performing the plurality of activations and operations of the recurrent neural network cell activation is performed by an accelerator (“The vector arbitration network manages data movement”, Page 6 Microarchitecture (V) paragraph 2) and produces intermediate computation data, and wherein the method further comprises storing the intermediate computation data in the accelerator. (“The vector arbitration network manages data movement among the memory components: pipeline register files (MRF and VRFs), DRAM, and network I/O queues.”, Page 6 Microarchitecture (V) paragraph 2) Regarding Claim 26, it comprises limitations similar to those of claim 21 and is therefore rejected for similar rationale. Regarding Claim 27, it comprises limitations similar to those of claim 22 and is therefore rejected for similar rationale. Regarding Claim 28, it comprises limitations similar to those of claim 23 and is therefore rejected for similar rationale. Regarding Claim 29, it comprises limitations similar to those of claim 24 and is therefore rejected for similar rationale. Response to Arguments Applicant's arguments filed June 30, 2025 have been fully considered but they are not persuasive. On pages 8-10, Applicant argues that the amended claims overcome the previous rejection under 35 U.S.C. 112(b). Examiner agrees and the previous rejection is withdrawn. Beginning on page 10 of remarks, Applicant argues that the prior art does not teach the newly amended limitation “executing an instruction that implements a recurrent neural network cell activation, the recurrent neural network cell activation being a long short-term memory cell activation, and the instruction including an operation code identifying the instruction and specifying a function code identifying a function to be performed based on executing the instruction, the function being the long short-term memory cell activation.” The rejection above has been modified, necessitated by Applicant’s amendments, to incorporate Cammarota. Cammarota teaches the newly amended limitations and Applicant’s arguments are not persuasive. Additionally, Cammarota is relied upon to teach “the plurality of activations and operations performed in a single invocation of the instruction,” argued on page 12 of remarks. Applicant’s arguments are not persuasive. Conclusion Claims 1-6, 9-13, 15-18, and 20-29 are rejected. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL T PELLETT whose telephone number is (571)270-7156. The examiner can normally be reached Monday - Friday 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interaviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Li Zhen can be reached on 571-272-3768. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL T PELLETT/Primary Examiner, Art Unit 2121
Read full office action

Prosecution Timeline

Jun 17, 2021
Application Filed
Sep 16, 2024
Non-Final Rejection — §103, §112
Nov 21, 2024
Applicant Interview (Telephonic)
Nov 25, 2024
Examiner Interview Summary
Dec 20, 2024
Response Filed
Apr 25, 2025
Final Rejection — §103, §112
Jun 23, 2025
Examiner Interview Summary
Jun 23, 2025
Applicant Interview (Telephonic)
Jun 30, 2025
Response after Non-Final Action
Jul 29, 2025
Request for Continued Examination
Aug 02, 2025
Response after Non-Final Action
Mar 10, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
91%
With Interview (+13.8%)
3y 8m
Median Time to Grant
High
PTA Risk
Based on 451 resolved cases by this examiner. Grant probability derived from career allow rate.

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