Prosecution Insights
Last updated: May 29, 2026
Application No. 17/354,446

OPTICAL COMMUNICATION BETWEEN INTEGRATED CIRCUIT DEVICE ASSEMBLIES

Non-Final OA §103
Filed
Jun 22, 2021
Examiner
HOLLWEG, THOMAS A
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Non-Final)
53%
Grant Probability
Moderate
2-3
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 53% of resolved cases
53%
Career Allowance Rate
246 granted / 462 resolved
-14.8% vs TC avg
Strong +31% interview lift
Without
With
+31.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
9 currently pending
Career history
478
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
86.2%
+46.2% vs TC avg
§102
8.6%
-31.4% vs TC avg
§112
3.4%
-36.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 462 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 21 are rejected under 35 U.S.C. 103 as being unpatentable over Dietrich US Pat. No. 11,169,446 in view of Chilton US Pat. No. 6,623,177 B1. With regard to claim 21, in figs. 18-19 Dietrich discloses an integrated circuit (IC) package, comprising: a package substrate (101); a first IC assembly, comprising: a first IC device(modulator array 106), attached to the packaged substrate, wherein the first IC device includes one or more first optical waveguides intersecting an edge of the first IC device; a second IC assembly adjacent to the first IC assembly and comprising; a third IC device (107) attached to the packaged substrate, wherein the third IC device includes one or more third optical waveguides intersecting an edge of the third IC device; an array structure between the edges of the first IC device and the edges of the third IC device (the claimed array structure comprises beam shaping elements 105 and the optical interface therebetween), wherein: the array structure comprises: a first transmission conduit optically coupling the first optical waveguides with the third optical waveguides (See col. 36, line 62 to col. 37, line 35 5-10 of Dietrich for further details). Dietrich does not expressly teach a second IC device as part of the first IC assembly and a fourth IC device as part of the second IC assembly. Chilton, fig. 1, teaches an optical interface array structure (22) have a plurality of optical IC devices on one side (24-1… 24-N) and a plurality of optical IC devices on another side (elements 24 on far side of fig. 1) where the optical interface array structure optically connects the first plurality of optical IC devices to the second set of optical IC devices to provide a compact and reliable interface for stacks of IC devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the optical IC device connection (first to third) of Dietrich using multiple optical IC device connections (second to fourth, etc.), as taught by Chilton, to create array of optical IC device connections to construct opto-electric computing devices with more components and capabilities. With regard to claim 22, Dietrich discloses that the array structure further comprises a cladding material surrounding the first and second transmission conduits (see fig. 21 showing structure around array structure) (examiner notes that disclosed and claimed “cladding” is not an optical cladding such as used to surround the core of an optical fiber, but rather elements near the disclosed lenses to provide structure to the array). With regard to claim 23, Dietrich device as modified by Chilton discloses that the first transmission conduit comprises: a first optical lens (105) aligned with a corresponding one of the first optical waveguides; a second optical lens (105) aligned with a corresponding one of the third optical waveguides; and an optically transmissive material between, and coupling, the first optical lens to the second optical lens; and the second transmission conduit comprises: a third optical lenses (105) aligned with a corresponding one of the second optical waveguides; a fourth optical lens (105) aligned with a corresponding one of the fourth optical waveguides; and an optically transmissive material between, and coupling, the third optical lens to the fourth optical lens (105). With regard to claim 24, Dietrich device as modified by Chilton discloses the one or more first optical waveguides comprise a plurality of first optical waveguides; the one or more second optical waveguides comprise a plurality of second optical waveguides; the one or more third optical waveguides comprise a plurality of third optical waveguides; and the one or more fourth optical waveguides comprises a plurality of fourth optical waveguides. With regard to claim 25, Dietrich device as modified by Chilton discloses the plurality of first optical waveguides has the same number of optical waveguides as the plurality of third optical waveguides; the plurality of second optical waveguides has the same number of optical waveguides as the plurality of fourth optical waveguides; and the array structure couples individual ones of the first optical waveguides with corresponding ones of the third optical waveguides, and couples individual ones of the second optical waveguides with corresponding ones of the fourth optical waveguides. With regard to claim 26, Dietrich device as modified by Chilton discloses the plurality of first optical waveguides has the same number of optical waveguides as the plurality of second optical waveguides; and the plurality of third optical waveguides has the same number of optical waveguides as the plurality of fourth optical waveguides. With regard to claim 27, Dietrich device as modified by Chilton discloses the first IC device electrically attached to the packaged substrate; the second IC device is electrically attached to the first IC device; the third IC device is electrically attached to the package substrate; and the fourth IC device is electrically attached to the third IC device. With regard to claim 28, Dietrich device as modified by Chilton discloses the array structure is a single array structure attached to both the edge of the first IC device and the edge of the second IC device. With regard to claim 29, Dietrich device as modified by Chilton discloses that each of the first, second, third and fourth IC devices comprises a microprocessor, a graphics device or a memory device (see IC devices 24 of Chilton). With regard to claim 30, Dietrich device as modified by Chilton discloses a system, comprising: an electronic board; and the IC package of claim 21 attached to the electronic board. With regard to claim 31, Dietrich as modified by Chilton discloses the IC package is electrically attached to the electronic board. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas A Hollweg whose telephone number is (571)270-1739. The examiner can normally be reached on M-F 8-4. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew W Such can be reached on (571)272-1570. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
Read full office action

Prosecution Timeline

Jun 22, 2021
Application Filed
Oct 21, 2021
Response after Non-Final Action
Oct 30, 2024
Non-Final Rejection mailed — §103
Feb 28, 2025
Response Filed
Sep 29, 2025
Final Rejection mailed — §103
Dec 22, 2025
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12631838
ROTATING CIRCULAR WAVEGUIDE CHANNEL FOR FOLDABLE ELECTRONIC DEVICES
2y 10m to grant Granted May 19, 2026
Patent 12546965
FIBER OPTIC ENCLOSURES AND CORRESPONDING SYSTEMS WITH OPTIONAL SPLITTER RATIO OUTPUTS
2y 8m to grant Granted Feb 10, 2026
Patent 12540690
CABLE ANCHORING SYSTEM
2y 7m to grant Granted Feb 03, 2026
Patent 12529845
Optical Waveguide Device and Method for Manufacturing the Same
2y 12m to grant Granted Jan 20, 2026
Patent 12449613
OPTICAL PART AND SEMICONDUCTOR LASER MODULE
4y 2m to grant Granted Oct 21, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
53%
Grant Probability
84%
With Interview (+31.1%)
3y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 462 resolved cases by this examiner. Grant probability derived from career allowance rate.

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