DETAILED ACTION
Response to Arguments
Applicant's arguments ("REMARKS") filed 26 February 2025 have been fully considered, and they are partially persuasive as to the previous grounds of rejection.
Claims 1, 7, and 14 were amended. Claims 1, 8, and 14 are independent. Claims 1-20 are currently pending.
Re: Claim Rejections Under 35 U.S.C. §103
Applicant’s amendment and arguments, indicated on pp.6-11 of the REMARKS, in response to the rejection of the claims under 35 U.S.C. §103 with respect to Jayavant et al., US 2013/0027413 A1 (hereafter, “Jayavant ‘413”), Branco, US 2017/0168902 A1 (hereinafter, “Branco ‘902”), Gulati et al., US 20190171538 A1 (hereinafter “Gulati ‘538”), and Chheda et al., US 2020/0104138 A1 (hereinafter, “Chheda ‘138”) have been fully considered and they are partially persuasive as to the previous grounds of rejection.
With respect to independent claims 1 and 14, the amendments to the claims do not appear to significantly alter the scope of the claims. Furthermore, with respect to the independent claims, Applicant essentially argues that the Examiner has improperly deconstructed the language of the independent claims by analyzing the limitation “restoring, by the trusted processor, the context and data from the memory to the parallel processor in response to the parallel processor powering up, wherein the restoring … is independent of a central processing unit (CPU) … and independent of invoking a driver of the processing system” in a piecemeal fashion across multiple references. Applicant further asserts that by not requiring Chheda ‘138 to disclose the entire limitation—including restoration from “external memory” and by a “trusted processor”—Examiner has disregarded the scope and structure of the claim. Applicant additionally argues that ‘[o]ne of ordinary skill in the art understands that providing a graphics processor core with the ability to save and restore registers within the graphics processor core independent of graphics driver software on the system as taught by Chheda does not teach the restoration of context and data from an external memory to a parallel processor’.
These arguments are not persuasive for the reasons outlined below.
It is proper to analyze multi-part limitations using a combination of references under 35 U.S.C. § 103. Applicant’s core objection is that the Examiner’s analysis improperly deconstructs a single limitation into multiple references. The Federal Circuit, however, has consistently held that individual features or sub-limitations of a claim may be taught by different references, and that a rejection may combine such teachings if the combination would have been obvious to a person of ordinary skill in the art. See In re Keller, 642 F.2d 413, 425 (CCPA 1981): “The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference… but what the combined teachings of the references would have suggested to those of ordinary skill in the art.”
In this case, the limitations within the independent claims are functionally and logically composed of several subcomponents:
What performs the restoring (“trusted processor”),
What is restored (“context and data”),
From where (“external memory”),
When (“powering up”), and
How (“independent of a central processing unit … and … invoking a driver”).
These components are independently addressed by the cited references:
Jayavant ‘413 teaches restoring context and data from external memory in response to a GPU powering back on.
Branco ‘902 teaches that context restoration is performed by a trusted processor operating in secure mode.
Gulati ‘538 teaches that the restoration occurs independently of the CPU.
Chheda ‘138 teaches that such restoration is performed independently of invoking a driver of the processing system.
A person of ordinary skill in the art would understand that these teachings, though not appearing in a single reference, collectively describe a coherent and workable system for restoring context and data under the conditions recited in the claim. Applicant appears to treat the restoring step as an indivisible block that must be disclosed entirely by a single reference. If all claims were to be analyzed under this standard, then all claims would have to be rejected under 35 U.S.C. § 102 using a single reference. See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986): “Non-obviousness cannot be established by attacking references individually where the rejection is based on a combination of references.” The “restoring” limitation is a compound operation that contains distinct sub-elements and qualifiers. The references used by the Examiner each provide an essential part of the overall concept, as stated above, and the combination would have been within the ordinary creativity and understanding of a person of ordinary skill in the art.
Applicant’s argument that Chheda ‘138 must itself disclose the entire process of ‘restoration from external memory and execution by a trusted processor’ is improper. The Examiner does not rely on Chheda ‘138 to teach those aspects. Rather, those limitations are already taught by Jayavant ‘413 and Branco ‘902, respectively. Chheda ‘138 is cited to disclose the missing teaching that the restoration occurs independently of invoking a driver. There is no requirement for each reference in a combination to recite the full scope of a limitation or duplicate what has already been disclosed elsewhere in the rejection.
Next, Applicant argues that Chheda ‘138 only discloses ‘… providing the graphics processor core 500 with the ability to save and restore registers within the graphics processor core 500 across low-power state transitions independently from the operating system and/or graphics driver software on the system …’ (Chheda ‘138, ¶92) (emphasis added), which implies that the data is not stored externally and thus cannot be reconciled with Jayavant ‘413. This argument conflates the location of the registers being restored with the location of the stored context data. The phrase ‘within the graphics processor core’ refers to the destination of the restored data (i.e., the registers), not the source from which the data is retrieved. Nothing in Chheda ‘138 prohibits the context data from being saved to and restored from an external memory. In fact, this is consistent with standard architectural practices in graphics systems, where register state is commonly saved to RAM or a dedicated storage outside the core itself. Therefore, the teachings of Chheda ‘138 are not mutually exclusive with those of Jayavant ‘413. A person of ordinary skill in the art would understand how the restoration of registers ‘within’ a graphics processor can be performed using data retrieved from an external source.
The Examiner maintains that Jayavant ‘413, Branco ‘902, Gulati ‘538, and Chheda ‘138 collectively disclose the independent claims. Each reference contributes a distinct portion of the limitation in a manner that would have been obvious to combine for a person of ordinary skill in the art. Applicant’s argument that each reference individually discloses the entire limitation is contrary to a proper § 103 analysis. Accordingly, the rejection of the independent claims under 35 U.S.C. § 103 is maintained. See Claim Rejections – 35 USC §103 below for further details.
With respect to dependent claim 7, as amended, claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. See Allowable Subject Matter below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 8, 13-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant et al., US 2013/0027413 A1 (hereafter, “Jayavant ‘413”), in view of Branco, US 2017/0168902 A1 (hereinafter, “Branco ‘902”), and further in view of Gulati et al., US 20190171538 A1 (hereinafter “Gulati ‘538”), and further in view of Chheda et al., US 2020/0104138 A1 (hereinafter, “Chheda ‘138”).
As per claim 1: Jayavant ‘413 discloses:
A method comprising:
accessing, (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC) [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2]) in response to the parallel processor powering down (accessing and storing operating state information and data in response to the GPU 240 entering a sleep mode and powering down [Jayavant ‘413, ¶¶6, 30, 35-36, 39; Fig. 2, Fig. 4A]);
storing the context and data at a memory external to the parallel processor (storing the operating state information and data at a memory 244, 256, where the memory 244, 256 is coupled to the GPU 240 and external to the GPU 240 [Jayavant ‘413, ¶¶36, 39, 43-44; Fig.2, Fig. 4A]); and
restoring, data from the memory to the parallel processor (restoring the operating state information and data to the GPU 240, from the external memory 244, 256, in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig.2, Fig. 4B])
Jayavant ‘413, as stated above, does not explicitly disclose: “accessing, by a trusted processor, context and data of a … restoring, by the trusted processor, the context and data … restoring of the context and data … by the trusted processor is independent of a central processing unit (CPU) of the processing system and independent of invoking a driver of the processing system.”
Branco ‘902, however, discloses:
accessing, by a trusted processor, context and data of a … (determining and accessing, by the processing circuitry 104 that may operate in secure mode, processor state data for a processor, where the processor data is verified to ensure its integrity [Branco ‘902, ¶¶11-12, 16, 19, 27; Fig. 1, Fig. 3])
… restoring, by the trusted processor, the context and data … restoring of the context and data … by the trusted processor (restoring, by the processing circuitry 104, processor states and data to the processor in response to returning to normal operation [Branco ‘902, ¶¶10, 12, 43; Fig. 3]) .
Jayavant ‘413 and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 and Branco ‘902 before them, to modify the method in Jayavant ‘413 to include the teachings of Branco ‘902, namely to implement the EC 150 of Jayavant ‘413 as a trusted and secure processing circuitry, as disclosed in Branco ‘902, such that the EC 150 may securely facilitate the accessing, storing, and restoring of state information and data of the graphics processing unit 240. The motivation for doing so would be to improve the protection of processor state data by ensuring that only privileged processing circuitry may operate on and access processor state data (see Branco ‘902, ¶¶2-3, 9).
As stated above, Jayavant ‘413 in view of Branco ‘902 does not explicitly disclose: “… restoring … is independent of a central processing unit (CPU) of the processing system and independent of invoking a driver of the processing system.”
Gulati ‘538, however, discloses:
… restoring … is independent of a central processing unit (CPU) of the processing system (the context save and restore circuit 58 performing a context save and restore for a GPU, independent of the CPU, where the restoration is performed in response to exiting an idle self-test state [Gulati ‘538, ¶¶59, 98-99, 133]) .
Jayavant ‘413 (modified by Branco ‘902) and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902) and Gulati ‘538 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902) to include the teachings of Gulati ‘538, namely to implement the restoring process of the GPU state information, as disclosed in Jayavant ‘413, to be independent of the CPU, where the restoring process is in response to the GPU exiting sleep mode. A motivation for doing so would be to reduce the complexity and increase efficiency of a context save/restore process for a GPU, by bypassing the CPU (see Gulati ‘538, ¶¶20, 97).
As stated above, Jayavant ‘413 in view of Branco ‘902, and further in view of Gulati ‘538 does not explicitly disclose: “… restoring … and independent of invoking a driver of the processing system.”
Chheda ‘138, however, discloses:
… restoring … and independent of invoking a driver of the processing system (a method for graphics engine reset and recovery, where a graphics microcontroller may provide a graphics processor with the ability to save and restore registers within the graphics processor across low-power state transitions independently from the graphics driver software on the system [Chheda ‘138, ¶92]).
Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) and Chheda ‘138 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) and Chheda ‘138 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) to include the teachings of Chheda ‘138, namely to implement the restoring process of the GPU state information, as disclosed in Jayavant ‘413, to be independent of the CPU as disclosed in Gulati ‘538, where the restoring process is also independent of the graphics driver software on the system, as disclosed in Chheda ‘138. A motivation for doing so would be to streamline the saving/restoring processes within the graphics processor across state transitions (see Chheda ‘138, ¶92).
As per claim 8: Jayavant ‘413 discloses:
A method, comprising:
fetching(retrieving the operating state information and data, from memory 244, 256, to the GPU 240 of a computer system 100 in response to the GPU 240 exiting sleep mode and powering up, where the memory 244, 256 is coupled to the GPU 240 and external to the GPU 240 [Jayavant ‘413, ¶¶30, 36, 39, 41, 43-44; Fig.2, Fig. 4B]);
restoring, (restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B])
Jayavant ‘413, as stated above, does not explicitly disclose: “fetching, by a trusted processor … verifying, at the trusted processor, that the context and data are untampered; and restoring, by the trusted processor … independent of a central processing unit (CPU) of the processing system and independent of invoking a driver of the processing system.”
Branco ‘902, however, discloses:
fetching, by a trusted processor (determining and accessing, by the processing circuitry 104 that may operate in secure mode, processor state data for a processor, where the processor data is verified to ensure its integrity [Branco ‘902, ¶¶11-12, 16, 19, 27; Fig. 1, Fig. 3]) … verifying, at the trusted processor, that the context and data are untampered … (detecting by the secure processing circuitry whether the integrity of the processor state data has been compromised using hash verification, where the detection is performed prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-12, 20; Fig. 3]) ; and restoring, by the trusted processor (restoring, by the processing circuitry 104, processor states and data to the processor in response to returning to normal operation [Branco ‘902, ¶¶10, 12, 43; Fig. 3]) … .
Jayavant ‘413 and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claims 1 and 3, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 and Branco ‘902 before them, to modify the method in Jayavant ‘413 to include the teachings of Branco ‘902.
As stated above, Jayavant ‘413 in view of Branco ‘902 does not explicitly disclose: “… restoring … independent of a central processing unit (CPU) of the processing system and independent of invoking a driver of the processing system.”
Gulati ‘538, however, discloses:
… restoring … independent of a central processing unit (CPU) of the processing system (the context save and restore circuit 58 performing a context save and restore for a GPU, independent of the CPU, where the restoration is performed in response to exiting an idle self-test state [Gulati ‘538, ¶¶59, 98-99, 133]).
Jayavant ‘413 (modified by Branco ‘902) and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902) and Gulati ‘538 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902) to include the teachings of Gulati ‘538.
As stated above, Jayavant ‘413 in view of Branco ‘902, and further in view of Gulati ‘538 does not explicitly disclose: “… restoring … and independent of invoking a driver of the processing system.”
Chheda ‘138, however, discloses:
… restoring … and independent of invoking a driver of the processing system (a method for graphics engine reset and recovery, where a graphics microcontroller may provide a graphics processor core with the ability to save and restore registers within the graphics processor across low-power state transitions independently from the graphics driver software on the system [Chheda ‘138, ¶92]).
Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) and Chheda ‘138 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) and Chheda ‘138 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) to include the teachings of Chheda ‘138.
As per claim 13: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138 discloses all limitations of claim 8, as stated above, from which claim 13 is dependent upon. Furthermore, Jayavant ‘413 discloses:
further comprising: bypassing reinitialization of the parallel processor in response to the parallel processor powering up (under the broadest reasonable interpretation, ‘reinitialization’ is interpreted as a cold-boot where normal operation is resumed after a considerable time due to data processing; bypassing a cold boot sequence of the GPU by resuming normal operations after exiting sleep mode in an efficient warm boot sequence [Jayavant ‘413, ¶¶6, 30, 41-43]).
As per claim 14: Jayavant ‘413 discloses:
A processing system (computer system 100 device [Jayavant ‘413, ¶19; Fig. 1]), comprising: a central processing unit (CPU) (CPU 102 [Jayavant ‘413, ¶19; Fig. 1]); a parallel processor (GPU 240, ¶24; Fig. 2); a memory external to the parallel processor (memory system 242 and SPI flash 256, where memory 242, 256 is coupled to the GPU 240 and external to the GPU 240 [Jayavant ‘413, ¶¶24-25, 36, 39, 43-44; Fig. 2, Fig.4A]); and (system EC 150 configured to perform operations [Jayavant ‘413, ¶¶20, 24, 28-30; Fig. 2]):
access a context of the parallel processor and data stored at the parallel processor (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC) [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2]) in response to the parallel processor powering down (accessing and storing operating state information and data in response to the GPU 240 entering a sleep mode and powering down [Jayavant ‘413, ¶¶6, 30, 35-36, 39; Fig. 2, Fig. 4A]);
store the context and data at the memory (storing the operating state information and data at a memory [Jayavant ‘413, ¶¶36, 39, 43-44; Fig. 4A]); and
restore the context and data from the memory to the parallel processor in response to the parallel processor powering up, wherein the restoring of the context and data (restoring the operating state information and data to the GPU 240, from the external memory 242, 256, in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig.2, Fig. 4B])
Jayavant ‘413, as stated above, does not explicitly disclose: “… a trusted processor configured to: access … restore … is independent of the CPU and independent of invoking a driver of the processing system.”
Branco ‘902, however, discloses:
… a trusted processor configured to: access … restore (determining and accessing, by the processing circuitry 104 that may operate in secure mode, processor state data for a processor, where the processor data is verified to ensure its integrity; restoring, by the processing circuitry 104, processor states and data to the processor in response to returning to normal operation [Branco ‘902, ¶¶10-12, 16, 19, 27, 43; Fig. 1, Fig. 3]) …
Jayavant ‘413 and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 and Branco ‘902 before them, to modify the method in Jayavant ‘413 to include the teachings of Branco ‘902.
As stated above, Jayavant ‘413 in view of Branco ‘902 does not explicitly disclose: “… restore … is independent of the CPU and independent of invoking a driver of the processing system.”
Gulati ‘538, however, discloses:
… restore … is independent of the CPU (the context save and restore circuit 58 performing a context save and restore for a GPU, independent of the CPU, where the restoration is performed in response to exiting an idle self-test state [Gulati ‘538, ¶¶59, 98-99, 133]).
Jayavant ‘413 (modified by Branco ‘902) and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902) and Gulati ‘538 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902) to include the teachings of Gulati ‘538.
As stated above, Jayavant ‘413 in view of Branco ‘902, and further in view of Gulati ‘538 does not explicitly disclose: “… restore … and independent of invoking a driver of the processing system.”
Chheda ‘138, however, discloses:
… restore … and independent of invoking a driver of the processing system (a method for graphics engine reset and recovery, where a graphics microcontroller may provide a graphics processor core with the ability to save and restore registers within the graphics processor across low-power state transitions independently from the graphics driver software on the system [Chheda ‘138, ¶92]).
Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) and Chheda ‘138 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) and Chheda ‘138 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 and Gulati ‘538) to include the teachings of Chheda ‘138.
As per claim 15: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138 discloses all limitations of claim 14, as stated above, from which claim 15 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]).
As stated above, Jayavant ‘413 does not explicitly disclose: “wherein the trusted processor is to detect tampering of the context and data prior to restoring the context and data to the … processor.”
Branco ‘902, however, discloses:
wherein the trusted processor is to detect tampering of the context and data prior to restoring the context and data to the … processor (the secure processing circuitry 104 detecting that the integrity of the processor state data has been compromised using hash verification, where the detection is performed prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-12, 20; Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 3, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) to include the teachings of Branco ‘902.
As per claim 20: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138 discloses all limitations of claim 14, as stated above, from which claim 20 is dependent upon. Furthermore, Jayavant ‘413 discloses:
wherein the parallel processor is to bypass reinitializing in response to the parallel processor powering up (under the broadest reasonable interpretation, ‘reinitialization’ is interpreted as a cold-boot where normal operation is resumed after a considerable time due to data processing; bypassing a cold boot sequence of the GPU by resuming normal operations after exiting sleep mode in an efficient warm boot sequence [Jayavant ‘413, ¶¶6, 30, 41-43]).
Claims 2-4, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ’138, and further in view of Tsirkin, US 2018/0239909 A1 (hereinafter, “Tsirkin ‘909”).
As per claim 2: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138 discloses all limitations of claim 1, as stated above, from which claim 2 is dependent upon. Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138 does not explicitly disclose the limitations of claim 2. Tsirkin ‘909, however, discloses:
encrypting the context and data to generate an encrypted context and encrypted data prior to storing the encrypted context and encrypted data at the memory (encrypting the processor state and data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) to include the teachings of Tsirkin ‘909, namely to encrypt the operating state information and data, as disclosed in Tsirkin ‘909, prior to storing the operating state information and data at a memory, as disclosed in Jayavant ‘413. The motivation for doing so would be to increase the protection of processor states such that they cannot be accessed by unauthorized entities (see Tsirkin ‘909, ¶¶13-16).
As per claim 3: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138, and further in view of Tsirkin ‘909 discloses all limitations of claims 1-2, as stated above, from which claim 3 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]).
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “detecting tampering of the encrypted context and encrypted data prior to restoring the context and data to the … processor.”
Branco ‘902, however, discloses:
detecting tampering of the restoring the context and data to the … processor (detecting that the integrity of the processor state data has been compromised using hash verification, where the detection is performed prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-12, 20; Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138) to include the teachings of Branco ‘902, namely to determine the integrity of the operating state information and data using hash verification, as disclosed in Branco ‘902, prior to storing the operating state information and data at a memory, as disclosed in Jayavant ‘413. The motivation for doing so would be to improve the protection of processor state data by ensuring the integrity of processor state data and that only privileged processing circuitry may operate on and access processor state data (see Branco ‘902, ¶¶2-3, 9).
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902 does not explicitly disclose: “… encrypted context and encrypted data …”.
Tsirkin ‘909, however, discloses:
… encrypted context and encrypted data … (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) to include the teachings of Tsirkin ‘909.
As per claim 4: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138, and further in view of Tsirkin ‘909 discloses all limitations of claims 1-3, as stated above, from which claim 4 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]),
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “hashing the context and data to generate a first hash value prior to storing the encrypted context and encrypted data at the memory; and accessing the encrypted context and encrypted data and hashing the encrypted context and encrypted data to generate a second hash value prior to restoring the context and data to the … processor, and wherein detecting comprises comparing the first hash value to the second hash value.
Branco ‘902, however, discloses:
hashing the context and data to generate a first hash value prior to storing the (hashing the processor state data to generate a hash and storing the processor state data in memory [Branco ‘902, ¶¶9, 11, 33]); and
accessing the restoring the context and data to the … processor (accessing the processor state data to generate a second updated hash prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-10, 20, 33]),
wherein detecting comprises comparing the first hash value to the second hash value (detecting whether the integrity of the processor state data has been compromised by comparing the first hash with the second updated hash [Branco ‘902, ¶¶9, 20, 33]).
Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 3, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) to include the teachings of Branco ‘902.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902 does not explicitly disclose: “… storing the encrypted context and encrypted data at the memory … the encrypted context and encrypted data …”.
Tsirkin ‘909, however, discloses:
… storing the encrypted context and encrypted data at the memory … the encrypted context and encrypted data … (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Chheda ‘138) to include the teachings of Tsirkin ‘909.
As per claim 16: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138, discloses all limitations of claims 14-15, as stated above, from which claim 16 is dependent upon. Jayavant ‘413 in view of Gulati ‘538, and further in view of Chheda ‘138 does not explicitly disclose the limitations of claim 16. Tsirkin ‘909, however, discloses:
wherein the (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by and Gulati ‘538 and Chheda ‘138) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by and Gulati ‘538 and Chheda ‘138) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by and Gulati ‘538 and Chheda ‘138) to include the teachings of Tsirkin ‘909.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Tsirkin ‘909 does not explicitly disclose: “wherein the trusted processor is to: …”.
Branco ‘902, however, discloses:
wherein the trusted processor is to: … (determining and accessing, by the processing circuitry 104 that may operate in secure mode, processor state data for a processor, where the processor data is verified to ensure its integrity, and where the secure processing circuitry may perform cryptographic functions [Branco ‘902, ¶¶11-13, 16, 19-20, 27; Fig. 1, Fig. 3])
Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Tsirkin ‘909) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Tsirkin ‘909) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Tsirkin ‘909) to include the teachings of Branco ‘902.
As per claim 17: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138, and further in view of Tsirkin ‘909 discloses all limitations of claims 14-16, as stated above, from which claim 17 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]); and
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “wherein the trusted processor is to: hash the context and data to generate a first hash value prior to storing the encrypted context and encrypted data at the memory; access the encrypted context and data and hash the encrypted context and data to generate a second hash value prior to restoring the context and data to the … processor; and compare the first hash value to the second hash value.”
Branco ‘902, however, discloses:
wherein the trusted processor is to: hash the context and data to generate a first hash value prior to storing the (the secure processing circuitry hashing the processor state data to generate a hash and storing the processor state data in memory [Branco ‘902, ¶¶9, 11, 33]);
access the restoring the context and data to the … processor (accessing the processor state data to generate a second updated hash prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-10, 20, 33]); and
compare the first hash value to the second hash value (detecting whether the integrity of the processor state data has been compromised by comparing the first hash with the second updated hash [Branco ‘902, ¶¶9, 20, 33]).
Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 3, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) to include the teachings of Branco ‘902.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902 does not explicitly disclose: “… storing the encrypted context and encrypted data at the memory … the encrypted context and data … the encrypted context and data …”.
Tsirkin ‘909, however, discloses:
… storing the encrypted context and encrypted data at the memory … the encrypted context and data … the encrypted context and data … (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Branco ‘902) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Branco ‘902) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Branco ‘902) to include the teachings of Tsirkin ‘909.
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138, and further in view of Rawson et al., US 2010/0141664 A1 (hereinafter, “Rawson ‘664”).
As per claim 5: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138 discloses all limitations of claim 1, as stated above, from which claim 5 is dependent upon. Furthermore, Jayavant ‘413 discloses:
wherein the parallel processor comprises a graphics processing unit (GPU) and the data accessed (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC) [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2])
As stated above, Jayavant ‘413 does not explicitly disclose: “… the data accessed by the trusted processor is stored at a frame buffer of the GPU.”
Rawson ‘664, however, discloses:
… the data accessed by the (the data accessed by the processor 202 is stored at the frame buffer in the graphics memory 234 of the GPU [Rawson ‘664, ¶¶7, 21, 25; Fig. 2]).
Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Rawson ‘664 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Rawson ‘664 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) to include the teachings of Rawson ‘664, namely to access and store operating state information and data of a graphics processing unit 240 (GPU), as disclosed by Jayavant ‘413, from the frame buffer of the GPU 240, as disclosed by Rawson ‘664. The motivation for doing so would be to clarify the specific part of the GPU local memory, the frame buffer, that contains the relevant state and context data of the GPU that is to be accessed (see Rawson ‘664, ¶¶7, 21).
As stated above, Jayavant ‘413 in view of Rawson ‘664 does not explicitly disclose: “… the data accessed by the trusted processor …”.
Branco ‘902, however, discloses:
… the data accessed by the trusted processor … (determining and accessing, by the processing circuitry 104 that may operate in secure mode, processor state data for a processor, where the processor data is verified to ensure its integrity [Branco ‘902, ¶¶11-12, 16, 19, 27; Fig. 1, Fig. 3])
Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Rawson ‘664) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Rawson ‘664) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Chheda ‘138 & Rawson ‘664) to include the teachings of Branco ‘902.
As per claim 18: Jayavant ‘413, in view of Branco ‘902, and further in view of Gulati ‘538, and further in view of Chheda ‘138 discloses all limitations of claim 14, as stated above, from which claim 18 is dependent upon. Furthermore, Jayavant ‘413 discloses:
wherein the parallel processor comprises a graphics processing unit (GPU) and the data accessed (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC) [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2])
As stated above, Jayavant ‘413 does not explicitly disclose: “… the data accessed by the trusted processor is stored at a frame buffer of the GPU.”
Rawson ‘664, however, discloses:
… the data accessed by the (the data accessed by the processor 202 is stored at the frame buffer in the graphics memory 234 of the GPU [Rawson ‘664, ¶¶7, 21, 25; Fig. 2]).
Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Rawson ‘664 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) and Rawson ‘664 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Chheda ‘138) to include the teachings of Rawson ‘664, namely to access and store operating state information and data of a graphics processing unit 240 (GPU), as disclosed by Jayavant ‘413, from the frame buffer of the GPU 240, as disclosed by Rawson ‘664. The motivation for doing so would be to clarify the specific part of the GPU local memory, the frame buffer, that contains the relevant state and context data of the GPU that is to be accessed (see Rawson ‘664, ¶¶7, 21).
As stated above, Jayavant ‘413 in view of of Rawson ‘664 does not explicitly disclose: “… the data accessed by the trusted processor …”.
Branco ‘902, however,