DETAILED ACTION
Response to Arguments
Applicant's arguments ("REMARKS") filed 27 March 2026 have been fully considered, and they are not persuasive as to the previous grounds of rejection.
No claims were amended. Claim 7 was previously canceled. Claims 1, 8, and 14 are independent. Claims 1-6 and 8-20 are currently pending.
Re: Claim Rejections Under 35 U.S.C. §103
Applicant’s arguments, indicated on pp.6-12 of the REMARKS, in response to the rejection of the claims under 35 U.S.C. §103 with respect to Jayavant et al., US 2013/0027413 A1 (hereinafter, “Jayavant ‘413”), Gulati et al., US 2019/0171538 A1 (hereinafter, “Gulati ‘538”), Senda, US 2017/0097836 A1 (hereinafter, “Senda ‘836”), and Branco, US 2017/0168902 A1 (hereinafter, “Branco ‘902”) have been fully considered, and they are not persuasive as to the previous grounds of rejection. In particular, with respect to the independent claims, Applicant argues that:
Senda ‘836’s alternative driver is itself a driver for the video hardware.
No component in the cited references performs both the accessing and the restoring limitations recited in the independent claims.
In Response to Argument A
On pp.6-7 of the REMARKS, Applicant argues that Senda ‘836’s alternative driver is itself a driver for the video hardware. Applicant does not dispute that Senda ‘836 discloses a component that performs recovery processing for video hardware 21 from an energy-saving mode before the video driver 62 is activated. Rather, Applicant argues that this component (alternative driver 32) is itself a driver that corresponds to the video hardware, and that Senda ‘836 therefore cannot disclose restoring the context and data “before or while a central processing unit (CPU) of the processing system triggers initialization of a driver for the parallel processor”, because the substitute component is a driver that is initialized for the video hardware.
The Examiner respectfully disagrees.
First, this argument attacks Senda ‘836 in isolation. One cannot show nonobviousness by attacking references individually where, as here, the rejection is based on a combination of references. In re Keller, 642 F.2d 413, 425 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986); MPEP § 2145(IV). Senda ‘836 is not relied upon to disclose the component that performs the restoration. That component is disclosed by Gulati ‘538, which discloses a context save and restore circuit 58 that performs the save and restore operations independent of instructions from CPU 16 (Gulati ‘538, ¶¶98-99, 133; Fig.2). Senda ‘836 is relied upon for the relationship between the restoration and the triggering of driver initialization. The proposed modification does not import Senda ‘836’s alternative driver 32 into the combination as the restoring agent. The modification applies Senda ‘836’s disclosure that the recovery process may be completed before, or concurrently with, the invocation of the corresponding driver.
Second, Applicant’s argument presumes that the recited “driver for the parallel processor” reads on the alternative driver 32 of Senda ‘836, and that the restoration therefore occurs after that driver’s initialization is triggered. Even accepting that premise, the claim is not limited to restoration occurring before driver initialization is triggered. The independent claims recite restoration occurring “before or while” the CPU triggers initialization of a driver for the parallel processor. Senda ‘836 discloses that the information processing apparatus 100 includes a control device 11 such as a central processing unit (CPU) (Senda ‘836, ¶22; Fig. 1). Upon recovery from the energy-saving mode, the host OS 30 (implemented by the control device 11 (Senda ‘836, ¶25)) invokes a recovery processing routine of each driver, including a recovery processing routine for the alternative driver 32, where the alternative driver 32 then performs the recovery processing of the video hardware 21 and stores the contents in the alternative driver structure 201 (Senda ‘836, ¶¶57-58, 65; Fig. 6, Fig.7). The recovery of the video hardware 21 and the invocation of the alternative driver 32 are thus part of the same sequence. The restoration is performed while the CPU triggers initialization of that driver. It is further noted that the claim recites that the CPU “triggers initialization” of a driver, not that the driver completes initialization. Under the broadest reasonable interpretation, the invocation of the driver’s recovery routine is a trigger.
Senda ‘836 also discloses the “before” alternative, as recited in the independent claims. The recovery processing of the video hardware 21 is performed substitutively by the alternative driver 32 before the guest OS 60 invokes the recovery processing routine of the video driver 62, and the video driver 62 thereafter succeeds the contents of that processing rather than repeating it (Senda ‘836, ¶¶60-61, 63, 69-70; Fig.6, Fig.8). Senda ‘836 states that the recovery processing can be started beforehand by the alternative driver 32 without waiting for completion of activation (recovery) of the guest OS 60 (Senda ‘836, ¶63). The video driver 62 is a driver for the video hardware 21 (Senda ‘836, ¶30). Accordingly, the limitation is met under either the “before” or the “while” alternative.
Third, Applicant’s argument relies on limitations that are not recited in the independent claims. Limitations from the specification are not read into the claims, and arguments must be directed to the claims as they stand. In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993); In re Self, 671 F.2d 1344, 1348 (CCPA 1982); MPEP § 2145(VI). Claim 1 requires only that the restoration occur “before or while a central processing unit (CPU) of the processing system triggers initialization of a driver for the parallel processor”. The claim does not exclude the initialization of any other driver. The disclosure of an additional driver does not remove Senda ‘836 from the scope of the claim.
In Response to Argument B
On pp.7-8 of the REMARKS, Applicant argues that the combination of references fails to teach or suggest any component (much less “a trusted processor”) that performs both the accessing and the restoring features recited in claim 1.
The Examiner respectfully disagrees.
Gulati ‘538 discloses a context save and restore circuit 58 that performs both the accessing and the restoring features recited in the independent claims. Gulati ‘538 states that the context save and restore circuit 58 may be hardwire circuitry that stores contexts of GPU 18 prior to the self-test and restores the context of GPU 18 subsequent to self-test, and that the circuit may store the values of internal registers, depth buffer, frame buffer and the like into system memory 30, and retrieve the values from system memory 30 for restoring GPU 18 (Gulati ‘538, ¶98). Gulati ‘538 further states that the context save and restore circuit 58 is responsible for saving any necessary state and restoring it on exit from the self-test independent of CPU 16, and that no software context save and restore process may be needed (Gulati ‘538, ¶¶99, 133; Fig.5). Thus, Gulati ‘538 discloses a single hardwired circuit that both stores the GPU context to an external system memory and retrieves that context from the external system memory for restoration to the GPU. The reference to “a trusted processor” in the Applicant’s argument is not accompanied by an explanation of why the context save and restore circuit 58 of Gulati ‘538, as combined with the system embedded controller 150 of Jayavant ‘413, fails to disclose said limitation. Jayavant ‘413 also discloses a single controller that controls both directions of the transfer. The system embedded controller 150 initiates and controls the entry into and exit from the deep sleep state. The system embedded controller 150 directs that the GPU 240 restore an operating state from the SPI flash device 256 rather than perform a full cold-boot sequence (Jayavant ‘413, ¶¶28-30, 39, 41; Fig. 2, Fig.4A, Fig.4B).
Thus, for the reasons stated above, the rejection of independent claims 1, 8, and 14 under 35 U.S.C. 103 is maintained. Claims 2-6, 9-13, and 14-20 are rejected for at least the same reasons due to their dependency on the corresponding independent claims.
See Claim Rejections – 35 USC §103 below for further details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant et al., US 2013/0027413 A1 (hereinafter, “Jayavant ‘413”), in view of Gulati et al., US 2019/0171538 A1 (hereinafter, “Gulati ‘538”), and further in view of Senda, US 2017/0097836 A1 (hereinafter, “Senda ‘836”).
As per claim 1: Jayavant ‘413 discloses:
A method comprising:
accessing, (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC); the save and restore operations are initiated and controlled by the EC 150 [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2]) in response to the parallel processor powering down (accessing and storing operating state information and data in response to the GPU 240 entering a sleep mode and powering down [Jayavant ‘413, ¶¶6, 30, 35-36, 39; Fig. 2, Fig. 4A]);
storing the context and data at a memory external to the parallel processor (storing the operating state information and data at a memory 244, 256, where the memory 244, 256 is coupled to the GPU 240 and external to the GPU 240 [Jayavant ‘413, ¶¶36, 39, 43-44; Fig. 2, Fig. 4A]); and
in response to the parallel processor powering up, restoring, (restoring the operating state information and data to the GPU 240, from the external memory 244, 256, in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 2, Fig. 4B])
Jayavant ‘413, as stated above, does not explicitly disclose: “… accessing, by a trusted processor, context and data of a ... restoring, by the trusted processor, the context and data ... before or while a central processing unit (CPU) of the processing system triggers initialization of a driver for the parallel processor.”
Gulati ‘538, however, discloses:
… accessing, by a trusted processor, context and data of a ... restoring, by the trusted processor, the context and data ... (the context save and restore circuit 58, which is hardwired circuitry separate from the GPU execution units, storing GPU context including values of internal registers, depth buffer, instruction buffer, frame buffer into system memory 30, and restoring the context to the GPU, where the context save and restore circuit 58 performs these operations independent of instructions from CPU 16 [Gulati ‘538, ¶¶98-99, 133; Fig. 2]) .
Jayavant ‘413 and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 and Gulati ‘538 before them, to modify the method in Jayavant ‘413 to include the teachings of Gulati ‘538, namely to implement the context save and restore operations using a dedicated hardwired circuit, as disclosed in Gulati ‘538, such that the context save and restore operations may be performed independent of the CPU. The motivation for doing so would be to reduce the complexity of context save and restore by bypassing the CPU and eliminating the need for software-controlled handshaking operations (see Gulati ‘538, ¶¶20, 57, 97).
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “... restoring ... before or while a central processing unit (CPU) of the processing system triggers initialization of a driver for the parallel processor.”
Senda ‘836, however, discloses:
... restoring ... before or while a central processing unit (CPU) of the processing system triggers initialization of a driver for the parallel processor (an alternative driver 32 performing recovery processing for video hardware 21 from an energy-saving mode, where the recovery processing is performed substitutively before the video driver 62 is activated; the control device 11, which comprises a CPU, is configured to activate the video driver 62 [Senda ‘836, ¶¶22, 25, 34-37, 63, 70]).
Jayavant ‘413 (modified by Gulati ‘538) and Senda ‘836 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of video/graphics processor state data during power state transitions. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538) and Senda ‘836 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538) to include the teachings of Senda ‘836, namely to perform the GPU context restoration before the video driver is activated, as disclosed in Senda ‘836. The motivation for doing so would be to reduce system wake latency and avoid redundant hardware initialization processing, since the video driver can succeed the contents of the recovery processing without performing recovery processing again (see Senda ‘836, ¶¶63, 70-71).
As per claim 14: Jayavant ‘413 discloses:
A processing system (computer system 100 device [Jayavant ‘413, ¶19; Fig. 1]), comprising: a central processing unit (CPU) (CPU 102 [Jayavant ‘413, ¶19; Fig. 1]); a parallel processor (GPU 240 [Jayavant ‘413, ¶24; Fig. 2]); a memory external to the parallel processor (memory system 242 and SPI flash 256, where memory 242, 256 is coupled to the GPU 240 and external to the GPU 240 [Jayavant ‘413, ¶¶24-25, 36, 39, 43-44; Fig. 2, Fig. 4A]); and (system EC 150 configured to perform operations [Jayavant ‘413, ¶¶20, 24, 28-30; Fig. 2]):
access a context of the parallel processor and data stored at the parallel processor (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC); the save and restore operations are initiated and controlled by the EC 150 [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2]) in response to the parallel processor powering down (accessing and storing operating state information and data in response to the GPU 240 entering a sleep mode and powering down [Jayavant ‘413, ¶¶6, 30, 35-36, 39; Fig. 2, Fig. 4A]);
store the context and data at the memory (storing the operating state information and data at a memory [Jayavant ‘413, ¶¶36, 39, 43-44; Fig. 4A]); and
in response to the parallel processor powering up, restore the context and data from the memory to the parallel processor (restoring the operating state information and data to the GPU 240, from the external memory 242, 256, in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 2, Fig. 4B])
Jayavant ‘413, as stated above, does not explicitly disclose: “... a trusted processor configured to: access ... restore ... before or while the CPU triggers initialization of a driver for the parallel processor.”
Gulati ‘538, however, discloses:
... a trusted processor configured to: access ... store ... restore (the context save and restore circuit 58, which is hardwired circuitry, configured to store GPU context including values of internal registers, depth buffer, instruction buffer, frame buffer into system memory 30, and restore the context to the GPU, where the operations are performed independent of instructions from CPU 16 [Gulati ‘538, ¶¶98-99, 133; Fig. 2]) .
Jayavant ‘413 and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 and Gulati ‘538 before them, to modify the method in Jayavant ‘413 to include the teachings of Gulati ‘538.
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “... restore ... before or while the CPU triggers initialization of a driver for the parallel processor.”
Senda ‘836, however, discloses:
... restore ... before or while the CPU triggers initialization of a driver for the parallel processor (an alternative driver 32 performing recovery processing for video hardware 21 from an energy-saving mode, where the recovery processing is performed substitutively before the video driver 62 is activated; the control device 11, which comprises a CPU, is configured to activate the video driver 62 [Senda ‘836, ¶¶22, 25, 34-37, 63, 70]).
Jayavant ‘413 (modified by Gulati ‘538) and Senda ‘836 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of video/graphics processor state data during power state transitions. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538) and Senda ‘836 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538) to include the teachings of Senda ‘836.
As per claim 20: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 discloses all limitations of claim 14, as stated above, from which claim 20 is dependent upon. Furthermore, Jayavant ‘413 discloses:
wherein the parallel processor is to bypass reinitializing in response to the parallel processor powering up (under the broadest reasonable interpretation, ‘reinitialization’ is interpreted as a cold-boot where normal operation is resumed after a considerable time due to data processing; bypassing a cold boot sequence of the GPU by resuming normal operations after exiting sleep mode in an efficient warm boot sequence [Jayavant ‘413, ¶¶6, 30, 41-43]).
Claims 8, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco, US 2017/0168902 A1 (hereinafter, “Branco ‘902”).
As per claim 8: Jayavant ‘413 discloses:
A method, comprising: fetching, by a trusted processor, context and data for a parallel processor stored at a memory of a processing system in response to the parallel processor powering up, wherein the memory is external to the parallel processor (retrieving the operating state information and data, from memory 244, 256, to the GPU 240 of a computer system 100 in response to the GPU 240 exiting sleep mode and powering up, where the memory 244, 256 is coupled to the GPU 240 and external to the GPU 240 [Jayavant ‘413, ¶¶30, 36, 39, 41, 43-44; Fig. 2, Fig. 4B]);
restoring, (restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B])
Jayavant ‘413, as stated above, does not explicitly disclose: “fetching, by a trusted processor ... verifying, at the trusted processor, that the context and data are untampered; and restoring, by the trusted processor ... before or while a central processing unit (CPU) of the processing system triggers initialization of a driver for the parallel processor.”
Gulati ‘538, however, discloses:
fetching, by a trusted processor ... restoring, by the trusted processor (the context save and restore circuit 58, which is hardwired circuitry, fetching and restoring GPU context from system memory 30 to the GPU, independent of instructions from CPU 16 [Gulati ‘538, ¶¶98-99, 133; Fig. 2]) ... .
Jayavant ‘413 and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of GPU state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 and Gulati ‘538 before them, to modify the method in Jayavant ‘413 to include the teachings of Gulati ‘538.
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “... verifying, at the trusted processor, that the context and data are untampered ... before or while a central processing unit (CPU) of the processing system triggers initialization of a driver for the parallel processor.”
Senda ‘836, however, discloses:
… ...
... restoring ... before or while a central processing unit (CPU) of the processing system triggers initialization of a driver for the parallel processor (an alternative driver 32 performing recovery processing for video hardware 21 from an energy-saving mode, where the recovery processing is performed substitutively before the video driver 62 is activated; the control device 11, which comprises a CPU, is configured to activate the video driver 62 [Senda ‘836, ¶¶22, 25, 34-37, 63, 70])
Jayavant ‘413 (modified by Gulati ‘538) and Senda ‘836 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of video/graphics processor state data during power state transitions. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538) and Senda ‘836 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538) to include the teachings of Senda ‘836.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Senda ‘836 does not explicitly disclose: “verifying, at the trusted processor, that the context and data are untampered.”
Branco ‘902, however, discloses:
verifying, at the trusted processor, that the context and data are untampered (detecting by the secure processing circuitry 104 whether the integrity of the processor state data has been compromised using hash verification, where the detection is performed prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-12, 20; Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) to include the teachings of Branco ‘902, namely to verify the integrity of the GPU context and data using hash verification prior to restoration. The motivation for doing so would be to improve the protection of processor state data by detecting whether the stored state has been compromised or tampered with (see Branco ‘902, ¶¶2-3, 9).
As per claim 13: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco ‘902 discloses all limitations of claim 8, as stated above, from which claim 13 is dependent upon. Furthermore, Jayavant ‘413 discloses:
further comprising: bypassing reinitialization of the parallel processor in response to the parallel processor powering up (under the broadest reasonable interpretation, ‘reinitialization’ is interpreted as a cold-boot where normal operation is resumed after a considerable time due to data processing; bypassing a cold boot sequence of the GPU by resuming normal operations after exiting sleep mode in an efficient warm boot sequence [Jayavant ‘413, ¶¶6, 30, 41-43]).
As per claim 15: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 discloses all limitations of claim 14, as stated above, from which claim 15 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]).
As stated above, Jayavant ‘413 does not explicitly disclose: “wherein the trusted processor is to detect tampering of the context and data prior to restoring the context and data to the ... processor.”
Branco ‘902, however, discloses:
wherein the trusted processor is to detect tampering of the context and data prior to restoring the context and data to the ... processor (the secure processing circuitry 104 detecting that the integrity of the processor state data has been compromised using hash verification, where the detection is performed prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-12, 20; Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 8, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) to include the teachings of Branco ‘902.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Tsirkin, US 2018/0239909 A1 (hereinafter, “Tsirkin ‘909”).
As per claim 2: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 discloses all limitations of claim 1, as stated above, from which claim 2 is dependent upon. Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 does not explicitly disclose the limitations of claim 2. Tsirkin ‘909, however, discloses:
encrypting the context and data to generate an encrypted context and encrypted data prior to storing the encrypted context and encrypted data at the memory (encrypting the processor state and data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) to include the teachings of Tsirkin ‘909, namely to encrypt the operating state information and data, as disclosed in Tsirkin ‘909, prior to storing the operating state information and data at a memory, as disclosed in Jayavant ‘413. The motivation for doing so would be to increase the protection of processor states such that they cannot be accessed by unauthorized entities (see Tsirkin ‘909, ¶¶13-16).
Claims 3-4 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Tsirkin ‘909, and further in view of Branco ‘902.
As per claim 3: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Tsirkin ‘909 discloses all limitations of claims 1-2, as stated above, from which claim 3 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]).
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “detecting tampering of the encrypted context and encrypted data prior to restoring the context and data to the ... processor.”
Branco ‘902, however, discloses:
detecting tampering of the restoring the context and data to the ... processor (detecting that the integrity of the processor state data has been compromised using hash verification, where the detection is performed prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-12, 20; Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) to include the teachings of Branco ‘902, namely to determine the integrity of the operating state information and data using hash verification, as disclosed in Branco ‘902, prior to restoring the operating state information and data, as disclosed in Jayavant ‘413. The motivation for doing so would be to improve the protection of processor state data by ensuring the integrity of processor state data and that only privileged processing circuitry may operate on and access processor state data (see Branco ‘902, ¶¶2-3, 9).
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902 does not explicitly disclose: “... encrypted context and encrypted data ...”.
Tsirkin ‘909, however, discloses:
... encrypted context and encrypted data ... (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) to include the teachings of Tsirkin ‘909.
As per claim 4: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Tsirkin ‘909, and further in view of Branco ‘902 discloses all limitations of claims 1-3, as stated above, from which claim 4 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]),
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “hashing the context and data to generate a first hash value prior to storing the encrypted context and encrypted data at the memory; and accessing the encrypted context and encrypted data and hashing the encrypted context and encrypted data to generate a second hash value prior to restoring the context and data to the ... processor, and wherein detecting comprises comparing the first hash value to the second hash value.”
Branco ‘902, however, discloses:
hashing the context and data to generate a first hash value prior to storing the (hashing the processor state data to generate a hash and storing the processor state data in memory [Branco ‘902, ¶¶9, 11, 33]); and
accessing the restoring the context and data to the ... processor (accessing the processor state data to generate a second updated hash prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-10, 20, 33]),
wherein detecting comprises comparing the first hash value to the second hash value (detecting whether the integrity of the processor state data has been compromised by comparing the first hash with the second updated hash [Branco ‘902, ¶¶9, 20, 33]).
Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 3, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) to include the teachings of Branco ‘902.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902 does not explicitly disclose: “... storing the encrypted context and encrypted data at the memory ... the encrypted context and encrypted data ...”.
Tsirkin ‘909, however, discloses:
... storing the encrypted context and encrypted data at the memory ... the encrypted context and encrypted data ... (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) to include the teachings of Tsirkin ‘909.
As per claim 16: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco ‘902 discloses all limitations of claims 14-15, as stated above, from which claim 16 is dependent upon. Jayavant ‘413 in view of Gulati ‘538, and further in view of Senda ‘836 does not explicitly disclose the limitations of claim 16. Tsirkin ‘909, however, discloses:
wherein the (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Senda ‘836 & Branco ‘902) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Senda ‘836 & Branco ‘902) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Senda ‘836 & Branco ‘902) to include the teachings of Tsirkin ‘909.
As stated above, Jayavant ‘413 in view of Tsirkin ‘909 does not explicitly disclose: “wherein the trusted processor is to: ...”.
Gulati ‘538, however, discloses:
wherein the trusted processor is to: ... (the context save and restore circuit 58, which is hardwired circuitry, configured to perform operations on GPU context independent of instructions from CPU 16 [Gulati ‘538, ¶¶98-99, 133; Fig. 2]).
Jayavant ‘413 (modified by Senda ‘836 & Tsirkin ‘909 & Branco ‘902) and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Senda ‘836 & Tsirkin ‘909 & Branco ‘902) and Gulati ‘538 before them, to modify the method in Jayavant ‘413 (modified by Senda ‘836 & Tsirkin ‘909 & Branco ‘902) to include the teachings of Gulati ‘538.
As per claim 17: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Tsirkin ‘909, and further in view of Branco ‘902 discloses all limitations of claims 14-16, as stated above, from which claim 17 is dependent upon. Furthermore, Jayavant ‘413 discloses:
wherein the
(restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]); and
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “wherein the trusted processor is to: hash the context and data to generate a first hash value prior to storing the encrypted context and encrypted data at the memory; access the encrypted context and data and hash the encrypted context and data to generate a second hash value prior to restoring the context and data to the ... processor; and compare the first hash value to the second hash value.”
Branco ‘902, however, discloses:
wherein the trusted processor is to: hash the context and data to generate a first hash value prior to storing the (the secure processing circuitry hashing the processor state data to generate a hash and storing the processor state data in memory [Branco ‘902, ¶¶9, 11, 33]);
access the restoring the context and data to the ... processor (accessing the processor state data to generate a second updated hash prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-10, 20, 33]); and
compare the first hash value to the second hash value (detecting whether the integrity of the processor state data has been compromised by comparing the first hash with the second updated hash [Branco ‘902, ¶¶9, 20, 33]).
Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 8, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 and Senda ‘836) to include the teachings of Branco ‘902.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902 does not explicitly disclose: “... storing the encrypted context and encrypted data at the memory ... the encrypted context and data ... the encrypted context and data ...”.
Tsirkin ‘909, however, discloses:
... storing the encrypted context and encrypted data at the memory ... the encrypted context and data ... the encrypted context and data ... (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836 & Branco ‘902) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836 & Branco ‘902) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836 & Branco ‘902) to include the teachings of Tsirkin ‘909.
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Rawson et al., US 2010/0141664 A1 (hereinafter, “Rawson ‘664”).
As per claim 5: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 discloses all limitations of claim 1, as stated above, from which claim 5 is dependent upon. Furthermore, Jayavant ‘413 discloses:
wherein the parallel processor comprises a graphics processing unit (GPU) and the data accessed (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC); the save and restore operations are initiated and controlled by the EC 150 [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2])
As stated above, Jayavant ‘413 does not explicitly disclose: “... the data accessed by the trusted processor is stored at a frame buffer of the GPU.”
Rawson ‘664, however, discloses:
... the data accessed by the (the data accessed by the processor 202 is stored at the frame buffer in the graphics memory 234 of the GPU [Rawson ‘664, ¶¶7, 21, 25; Fig. 2]).
Jayavant ‘413 (modified by Senda ‘836) and Rawson ‘664 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Senda ‘836) and Rawson ‘664 before them, to modify the method in Jayavant ‘413 (modified by Senda ‘836) to include the teachings of Rawson ‘664, namely to access and store operating state information and data of a graphics processing unit 240 (GPU), as disclosed by Jayavant ‘413, from the frame buffer of the GPU 240, as disclosed by Rawson ‘664. The motivation for doing so would be to clarify the specific part of the GPU local memory, the frame buffer, that contains the relevant state and context data of the GPU that is to be accessed (see Rawson ‘664, ¶¶7, 21).
As stated above, Jayavant ‘413 in view of Rawson ‘664 does not explicitly disclose: “... the data accessed by the trusted processor ...”.
Gulati ‘538, however, discloses:
... the data accessed by the trusted processor ... (the context save and restore circuit 58, which is hardwired circuitry, accessing and storing GPU context [Gulati ‘538, ¶¶98-99, 133; Fig. 2]).
Jayavant ‘413 (modified by Senda ‘836 & Rawson ‘664) and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Senda ‘836 & Rawson ‘664) and Gulati ‘538 before them, to modify the method in Jayavant ‘413 (modified by Senda ‘836 & Rawson ‘664) to include the teachings of Gulati ‘538.
As per claim 18: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 discloses all limitations of claim 14, as stated above, from which claim 18 is dependent upon. Furthermore, Jayavant ‘413 discloses:
wherein the parallel processor comprises a graphics processing unit (GPU) and the data accessed (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC); the save and restore operations are initiated and controlled by the EC 150 [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2])
As stated above, Jayavant ‘413 does not explicitly disclose: “... the data accessed by the trusted processor is stored at a frame buffer of the GPU.”
Rawson ‘664, however, discloses:
... the data accessed by the (the data accessed by the processor 202 is stored at the frame buffer in the graphics memory 234 of the GPU [Rawson ‘664, ¶¶7, 21, 25; Fig. 2]).
Jayavant ‘413 (modified by Senda ‘836) and Rawson ‘664 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 5, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Senda ‘836) and Rawson ‘664 before them, to modify the method in Jayavant ‘413 (modified by Senda ‘836) to include the teachings of Rawson ‘664.
As stated above, Jayavant ‘413 in view of Rawson ‘664 does not explicitly disclose: “... the data accessed by the trusted processor ...”.
Gulati ‘538, however, discloses:
... the data accessed by the trusted processor ... (the context save and restore circuit 58, which is hardwired circuitry, accessing and storing GPU context [Gulati ‘538, ¶¶98-99, 133; Fig. 2]).
Jayavant ‘413 (modified by Senda ‘836 & Rawson ‘664) and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Senda ‘836 & Rawson ‘664) and Gulati ‘538 before them, to modify the method in Jayavant ‘413 (modified by Senda ‘836 & Rawson ‘664) to include the teachings of Gulati ‘538.
Claims 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Zimmer et al., US 2004/0148536 A1 (hereinafter, “Zimmer ‘536”).
As per claim 6: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 discloses all limitations of claim 1, as stated above, from which claim 6 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(storing operating state information and data at a memory in response to the GPU 240 entering a sleep mode and powering down [Jayavant ‘413, ¶¶6, 30, 35-36, 39, 43-44; Fig. 2, Fig. 4A]).
As stated above, Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 does not explicitly disclose: “allocating, by the driver, a portion of the memory for storing the context and data in response to the ... processor powering down.”
Zimmer ‘536, however, discloses:
allocating, by the driver, a portion of the memory for storing the context and data in response to the ... processor powering down (allocating, using firmware and drivers, a portion of the system memory for storing processor 12 context restore data in response to the processor 12 entering a low power state [Zimmer ‘536, ¶¶11, 19-23, 29-30; Fig. 1, Fig. 3]).
Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) and Zimmer ‘536 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) and Zimmer ‘536 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) to include the teachings of Zimmer ‘536, namely to allocate memory, as disclosed in Zimmer ‘536, in response to the GPU 240 entering a sleep mode and powering down, as disclosed in Jayavant ‘413, such that the allocated memory is used to store operating state information and data. The motivation for doing so would be to increase the efficiency of storing context restore data by using readily available and easily configurable memory on an as-needed basis (see Zimmer ‘536, ¶¶14, 23, 29).
As per claim 19: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836 discloses all limitations of claim 14, as stated above, from which claim 19 is dependent upon. Furthermore, Jayavant ‘413 discloses:
(storing operating state information and data at a memory in response to the GPU 240 entering a sleep mode and powering down [Jayavant ‘413, ¶¶6, 30, 35-36, 39, 43-44; Fig. 2, Fig. 4A]).
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “wherein the trusted processor is to: allocate, by the driver, a portion of the memory for storing the context and data in response to the ... processor powering down.”
Zimmer ‘536, however, discloses:
wherein the the memory for storing the context and data in response to the ... processor powering down (allocating, using firmware and drivers, a portion of the system memory for storing processor 12 context restore data in response to the processor 12 entering a low power state [Zimmer ‘536, ¶¶11, 19-23, 29-30; Fig. 1, Fig. 3]).
Jayavant ‘413 (modified by Senda ‘836) and Zimmer ‘536 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 6, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Senda ‘836) and Zimmer ‘536 before them, to modify the method in Jayavant ‘413 (modified by Senda ‘836) to include the teachings of Zimmer ‘536.
As stated above, Jayavant ‘413 in view of Zimmer ‘536 does not explicitly disclose: “wherein the trusted processor is to: ...”.
Gulati ‘538, however, discloses:
wherein the trusted processor is to: ... (the context save and restore circuit 58, which is hardwired circuitry, configured to perform operations on GPU context [Gulati ‘538, ¶¶98-99, 133; Fig. 2]).
Jayavant ‘413 (modified by Senda ‘836 & Zimmer ‘536) and Gulati ‘538 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 1, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Senda ‘836 & Zimmer ‘536) and Gulati ‘538 before them, to modify the method in Jayavant ‘413 (modified by Senda ‘836 & Zimmer ‘536) to include the teachings of Gulati ‘538.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco ‘902, and further in view of Rawson ‘664, and further in view of Tsirkin ‘909.
As per claim 9: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco ‘902 discloses all limitations of claim 8, as stated above, from which claim 9 is dependent upon. Furthermore, Jayavant ‘413 discloses:
wherein the parallel processor comprises a graphics processing unit (GPU), further comprising: accessing, (accessing and storing operating state information and data of a graphics processing unit 240 (GPU) of a computer system 100, where the data operations are facilitated by embedded controller 150 (EC); the save and restore operations are initiated and controlled by the EC 150 [Jayavant ‘413, ¶¶8, 24, 36, 39, 43; Fig. 1, Fig. 2]) in response to the GPU powering down (accessing and storing operating state information and data in response to the GPU 240 entering a sleep mode and powering down [Jayavant ‘413, ¶¶6, 30, 35-36, 39; Fig. 2, Fig. 4A]);
storing the (storing the operating state information and data at a memory [Jayavant ‘413, ¶¶36, 39, 43-44; Fig. 4A]).
As stated above, Jayavant ‘413 in view of Gulati ‘538 does not explicitly disclose: “... accessing, by the trusted processor ... data stored at a frame buffer of the GPU ... encrypting and hashing the context and data to generate a first hash value; and ... storing the encrypted context and data ...”.
Branco ‘902, however, discloses:
... accessing, by the trusted processor ... data stored at (determining and accessing, by the processing circuitry 104 that may operate in secure mode, processor state data for a processor, where the processor data is verified to ensure its integrity [Branco ‘902, ¶¶11-12, 16, 19, 27; Fig. 1, Fig. 3]) the GPU ...
... storing the context and data ... (hashing the processor state data to generate a hash and storing the processor state data in memory [Branco ‘902, ¶¶9, 11, 33]).
Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claims 1 and 4, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836) to include the teachings of Branco ‘902.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902 does not explicitly disclose: “... accessing ... data stored at a frame buffer of the GPU ... encrypting and ... the context and data ... the encrypted context and data ...”.
Rawson ‘664, however, discloses:
... accessing ... data stored at a frame buffer of the GPU ... (the data accessed by the processor 202 is stored at the frame buffer in the graphics memory 234 of the GPU [Rawson ‘664, ¶¶7, 21, 25; Fig. 2]) …
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) and Rawson ‘664 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 5, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) and Rawson ‘664 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836) to include the teachings of Rawson ‘664.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902, and further in view of Rawson ‘664 does not explicitly disclose: “... encrypting and ... the context and data ... the encrypted context and data ...”.
Tsirkin ‘909, however, discloses:
... encrypting and ... the context and data ... the encrypted context and data ... (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) to include the teachings of Tsirkin ‘909.
As per claim 10: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco ‘902, and further in view of Rawson ‘664, and further in view of Tsirkin ‘909 discloses all limitations of claims 8-9, as stated above, from which claim 10 is dependent upon. Furthermore, Jayavant ‘413 discloses:
further comprising: (restoring the operating state information and data to the GPU 240 in response to the GPU 240 exiting sleep mode and powering up [Jayavant ‘413, ¶¶30, 41, 43-44; Fig. 4B]); and
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Rawson ‘664 does not explicitly disclose: “further comprising: accessing the encrypted context and data and hashing the encrypted context and data to generate a second hash value prior to restoring the context and data to the ... wherein detecting comprises comparing the first hash value to the second hash value.”
Branco ‘902, however, discloses:
further comprising: accessing the restoring the context and data to the ... (accessing the processor state data to generate a second updated hash prior to restoring the processor state to the processor [Branco ‘902, ¶¶9-10, 20, 33]) wherein detecting comprises comparing the first hash value to the second hash value (detecting whether the integrity of the processor state data has been compromised by comparing the first hash with the second updated hash [Branco ‘902, ¶¶9, 20, 33]).
Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Branco ‘902 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 3, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Branco ‘902 before them, to modify the method in Jayavant ‘413 (modified by Gulati ‘538 & Senda ‘836 & Rawson ‘664) to include the teachings of Branco ‘902.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Rawson ‘664, and further in view of Branco ‘902 does not explicitly disclose: “... accessing the encrypted context and data ... the encrypted context and data ...”.
Tsirkin ‘909, however, discloses:
... accessing the encrypted context and data ... the encrypted context and data ... (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) to include the teachings of Tsirkin ‘909.
As per claim 11: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco ‘902, and further in view of Rawson ‘664, and further in view of Tsirkin ‘909 discloses all limitations of claims 8-9, as stated above, from which claim 11 is dependent upon. Jayavant ‘413, in view of Gulati ‘538, and further in view of Branco ‘902, and further in view of Rawson ‘664 does not explicitly disclose the limitations of claim 11. Tsirkin ‘909, however, discloses:
wherein storing comprises: storing the encrypted context and data at a pre-reserved portion of the memory (encrypting the processor state data prior and storing the processor state data at a memory, where the memory is structured to have a portion to store the processor state data [Tsirkin ‘909, ¶¶4, 16, 26, 39, 48, 50; Fig. 1, Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) to include the teachings of Tsirkin ‘909.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco ‘902, and further in view of Rawson ‘664, and further in view of Tsirkin ‘909, and further in view of Zimmer ‘536.
As per claim 12: Jayavant ‘413, in view of Gulati ‘538, and further in view of Senda ‘836, and further in view of Branco ‘902, and further in view of Rawson ‘664, and further in view of Tsirkin ‘909 discloses all limitations of claims 8-9, as stated above, from which claim 12 is dependent upon. Furthermore, Jayavant ‘413 discloses:
further comprising: (storing operating state information and data at a memory in response to the GPU 240 entering a sleep mode and powering down [Jayavant ‘413, ¶¶6, 30, 35-36, 39, 43-44; Fig. 2, Fig. 4A]).
As stated above, Jayavant ‘413, in view of Gulati ‘538, and further in view of Branco ‘902, and further in view of Rawson ‘664 does not explicitly disclose: “allocating, by the driver, a portion of the system memory for storing the encrypted context and data in response to the ... powering down.”
Zimmer ‘536, however, discloses:
allocating, by the driver, a portion of the system memory for storing the context and data in response to the ... powering down (allocating, using firmware and drivers, a portion of the system memory for storing processor 12 context restore data in response to the processor 12 entering a low power state [Zimmer ‘536, ¶¶11, 19-23, 29-30; Fig. 1, Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Zimmer ‘536 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 6, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) and Zimmer ‘536 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664) to include the teachings of Zimmer ‘536.
As stated above, Jayavant ‘413 in view of Gulati ‘538, and further in view of Branco ‘902, and further in view of Rawson ‘664, and further in view of Zimmer ‘536 does not explicitly disclose: “... storing the encrypted context and data ...”.
Tsirkin ‘909, however, discloses:
... storing the encrypted context and data ... (encrypting the processor state data prior to storing the processor state data at a memory [Tsirkin ‘909, ¶¶4, 26, 39, 48, 50; Fig. 3]).
Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664 & Zimmer ‘536) and Tsirkin ‘909 are analogous art because they are from the same field of endeavor, namely that of the management of processing systems through the storing and restoring of processor state data. For the reasons stated in claim 2, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664 & Zimmer ‘536) and Tsirkin ‘909 before them, to modify the method in Jayavant ‘413 (modified by Branco ‘902 & Gulati ‘538 & Senda ‘836 & Rawson ‘664 & Zimmer ‘536) to include the teachings of Tsirkin ‘909.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dalal et al., US 9778728 B2: store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. The component may be configured to wake up the memory controller within the SOC, in order to write the data to memory. The remainder of the SOC may remain powered down.
Sodhi et al., US 9400545 B2: a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
Patil et al., US 20190108037 A1: instead of waiting for the processing operation to be completed by CPU before starting to power-up GPU, the initialization of GPU begins earlier, where at least a portion of initialization of GPU is performed at the same time as processing operation of CPU.
Jane et al., US 9390461 B1: the GPU mode controls may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.
Alben et al., US 7886164 B1: running a GPU self test during bootup, where the self test can be performed independent from the CPU and the driver.
Sulatycke et al., US 20160125565 A1: commands are queued in a related CPU context queue and then fetched independently by the GPU into its own queue. As result, if the CPU stalls, the GPU will continue running without a problem. With regard to the communication between the CPU and GPU, this is performed independently.
Grossman., US 20090160867 A1: The use of a pre-defined, ordered list of contexts allows the GPU to execute certain command threads as if it were independent of the host CPU, where the GPU to make processing decisions independently of the host CPU in order to efficiently exploit the processing capabilities of the GPU.
Schluessler et al., US 11037269 B1: save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory.
Rath et al., US 20140204102 A1: Data and/or control information can be transferred directly to and/or from the GPU without involvement of a central processing unit (CPU) or a host memory. That is, in some embodiments, data to be processed by the GPU can be received by the GPU bypassing the CPU and host memory of the system.
Veal et al., US 20140198116 A1: GPU resources are located in GPU addressable high-speed non-volatile memory at suspend time, they are available at resume time very quickly, which allows the application to resume operation immediately. Resources do not have to be recreated in CPU and GPU addressable memory.
Geng et al., US 2021/0019240 A1: recovering and restoring the context data of processor, where the recovery and restoration of the context data of the processor may occur simultaneously with the initialization of the CPU.
Chheda et al., US 20200104138 A1: technology that triggers an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer.
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/ALAN L KONG/Examiner, Art Unit 2494
/JUNG W KIM/Supervisory Patent Examiner, Art Unit 2494
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