Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The present Office Action is responsive to communication received 4/21/2026. Claims 1, 3-17 and 19-21 are pending.
Response to arguments
Applicant arguments received on 4/21/2026 are addressed as follows:
Regarding the rejection of the claims under 112b, the amendment to the independent claims overcomes the rejection. The rejection is withdrawn.
Regarding the prior art rejection, Applicant arguments have been considered but are not persuasive:
Applicant argues Noehring or any other prior art cited in the previous rejection meet the "inform software in response to detection of the two or more incoming packets." Applicant argues:
“The Office relies on Noehring paragraph [0025] to allegedly meet the limitation "inform software in response to detection of the two or more incoming packets." However, Noehring paragraph [0025] explicitly states that the microcontroller is notified via an interrupt "[a]fter the header, e.g., the first 32 or 64 bytes of the packet, moves into the IFIFO 204." This describes generating an interrupt in response to receiving a single packet's header. Nothing in Noehring teaches or suggests waiting for the detection of "two or more incoming packets" before informing the software. Accordingly, Noehring fails to disclose this limitation.”
The examiner respectfully disagrees, Noehring discloses receiving a data stream of three small packets in the buffer ([0034], to align the packets, for instance align on a 64-bit boundary ([0030]); the CAC command in the SA block cipher denote which ci[her engine or authentication engine each of the three keys corresponding to the three packets goes to ([0034]).
Applicant also argues Chhabra teaches away from the invention, the examiner respectfully disagrees and points to Chhabra teaching processing packets with threshold size T, smaller than the trusted execution size (0126).
The rejection is being clarified below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11, 13-17, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over US 20110258457 to Noehring et al., hereinafter Noehring, in view of US 20200052892 to Chhabra et al., hereinafter Chhabra and US 20170364688 to Desai et al., hereinafter Desai. Noehring is cited in IDS received 10/3/2025
Regarding claim 1, and substantially claim 17, Noehring discloses
An apparatus comprising:
memory coupled to cryptographic logic circuitry; and the cryptographic logic circuitry to receive a plurality of incoming packets of a stream and store two or more incoming packets from the plurality of incoming packets in the memory (Fig. 2, [0021][0022]: cryptographic core receives data stream into IFIFO (memory), the stream comprising a group of packets), wherein the memory is accessible by the cryptographic logic circuitry ([0021]: the cryptographic core encrypts or decrypts the packets stored in the IFIFO),
wherein the cryptographic logic circuitry is to inform software in response to detection of the two or more incoming packets ([0034]: receiving a data stream of three small packets in the buffer, aligned on a 64-bit boundary ([0030]); the CAC command in the SA block cipher denote which ci[her engine or authentication engine each of the three keys corresponding to the three packets goes to ([0034])).
Noehring discloses aligning the packets on a specific size before processing of the packets ([0030]); Noehring does not explicitly teach but in an analogous art Chhabra discloses the cryptographic logic circuitry is to cryptographically process a packet having a size larger than any one of the two or more incoming packets, wherein a combination of the two or more incoming packets are to form the packet to be cryptographically processed by the cryptographic logic circuitry ([0126][0127]: processing packet of trusted execution session greater than threshold size T of each packet).
Noehring and Chhabra are both drawn to processing packets in a stream using cryptographic cores; it would have been obvious to a skilled artisan before the instant application was filed to process packets larger than a threshold size of incoming packets for processing as taught by Chhabra, because it would “reduce or eliminate cryptographic waste as a foundation approach to ensure reduced or no latency addition for encryption/decryption in the presence of variable sized requests sent or received over one or more communication links … “ (Chhabra [0022], see also [0055]).
Noehring in view of Chhabra fails to teach the memory is accessible by the cryptographic logic circuitry and inaccessible by the software. In an analogous art, Desai discloses a channel identifier (CID) filter controlling the size of packets received for encryption in a trusted I/O processor reserved memory (TIO PRM) ([0022]; “the contents of the TIO PRM are thus not accessible to untrusted software of the computing device 100 such as an operating system or operating system drivers and also not accessible to trusted software such as application enclaves” ([0051]). Therefore Desai disclose the memory inaccessible by the software including operating system. It would have been obvious to a skilled artisan before the instant application was filed to receive stream of packets in a memory inaccessible by software as taught by Desai because it would protect the confidentiality of plaintext data against untrusted software (Desai [0018]).
Regarding claim 17, the claim recites substantially the same content as claim 1 and is rejected by the rationale set forth for rejecting claim 1.
Regarding claims 3 and substantially claim 19, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1 or non-transitory computer-readable medium of claim 17, wherein the software is to indicate to the cryptographic logic circuitry whether to drop one or more transactions to be received after the two or more incoming packets (Noehring [0029]) or to process the two or more incoming packets out-of- order and continue to process the one or more transactions (Chhabra [0067]: receive interleaved packets of different sizes, hence the method to break up packets to be the same size for processing (see claim 1)).
Regarding claims 4 and substantially claim 20, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1 or non-transitory computer-readable medium of claim 17, the cryptographic logic circuitry is to receive the two or more incoming packets out-of-order transactions (Chhabra [0067]: receive interleaved packets of different sizes, hence the method to break up packets to be the same size for processing (see claim 1)).
Regarding claim 5, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to notify the software after a first granularity of encrypted or decrypted transaction size has been reached in response to a request by the software to be notified after reaching the first granularity (Noehring [0017], Chhabra [0058]: 64 bit of GCM granularity to process the packets, see claim 1 for motivation to combine with Noehring).
Regarding claim 6, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the two or more incoming packets are fragmented or unaligned for Advanced Encryption Standard (AES) encryption or AES decryption (Noehring [0035]).
Regarding claim 7, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the two or more incoming packets are each to have a lower size than 16 bytes (Noehring [0030]: packets size 64-bits or 8 bytes).
Regarding claim 8, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, the plurality of incoming packets have a size to be determined at boot time or design time (Noehring [0032]: use of a 32-bits processor, per design or Chhabra [0064]: use of 64B block size).
Regarding claim 9, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein at least one of the plurality of incoming packets is 16 bytes (Chhabra [0127][0128]: packets between 0 -M bytes, where M =1024).
Regarding claim 10, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to encrypt or decrypt the two or more incoming packets (Noehring [0019][0035]).
Regarding claim 11, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to encrypt or decrypt the two or more incoming packets in accordance with Advanced Encryption Standard (AES) (Noehring [0035]).
Regarding claim 13, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the memory comprises one or more of SRAM (Static Random Access Memory), MRAM (Magnetoresistive Random Access Memory), and DRAM (Dynamic Random Access Memory (Chhabra [0097]).
Regarding claim 14, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to store a transaction identifier corresponding to the two or more incoming packets in a buffer (Noehring [0022], fig. 2, IFIFO 204: header identifying protocol to se to process packets).
Regarding claim 15, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the memory comprises the buffer (Noehring fig. 2, IFIFO 204).
Regarding claim 16, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to notify the software after encrypting or decrypting the two or more incoming packets (Desai [0042]: encrypt data and pass to OS).
Regarding claim 21, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the software is an operating system (Desai, [0051], see claim 1 for motivation to combine).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Noehring, in view of Chhabra and Desai, and further in view of Zhang, et al. "Ensuring data confidentiality with a secure XTS-AES design in flash translation layer." 2020 IEEE, pages 289-294, hereinafter Zhang.
Regarding claim 12, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, but fails to explicitly teach the cryptographic logic circuitry is to encrypt or decrypt the two or more incoming packets in accordance with Advanced Encryption Standard (AES) in XEX-based Tweakable-codebook mode with ciphertext Stealing (XTS) mode.
However using (AES) in XEX-based Tweakable-codebook mode with ciphertext Stealing (XTS) mode is known in the art, as evidenced by Zhang. Zhang discloses using XTS-AES with ciphertext stealing when the sector size is not divisible by the bock size and separately encrypting plaintext blocks with a tweakable block cipher (p.290, under II, A). It would have been obvious to a skilled artisan before the instant application was filed to apply AES as claimed and as taught by Zhang because it would use a fixed-length encryption that enables XTS to be embedded in the existing storage system easily without modifying the structure of any system (Zhang p.290, in II, A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pismenny et al US 20190116127 discloses combining packet payload before encryption. Pismenny discloses limitations recited in claim 1 as follows:
An apparatus comprising (Fig. 1, 22) : memory (Fig. 1, 30) coupled to cryptographic logic circuitry (Fig. 1 , 40, 0038, 0044) ; and the cryptographic logic circuitry to receive a plurality of incoming packets of a stream and store two or more incoming packets from the plurality of incoming packets in the memory (Fig. 2, stream 51 comprising packets 54 with payload 52 (tcp1, tcp2 …)), wherein the memory is accessible by the cryptographic logic circuitry; wherein the cryptographic logic circuitry is to inform software in response to detection of the two or more incoming packets (0047 processing circuitry 40 signals CPU 28), wherein the cryptographic logic circuitry is to cryptographically process a packet having a size larger than any one of the two or more incoming packets, wherein a combination of the two or more incoming packets are to form the packet to be cryptographically processed by the cryptographic logic circuitry (0049-0050: the lengths of records 56 spans multiples consecutive packets 54, for instance data record 56 processed by processing circuitry marked TLS2 spans the payloads of tcp3, tcp4 and tcp5 ; the record 56 to be encrypted/decrypted by the processing circuit is greater than the size of packets received 54, which are combined to achieve the desired record length).
Jiang et al US 11108751 disclose processing jumbo packet payload with a size greater than the maximum transfer unit size (multiple mtu combined/merged to form a jumbo packet)- encrypted jumbo packet segmented for transmission (fig. 2)-
Balasubramanian et al US 10785020 disclose segmenting one large packet into smaller MTU sized packets on transmit, and combine multiple smaller packets into one large packet on receive.
Izenberg US 20150081726 discloses storing an original packet header, building new packet by combining a new generated header and a transmitted data based on the selected Max Segment Size MSS.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CATHERINE B THIAW whose telephone number is (571)270-1138. The examiner can normally be reached Monday-Thursday 7am-5pm with Flex.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Catherine Thiaw/Supervisory Patent Examiner, Art Unit 2407 9/7/2026
Prosecution Insights