Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/1/2025 has been entered.
Claims 1, 3-17, 19-21 are pending. Claims 2 and 18 are cancelled.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/3/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 17 and their respective dependent claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 3-17, 19-21 recite the limitation “the memory is … inaccessible by the software” (see claims 1 and 17). There is insufficient antecedent basis for “the software” in the claims. For examination purposes, the limitation will be considered as “the memory is … inaccessible by software”. Clarification is kindly requested.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11, 13-17, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over US 20110258457 to Noehring et al., hereinafter Noehring, in view of US 20200052892 to Chhabra et al., hereinafter Chhabra and US 20170364688 to Desai et al., hereinafter Desai. Noehring is cited in IDS received 10/3/2025
Regarding claim 1, and substantially claim 17, Noehring discloses
An apparatus comprising:
memory coupled to cryptographic logic circuitry; and the cryptographic logic circuitry to receive a plurality of incoming packets of a stream and store two or more incoming packets from the plurality of incoming packets in the memory (Fig. 2, [0021][0022]: cryptographic core receives data stream into IFIFO (memory), the stream comprising a group of packets), wherein the memory is accessible by the cryptographic logic circuitry ([0021]: the cryptographic core encrypts or decrypts the packets stored in the IFIFO),
wherein the cryptographic logic circuitry is to inform software in response to detection of the two or more incoming packets ([0025]: the microcontroller 208 (software) is notified via an interrupt after a packet header is detected, to start programming the ARI controllers, thus enabling the ARI controllers to read data from the IFIFO).
Noehring discloses aligning the packets on a specific size before processing of the packets ([0030]); Noehring does not explicitly teach but in an analogous art Chhabra discloses the cryptographic logic circuitry is to cryptographically process a packet having a size larger than any one of the two or more incoming packets, wherein a combination of the two or more incoming packets are to form the packet to be cryptographically processed by the cryptographic logic circuitry ([0058],[0126]: encrypt plaintext data blocks of a data packet of a trusted execution session greater than a data packet size threshold in sub-groups of plaintext data blocks that are smaller than the data packet size threshold). Noehring and Chhabra are both drawn to processing packets in a stream using cryptographic cores; it would have been obvious to a skilled artisan before the instant application was filed to combine packets in a packet of a larger size for processing as taught by Chhabra, because it would “reduce or eliminate cryptographic waste as a foundation approach to ensure reduced or no latency addition for encryption/decryption in the presence of variable sized requests sent or received over one or more communication links … “ (Chhabra [0022], see also [0055]).
Noehring in view of Chhabra fails to teach the memory is accessible by the cryptographic logic circuitry and inaccessible by the software. In an analogous art, Desai discloses a channel identifier (CID) filter controlling the size of packets received for encryption in a trusted I/O processor reserved memory (TIO PRM) ([0022]; “the contents of the TIO PRM are thus not accessible to untrusted software of the computing device 100 such as an operating system or operating system drivers and also not accessible to trusted software such as application enclaves” ([0051]). Therefore Desai disclose the memory inaccessible by the software including operating system. It would have been obvious to a skilled artisan before the instant application was filed to receive stream of packets in a memory inaccessible by software as taught by Desai because it would protect the confidentiality of plaintext data against untrusted software (Desai [0018]).
Regarding claim 17, the claim recites substantially the same content as claim 1 and is rejected by the rationale set forth for rejecting claim 1.
Regarding claims 3 and substantially claim 19, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1 or non-transitory computer-readable medium of claim 17, wherein the software is to indicate to the cryptographic logic circuitry whether to drop one or more transactions to be received after the two or more incoming packets (Noehring [0029]) or to process the two or more incoming packets out-of- order and continue to process the one or more transactions (Chhabra [0067]: receive interleaved packets of different sizes, hence the method to break up packets to be the same size for processing (see claim 1)).
Regarding claims 4 and substantially claim 20, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1 or non-transitory computer-readable medium of claim 17, the cryptographic logic circuitry is to receive the two or more incoming packets out-of-order transactions (Chhabra [0067]: receive interleaved packets of different sizes, hence the method to break up packets to be the same size for processing (see claim 1)).
Regarding claim 5, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to notify the software after a first granularity of encrypted or decrypted transaction size has been reached in response to a request by the software to be notified after reaching the first granularity (Noehring [0017], Chhabra [0058]: 64 bit of GCM granularity to process the packets, see claim 1 for motivation to combine with Noehring).
Regarding claim 6, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the two or more incoming packets are fragmented or unaligned for Advanced Encryption Standard (AES) encryption or AES decryption (Noehring [0035]).
Regarding claim 7, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the two or more incoming packets are each to have a lower size than 16 bytes (Noehring [0030]: packets size 64-bits or 8 bytes).
Regarding claim 8, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, the plurality of incoming packets have a size to be determined at boot time or design time (Noehring [0032]: use of a 32-bits processor, per design or Chhabra [0064]: use of 64B block size).
Regarding claim 9, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein at least one of the plurality of incoming packets is 16 bytes (Chhabra [0127][0128]: packets between 0 -M bytes, where M =1024).
Regarding claim 10, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to encrypt or decrypt the two or more incoming packets (Noehring [0019][0035]).
Regarding claim 11, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to encrypt or decrypt the two or more incoming packets in accordance with Advanced Encryption Standard (AES) (Noehring [0035]).
Regarding claim 13, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the memory comprises one or more of SRAM (Static Random Access Memory), MRAM (Magnetoresistive Random Access Memory), and DRAM (Dynamic Random Access Memory (Chhabra [0097]).
Regarding claim 14, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to store a transaction identifier corresponding to the two or more incoming packets in a buffer (Noehring [0022], fig. 2, IFIFO 204: header identifying protocol to se to process packets).
Regarding claim 15, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the memory comprises the buffer (Noehring fig. 2, IFIFO 204).
Regarding claim 16, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the cryptographic logic circuitry is to notify the software after encrypting or decrypting the two or more incoming packets (Desai [0042]: encrypt data and pass to OS).
Regarding claim 21, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, wherein the software is an operating system (Desai, [0051], see claim 1 for motivation to combine).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Noehring, in view of Chhabra and Desai, and further in view of Zhang, et al. "Ensuring data confidentiality with a secure XTS-AES design in flash translation layer." 2020 IEEE, pages 289-294, hereinafter Zhang.
Regarding claim 12, Noehring in view of Chhabra and Desai discloses the apparatus of claim 1, but fails to explicitly teach the cryptographic logic circuitry is to encrypt or decrypt the two or more incoming packets in accordance with Advanced Encryption Standard (AES) in XEX-based Tweakable-codebook mode with ciphertext Stealing (XTS) mode.
However using (AES) in XEX-based Tweakable-codebook mode with ciphertext Stealing (XTS) mode is known in the art, as evidenced by Zhang. Zhang discloses using XTS-AES with ciphertext stealing when the sector size is not divisible by the bock size and separately encrypting plaintext blocks with a tweakable block cipher (p.290, under II, A). It would have been obvious to a skilled artisan before the instant application was filed to apply AES as claimed and as taught by Zhang because it would use a fixed-length encryption that enables XTS to be embedded in the existing storage system easily without modifying the structure of any system (Zhang p.290, in II, A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Minemura et al 20140201776 discloses combining packet payload before encryption.
Choudhury et al 20070255947 disclose aligning block size to the expected block size before calculating a MAC.
Fetkovich et al 7151832 disclose a dynamic varying of encrypting of a stream of data at an encryption unit based on data content is disclosed.
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CATHERINE B. THIAW
Supervisory Patent Examiner
Art Unit 2407
/Catherine Thiaw/Supervisory Patent Examiner, Art Unit 2407 11/15/2025