DETAILED ACTION
This action is in response to the claims filed on 05/23/2025. Claims 1-25 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 5, 13, 19, 24 have been cancelled.
Claims 1-4, 6-12, 14-18, 20-23, and 25 are rejected under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 10-25 are rejected under 35 U.S.C. 103 as being unpatentable over Bhattacharjee et al. (U.S. PGPUB No. 20120151267) in view of Broderick et al. (U.S. PGPUB No. 20170004063), further in view of Maiyuran et al. (U.S. PGPUB No. 20190362460), further in view of Kapustin et al. (U.S. PGPub No. 20070226473).
Regarding Claim 1, Bhattacharjee teaches,
and hardware circuitry coupled to the processing resources, the hardware circuitry comprising: a watchpoint register programmed with a value of a watchpoint address ("the watchpoint identifies a portion of memory to be watched" [0012]), the watchpoint address comprising an address of a memory location in the processor (“The computer system hardware includes a processor50 and a memory system60” [0020]; the memory system (60) is interpreted as a component of the processor as shown in Bhattacharjee [FIG. 1]);;
and sequencer hardware circuitry to (“hardware trap” [0015]): determine, using the watchpoint register, whether a memory access request received from a thread of the plurality of threads is requesting access to the watchpoint address ("debugger40 implements the watchpoint by sending a ptrace system call [which includes] the relevant read-trap or write-trap (or both), including the watchpoint address" [0021]);
and responsive to the memory access request requesting the access to the watchpoint address, return an exception payload to the thread, the exception payload comprising watchpoint details corresponding to the watchpoint address and a scoreboard identifier (SBID) associated with the memory access request (“after completion of the read or write operation, sending an exception signal that indicates that the read or write operation occurred on the watched portion of memory” [0019])
and wherein the exception payload is returned in response to the memory access request requesting the access to the watchpoint address using the access type indicated in the access type field of the watchpoint register (“after completion of the read or write operation, sending an exception signal that indicates that the read or write operation occurred on the watched portion of memory” [0019]).
Bhattacharjee does not appear to disclose and Broderick teaches,
A processor comprising: processing resources to perform graphics operations using a plurality of threads ("[a processor] may be configured to execute multiple thread" [0108]; the processor may comprise dedicated graphics processing resources [0112])
wherein the access type of the operation comprises at least one of store, load, or atomic, (The watchpoint is configured to either: detect a modification (write access) or compare to a predetermined target (read access) [0064]; the watchpoint is configured accordingly [0064]).
It would have been obvious to someone of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Bhattacharjee’s teaching of watchpoints with read/write traps and exception signals to incorporate the teachings of Broderick to include processing resources to perform graphics operations using a plurality of threads to assist the debugging process of increasingly complex computer processors (Bhattacharjee, [0002]), including graphics processors and incorporate access type to send the user the appropriate output regarding the exception (Bhattacharjee, [0006]).
Bhattacharjee in view of Broderick does not appear to disclose and Maiyuran teaches,
wherein the SBID comprises a hardware data structure that logs and observes data dependencies of the memory access request in the processing resources (a hardware-specific identifier for SBID dependencies [0158]; with hardware scoreboard bits [0149]; where the dependency of instructions is logged [0209]; where the read operations and associated dependencies are corresponded to the SBID [0188])
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combined teaching of watchpoints with read/write traps and exception signals and processing resources to perform graphics operations using a plurality of threads of Bhattacharjee in view of Broderick with the SBID dependencies of Maiyuran. The resulting combination allows for dependency handling in GPUs to be simplified with hardware dependency handling [Maiyuran; 0030].
Bhattacharjee in view of Broderick, further in view of Maiyuran, disclose a watchpoint register comprising the watchpoint address [Bhattacharjee; 0012], but do not appear to disclose and Kapustin teaches,
wherein the watchpoint register further comprises an access type field to indicate an access type of an operation that accesses the watchpoint address (where there exists debug registers (30) as watchpoints [0040]; where the register access watchpoint system may be combined in a system relating to memory access [0016]; the register watchpoint may comprise an access type field (54) specifying triggering reads and/or writes ("indicate an access type of an operation...") [0040-0041]),
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combined teaching of watchpoints with read/write traps and exception signals with processing resources to perform graphics operations on a plurality of threads as taught by Bhattacharjee in view of Broderick, further in view of Maiyuran, to include the watchpoint comprising a field with the access type as taught by Kapustin. The resulting combination provides a strong diagnostic and analytical merit by triggering a breakpoint in response to an access to a register (or memory, [Kapustin; 0016]), and further provides breakpoint circuitry responsive to actual memory accesses regardless of interrupt or aborts [Kapustin, 0011].
Regarding Claim 2, Bhattacharjee teaches
The processor of claim 1, wherein the SBID is to track when registers used in the memory access request are available to use (the system includes "computer usable program code for allowing a read or write operation on the watched portion of memory” [0019])
and is to relate the watchpoint address back to the thread and instruction issuing the memory access request (the system includes “sending an exception signal that indicates that the read or write operation occurred on the watched portion of memory” [0019]; where “the exception signal is sent to a thread that caused the exception” [0017]).
Regarding Claim 3, Bhattacharjee teaches
The processor of claim 1, wherein the watchpoint address is provided by a debugging application ("debugger" (40)) to a debug surface corresponding to the processor ("The debugger40 may then notify the user that a read or write has occurred within the watchpoint address range” [0024]).
Regarding Claim 4, Bhattacharjee teaches
The processor of claim 3, wherein an exception handling routine of the processor reads the watchpoint address from the debug surface and causes the watchpoint address to be stored to the watchpoint register ("The user10 may input watchpoint address to the debugger40, which stores the watchpoint in a data address breakpoint register42” [0021]).
Regarding Claim 6, Bhattacharjee teaches
The processor of claim 1, wherein the hardware circuitry is further to return a data payload in response to the memory access request ("the thread will enter a trap handler in response to a read or a write operation occurring on a page that includes the watchpoint, but will allow the read or write operation to proceed" [0015]; for a memory access request, the data payload is returned).
Regarding Claim 7, Bhattacharjee teaches
The processor of claim 1, wherein,…, the thread is to jump to an exception handling routine of the processor (The thread will enter a trap handler in response to a read/write operation on watchpoint addresses [0015]), the exception handling routine is to read the watchpoint details from a debug register corresponding to the thread, store the watchpoint details to a debug surface corresponding to the processor ("the trap handler gives control to the debugger [...] The debugger may prompt a user for instructions" [0015]), and notify a debugger application via an interrupt process (User is prompted for instruction [0015]).
Bhattacharjee teaches the thread jumping to an exception handling routine responsive to either a read or write trap [0011], but does not appear to disclose and Broderick teaches
The processor of claim 1, wherein, responsive to receiving the exception payload (“The program trace information may comprise information relating program flow discontinuities (information about direct and indirect branches, exceptions etc.), which enables an external debugger to interpolate what sequence of events occurred between such discontinuities” [0049]), the thread is to jump to an exception handling routine of the processor …
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the exception handling routine of Bhattacharjee with the exception payload of Broderick to yield the predictable result of a combined processor that receives an exception payload and performs an exception handling routine to identify when a debugging routine should be applied (Bhattacharjee, [0006]).
Regarding Claim 8, in the combination of Bhattacharjee and Broderick above, Broderick teaches,
The processor of claim 1, wherein the processor comprises a graphics processing unit (GPU) ("The data processing system 600 may further comprise a dedicated graphics sub-system 615 [...] The graphics sub-system 615 may include one or more processing cores for supporting hardware accelerated graphics generation" [0112]).
Claims 10-12 and 14-15 recite a shift in statutory category and are rejected under the same grounds of rejection as Claims 1-4 and 6-7, above.
Claims 16-18 and 20 recite a shift in statutory category and are rejected under the same grounds of rejection as Claims 1-4 and 7, above.
Claims 21-23 and 25 recite a shift in statutory category and are rejected under the same grounds of rejection as Claims 1-4 and 7, above.
Claim 9 is rejected under 35 USC § 103 as being unpatentable over Bhattacharjee et al. (U.S. PGPUB 20120151267), herein referred to as Bhattacharjee, in view of Broderick et al. (U.S. PGPUB 20170004063), herein referred to as Broderick, further in view of Maiyuran et al. (U.S. PGPUB No. 20190362460) and Kapustin et al. (U.S. PGPub No. 20070226473), and further in view of Perley (U.S. PGPUB 20210173004).
Regarding Claim 9, Bhattacharjee in view of Broderick and further in view of Maiyuran and Kapustin do not appear to disclose and Perley teaches
The processor of claim 1, wherein the processor is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine (“processing system 500 includes one or more application specific cores, such as a GPU, another type of single-instruction-multiple-data (SIMD) core…” [0036]; where the processing system 500 further contains components for tracking state information and debugging [0033]).
It would have been obvious to someone of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify the combination of the watchpoint register system of Bhattacharjee as applied to a GPU as taught by Broderick including the hardware SBID of Maiyuran to include the SMID-based GPU watch trigger mechanisms of Perley. The resulting combination allows for an enhanced watchpoint/trigger mechanism for an unspecified type of processor (Bhattacharjee [0018]) to be extended to the SMID GPU environment (Perley [0036]) and allows for additional options and environments for “additional options for performing profiling, device debugging, validation coverage, or production workarounds” (Pearly [0008]).
Response to Arguments
Applicant’s remarks filed 11/12/2025 have been fully considered.
Applicant’s arguments with respect to the previous rejection under 35 U.S.C. 103 on independent Claim 1, and similarly Claims 10, 16, and 21, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
Reid et al. (U.S. PGPub No. 20100077143) teaches a data processing apparatus for monitoring accesses to a plurality of addressable locations [Abstract].
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.E.W./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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