DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to amendment filed on 11/07/2025. Claims 1-20 are pending. The amendment has overcome the drawing objection, claim objections, and rejection under 35 U.S.C. for claim 17 as set forth in previous office action.
Response to Arguments
Applicant asserted on page 11, “Applicant has amended claim 16 to clarify to which mode each plurality of values is associated with.”
Examiner respectfully disagrees because claim 16 has not been amended to address the 112(b) rejection as rejected in previous office action. Thus, such rejection for claim 16 remains outstanding.
In respond to Applicant’s argument regarding rejection under 35 U.S.C. 103 on page 12, “In sharp contrast, Elmer and Olson do not appear to teach or suggest a tensor mode and a DSP mode, as recited in the claims. Indeed, both Elmer and Olson appear to be silent with respect to at least a tensor mode.”
Examiner respectfully disagrees because merely reciting tensor mode and DSP mode in the claim is insufficient to distinguish over the art since the terms tensor and DSP are merely used as labels for two operating modes configuration, not as limitations that tie the claim to any particular hardware, algorithms, or applications. Thus, under broadest reasonable interpretation, tensor mode and DSP mode encompass any two distinct arithmetic operating configuration mode that can be mapped to the claim language, for example, integer mode and floating point mode of Elmer would be mapped to the tensor mode and DSP mode, respectively because as illustrated in Elmer figure 1, the array operates on matrices data [i.e., tensor] and the array processes digital data [i.e. DSP] for audio processing [0048].
In respond to Applicant’s request for rejoinder and allowance of claims 1-11 on page 14 of Remarks, “Applicant respectfully requests rejoinder and allowance of claims 1-11. Independent claim 1 recites, among other things, "a plurality of multipliers, wherein: in a tensor mode of operation and in a DSP mode of operation (Emphases added.) As mentioned above, at least these elements are believed to be allowable over the cited art. Accordingly, Applicant respectfully requests rejoinder and allowance of claims 1-11.”
Examiner respectfully disagrees because the elements amended are not allowable over the cited art. See rejection below for details.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14-16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 line 3 recites “the first value of the first plurality of values associated with the DSP mode”. There is lack of antecedent basis for such limitation of “the first value”. For examination purposes, Examiner interprets as “a first value of the first plurality of values associated with the DSP mode”.
Claim 16 line 2 and 3 recites "the first plurality of values". It is unclear whether "the first plurality of values" is referring to the first plurality of values as recited in the tensor mode of operation in claim 12 line 6 or the first plurality of values as recited in the DSP mode of operation in claim 12 line 17. For examination purposes, Examiner interprets "the first plurality of values" as the first plurality of values associated with the DSP mode.
Dependent claim 15 is also rejected for inheriting the same deficiencies in which claim it depends on.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Elmer – US 20210157549 in view of Olson – US 20100325188.
Regarding claim 12, Elmer teaches a digital signal processing (DSP) block (Elmer figure 1 illustrates an processing element array 100 that process digital data signal such integer or floating point [i.e., a digital signal processing (DSP) block] for signal application, such as audio processing [0048]) comprising: a plurality of columns of weight registers, wherein one or more of the plurality of columns of weight registers is configurable to receive values (Elmer figure 2A illustrates [0049] implementation of a PE, having a weight register 220, wherein figure 1 illustrates an array of 4x4 PE, thus at least 4 columns of registers 220 [i.e., a plurality of columns of weight registers receive weight values [i.e., values]); and adder circuitry, and a plurality of multipliers (Elmer, figure 2A illustrates adder 210 [i.e., adder circuitry], and a plurality of multipliers 208 [i.e., a plurality of multipliers]), wherein:
in a tensor mode of operation (Elmer, [0064] figure 2A or figure 10A describes 2 modes of operations, integer operation mode or floating point operation mode, wherein integer operation mode corresponds to a tensor mode of operation as array of PE processes matrices of data [i.e., tensor] ):
a first plurality of values associated with the tensor mode is stored in the plurality of columns of weight registers after being received (Elmer, the weight registers 220 in the 4x4 array PEs [i.e., the plurality of columns of weight registers] stores the weight values [i.e., a first plurality of values associated with the tensor mode]); after storing the first plurality of values associated with the tensor mode in the plurality of columns of weight registers, the plurality of multipliers is configurable to simultaneously multiply each value of the first plurality of values associated with the tensor mode by a value of a second plurality of values associated with the tensor mode to generate a first plurality of products associated with the tensor mode (Elmer, after storing the weight values, multipliers 208 in the 4x4 array performs multiplication. [0046] the multipliers 208 in each column operate arithmetic operation on each value of the weights and an input value of the input values stored in registers 204 [i.e., a value of a second plurality of values] to generate integer products 250 [i.e., a first plurality of products]);
the adder circuitry is configurable to receive the first plurality of products associated with the tensor mode and generate a first sum by adding the first plurality of products associated with the tensor mode without shifting any products of the first plurality of products (Elmer, the adders 210 of the 4x4 array [i.e., the adder circuitry] is configures to receive the products 250 generated from the multipliers 208 [i.e., the first plurality of products] to generate a first sum without shifting any products); and
in a DSP mode of operation (Elmer [0064] floating point operation mode, figure 1 illustrates an processing element array 100 that process digital data signal. Thus, the floating point operation mode corresponds to a DSP mode of operation):
a first portion of multipliers of the plurality of multipliers (Elmer, figure 10A illustrates the shared multiplier 208 as implemented in figure 2A, having a floating point multiplier 1004. Thus, the floating point multipliers 1004 in the 4x4 array corresponds to a first portion of multipliers of the plurality of multipliers) is configurable to multiply each of a first plurality of values associated with the DSP mode by each value of a second plurality of values associated with the DSP mode to generate a second plurality of products associated with the DSP mode (Elmer figures 1, 2A, and 10A [0066] illustrates the floating point sub multipliers 1004 multiply each floating point input data 244 [i.e., each value of a second plurality of values] by each floating point weight data 246 [i.e., each of a first plurality of values] to generate floating point products 251 [i.e., a second plurality of products]);
shifter is configurable to receive the second plurality of products associated with the DSP mode and generate a shifted plurality of products by shifting at least one of the second plurality of products associated with the DSP mode (Elmer [0077] describes floating point adder subcircuits 1014 include shifting the significand to align exponents. Thus, the subcircuits 1014 includes shifter configured to receive floating point products 251 and perform shifting the significand to align with exponent, which generate a shifted floating point products [i.e., a shifted plurality of product] by shifting the products 251); and
the adder circuitry is configurable to receive the shifted plurality of products associated with the DSP mode and generate a second sum by adding the shifted plurality of products associated with the DSP mode (Elmer [0077] describes the adders 210 [i.e., the adder circuitry] include floating point adder subcircuits 1014 perform binary addition on the aligned significant to determine floating point partial sum. Thus, the adder receives shifted/aligned products and generate a second sum by adding the aligned products).
While Elmer discloses shifting circuit [i.e., shifter] to receive the products and generate shifted products (Elmer [0077]). However, Elmer does not teach such shifting circuit being a multiplexer network. Olson teaches multiplexer network configured to receive data and generate shifted data (Olson figure 4 [0088] describes a pair of shift muxes 450 (or multiplexers) to receive data from CSA 430 and [0096] describes the shift mux perform bit shifting according to control signal)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to substitute the shifter circuit to perform alignment as disclosed in Elmer with the shift mux as disclosed in Olson. This modification would have been obvious because both references disclose operation of bit shifting, and Elmer merely disclose a circuit to perform shifting and is silenced regarding the implementation of the shifter. Furthermore, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art. See MPEP 2141(III)(B) Simple substitution of one known element for another to obtain predictable results.
Regarding claim 14, the combined system of Elmer in view of Olson teaches the DSP block of claim 12, in the DSP mode of operation, at least two multipliers of the first portion of multipliers of the plurality of multipliers receive the first value of the first plurality of values associated with the DSP mode and perform a multiplication operation involving the first value (Elmer, [0117] describes the same weight value [i.e., a first value] may be used by all PEs in a given row [i.e., at least two multipliers of the first portion of multipliers of the plurality of multipliers] for convolving [i.e., a multiplication operation] with each input data for input data set to optimize memory bandwidth).
Regarding claim 16, the combined system of Elmer in view of Olson teaches the DSP block of claim 12, wherein: each of the first plurality of values has a first precision; the first plurality of values is generated from a first value having a second precision that is greater than the first precision (Elmer, [0051] describes each weight 224 [i.e., each of the first plurality of values] each may include 8 bit, 9 bit, 16 bits. [0023, 0025] describes longer input bits, such as 64 bit or 32 bit result in greater amount of memory and communication bandwidth, thus is quantized to lower bit (e.g., 16 bit or 8 bit). Figure 3 [0101] describes signal modifier 309 for quantizing weights. Thus, the lower quantized precision (16 bit or 8 bit) of weights corresponds to first precision of the first plurality of values and the higher unquantized precision (e.g., 64 bit or 32 bit) corresponds to a second precision that is greater than the first precision).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Elmer in view of Olson as applied to claim 12 above, and further in view of Li – US 20210326118
Regarding claim 13, the combined system of Elmer in view of Olson teaches the DSP block of claim 12, in the tensor mode of operation (Elmer [0064] figure 2A or figure 10A describes 2 modes of operations, integer operation mode or floating point operation mode, wherein integer operation mode corresponds to the tensor mode of operation). However, the combined system of Elmer in view of Olson does not teach the first plurality of values have a shared exponent value. Li discloses a system that operates in different modes, wherein in a first mode of operation, a first plurality of values have a shared exponent value (Li discloses figure 4 illustrates a module [i.e., a system] that operates in fixed-point mode [i.e., a first mode of operation] and floating point mode. [0004] describes a chip for neural network model calculation is used as example. Two types of multiply accumulate modules coexist on the chip: a first type of the multiply accumulate module for a fixed-point operation (also referred to as an integer operation), and a second type of the multiply accumulate module for a floating-point operation. Figure 5 illustrates implementation for fixed point operation having multipliers and adders operate on a plurality of values, wherein [0042] described that fixed-point number is a representation where the decimal point positions of all data are fixed. Binary fixed-point value has the representation as integer x scaling factor (e.g.,
2
-
F
)
, where F represents the fractional number [i.e., exponent value]. Thus, for arithmetic operation addition to generate correct values, the F value for all operands is the same [i.e., shared]. Also see instant specification [0032] describes that fixed point data have shared common exponent).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention modify the PEs of the combined system of Elmer in view of Olson that operate on integer data type and floating point data type to operate on fixed point data type and floating point data type as disclosed in Li. This modification would have been obvious because the references includes multiply and accumulate operation for neural network models. Furthermore, Elmer [0050-0051] describes that PE may operate on integer data, floating point data, and any other suitable data type, wherein Li [0004] describes that fixed-point data operation is also referred as integer operation (e.g., other suitable data type). Moreover, operating fixed point data type provides better precision than integer since fixed point data also represent fractional number.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Elmer in view of Olson as applied to claim 14 above, and further in view of Koren - US 20190042538.
Regarding claim 15, the combined system of Elmer in view of Olson teaches the DSP block of claim 14, comprising: a register configurable to store the first value (Elmer, figure 2A figure 4 illustrate register 406 to store the weight value [i.e., the first value]). However, the combined system of Elmer in view of Olson does not teach a second multiplexer network configurable to route the first value to the at least two multipliers. Koren teaches a multiplexer network configurable to route a first value to multiplier (Koren figure 2 illustrates multiplexers 240 and 245 [i.e., a multiplexer network] configured to route data 210 [i.e., a first value] to multiplier 230 according to dense mode and sparsity mode operations [0026], wherein dense mode is to perform MAC operation without eliminating zeros and sparsity mode is to perform MAC operation with zero elimination on the data sets (e.g., weight and input data). also see [0036-0040] for operating two modes)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the PEs of the combined system of Elmer in view of Olson to having multiplexer to route data according to two different mode (e.g., dense and sparsity mode) as disclosed in Koren. This modification would have been obvious because the references disclose neural network operation using zero skipping scheme, and as recognized by Koren, [0020] neural network include a dense layer, where the layer contains either all or nearly all non-zero elements. Thus, modifying the PEs of the combined system of Elmer in view of Olson to not perform zero detecting in dense layer mode would reduce the operations of detecting zeros in the data. Furthermore, as disclosed in figure 2 and described in [0040], having multiplexer network to select data from memory device 250 or 255 in second mode (e.g., sparsity mode), wherein the data has been compressed to eliminate zero data. Thus, only non-zero data are fed into the PEs, whereas the combined system Elmer in view of Olson figure 2A illustrates weight value is preloaded into weight register before performing zero detecting. Accordingly, having multiplexer network to select nonzero data before storing in the register also decreases the load operation since only non-zero data are loaded into register.
As modified, the combined system of Elmer in view of Olson and Koren a second multiplexer network configurable to route the first value to the at least two multipliers (as modified, multiplexer 245 of Koren selects weight data [i.e., route the first value] according to mode operations, and the weight data are being passed to at least two multiplier in the same row as explained in [0117] of Elmer)
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Elmer – US 20210157549 in view of Koren
Regarding claim 17, Elmer teaches an integrated circuit device (Elmer figure 6 illustrates a neural network processor 602 implemented as FPGA [i.e., an integrated circuit device) comprising a digital signal processing (DSP) block (Elmer [0146] discloses the processor 602 includes systolic array 302, wherein [0099] describes array 302 is similar to array 100 in figure 1, which illustrates an processing element array 100 that process digital data signal such integer or floating point [i.e., a digital signal processing (DSP) block] for signal application, such as audio processing [0048]), the DSP block comprising:
a plurality of columns of weight registers, wherein one or more of the plurality of columns of weight registers is configurable to receive values (Elmer figure 2A illustrates [0049] implementation of a PE, having a weight register 220, wherein figure 1 illustrates an array of 4x4 PE, thus at least 4 columns of registers 220 [i.e., a plurality of columns of weight registers receive weight values [i.e., values]); and a multiplexer network, adder circuitry, and a plurality of multipliers (Elmer, figure 2A illustrates multiplexers 213 215 [i.e., a multiplexer network], adder 210 [i.e., adder circuitry], and a plurality of multipliers 208 [i.e., a plurality of multipliers]), wherein:
in a tensor mode of operation (Elmer, [0064] figure 2A or figure 10A describes 2 modes of operations, integer operation mode or floating point operation mode, wherein integer operation mode corresponds to a first mode of operation as array of PE processes matrices of data [i.e., tensor]); and
a first plurality of values associated with the tensor mode is stored in the plurality of columns of weight registers after being received (Elmer, the weight registers 220 in the 4x4 array PEs [i.e., the plurality of columns of weight registers] stores the weight values [i.e., a first plurality of values associated with the tensor mode]); after storing the first plurality of values associated with the tensor mode in the plurality of columns of weight registers, the plurality of multipliers is configurable to simultaneously multiply each value of the first plurality of values associated with the tensor mode by a value of a second plurality of values associated with the tensor mode to generate a first plurality of products (Elmer, after storing the weight values, multipliers 208 in the 4x4 array performs multiplication. [0046] the multipliers 408 in each column operate arithmetic operation on each value of the weights and an input value of the input values stored in registers 204 [i.e., a value of a second plurality of values] to generate integer products 250 [i.e., a first plurality of products]);
the adder circuitry is configurable to receive the first plurality of products and generate a first sum by adding the first plurality of products without shifting any products of the first plurality of products (Elmer, the adders 210 of the 4x4 array [i.e., the adder circuitry] is configures to receive the products 250 generated from the multipliers 208 [i.e., the first plurality of products] to generate a first sum without shifting any products); and
in a DSP mode of operation (Elmer [0064] floating point operation mode, figure 1 illustrates an processing element array 100 that process digital data signal. Thus, the floating point operation mode corresponds to a DSP mode of operation):
a respective first value of the first plurality of values associated with the DSP mode and respective second value of the second plurality of values associated with the DSP mode are input to each respective multiplier of a first portion of the plurality of multipliers (Elmer figure 10A illustrates the shared multiplier 208 as implemented in figure 2A, having a floating point multiplier 1004. Thus, the floating point multipliers 1004 in the 4x4 array corresponds to a first portion of multipliers of the plurality of multipliers and also illustrates a weight [i.e., a respective first value] and an input data are input to each floating point multiplier 1004 [i.e., each respective multiplier]); the first portion of the plurality of multipliers is configurable to multiply each of the first plurality of values associated with the DSP mode by each value of the second plurality of values associated with the DSP mode to generate a second plurality of products (Elmer figures 1, 2A, and 10 illustrate array of floating point number multipliers 1004 [i.e., the first portion of the plurality of multipliers] is configured to multiply each weight [i.e., each of the first plurality of values] by each input data [i.e., each of the second plurality of values] to generate products 251); and
the adder circuitry is configurable to generate a second sum based on the second plurality of products (Elmer, figure 1 and figure 2A illustrate adders 210 [i.e., the adder circuitry] configured to generate a second sum based on the products 251).
Elmer does not teach the multiplexer network configurable to receive a first plurality of values associated with the DSP mode and a second plurality of values associated with the DSP mode and route a respectively first value of the first plurality of values associated with the DSP mode and respective second value of the second plurality of values associated with the DSP mode to each respective multiplier. However, Koren teaches a multiplexer network configurable to receive a first plurality of values and a second plurality of values and route a respectively first value of the first plurality of values and respective second value of the second plurality of values to each respective multiplier (Koren figure 2 illustrates multiplexers 240 and 245 [i.e., a multiplexer network] configured to receive data from 210, 220, 245, and 255 [i.e., a first plurality of values and second plurality of values] and route each data to respective multiplier 230 according to dense mode and sparsity mode operations [0026], wherein dense mode is to perform MAC operation without eliminating zeros and sparsity mode is to perform MAC operation with zero elimination on the data sets (e.g., weight and input data). also see [0036-0040] for operating two modes)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the PEs of Elmer to having multiplexer to route data according to two different mode (e.g., dense and sparsity mode) as disclosed in Koren. This modification would have been obvious because the references disclose neural network operation using zero skipping scheme, and as recognized by Koren, [0020] neural network include a dense layer, where the layer contains either all or nearly all non-zero elements. Thus, modifying the PEs of Elmer to not perform zero detecting in dense layer mode would reduce the operations of detecting zeros in the data. Furthermore, as disclosed in figure 2 and described in [0040], having multiplexer network to select data from memory device 250 or 255 in second mode (e.g., sparsity mode), wherein the data has been compressed to eliminate zero data. Thus, only non-zero data are fed into the PEs, whereas the combined system Elmer in view of Olson figure 2A illustrates weight value is preloaded into weight register before performing zero detecting. Accordingly, having multiplexer network to select nonzero data before storing in the register also decreases the load operation since only non-zero data are loaded into register.
Regarding claim 20, the combined system of Elmer in view of Koren teaches the integrated circuit device of claim 17, wherein the integrated circuit device comprises a field-programmable gate array (FPGA) (Elmer figure 6 [0138] describes a neural network processor 602 implemented as FPGA [i.e., an integrated circuit device).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Elmer in view of Koren as applied to claim 17 above, and further in view of Olson.
Regarding claim 18, the combined system of Elmer in view of Koren teaches the integrated circuit device of claim 17, comprising shifting circuit configurable to receive the second plurality of products and generate a shifted plurality of products by shifting at least one of the second plurality of products (Elmer [0077] describes floating point adder subcircuits 1014 include shifting the significand to align exponents. Thus, the subcircuits 1014 includes shifting circuit configured to receive floating point products 251 and perform shifting the significand to align with exponent, which generate a shifted floating point products [i.e., a shifted plurality of product] by shifting the products 251), wherein the adder circuitry is configurable to generate the second sum by adding the shifted plurality of products (Elmer [0077] describes the adders 210 [i.e., the adder circuitry] include floating point adder subcircuits 1014 perform binary addition on the aligned significant to determine floating point partial sum. Thus, the adder receives shifted/aligned products and generate the second sum by adding the aligned/shifted products).
While the combined system of Elmer in view of Koren discloses shifting circuit to receive the products and generate shifted products (Elmer [0077]). However, the combined system of Elmer in view of Koren does not teach such shifting circuit being a second multiplexer network. Olson teaches multiplexer network configured to receive data and generate shifted data (Olson figure 4 [0088] describes a pair of shift muxes 450 (or multiplexers) to receive data from CSA 430 and [0096] describes the shift mux perform bit shifting according to control signal)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to substitute the shifter circuit to perform alignment as disclosed in the combined system of Elmer in view of Koren with the shift mux as disclosed in Olson. This modification would have been obvious because both references disclose operation of bit shifting, and Elmer merely disclose a circuit to perform shifting and is silenced regarding the implementation of the shifter. Furthermore, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art. See MPEP 2141(III)(B) Simple substitution of one known element for another to obtain predictable results.
Regarding claim 19, the combined system of Elmer in view of Koren and Olson teaches the integrated circuit device of claim 18, wherein, in the tensor mode of operation, the adder circuitry is configured to generate the first sum without shifting any products of the first plurality of products (Elmer, in integer mode operation [i.e., tensor mode of operation] the adders 210 of the 4x4 array [i.e., the adder circuitry] is configures to receive the products 250 generated from the multipliers 208 [i.e., the first plurality of products] to generate a first sum without shifting any products).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182