Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is an AIA application filed June 25, 2021.
The earliest effective filing date of this AIA application is seen as June 25, 2021, the actual filing date, there being no earlier priority applications.
The present application is also related to the applications giving rise to the following patent publication(s):
Office
Application
App. Date
Pub. #
Pub. Date
EP
22164406
03/25/2022
EP 4116752 A1
01/11/2023
CN
202210579449
05/25/2022
CN 115598774 A
01/13/2023
The claims filed July 20, 2026 are entered, currently outstanding, and subject to examination.
This action is in response to the request for continued examination/RCE filing of the same date.
The current status and history of the claims are summarized below:
Last Amendment/Response
Previously
Amended:
1, 2, 4-7, & 13
1, 2, & 4-14
Cancelled:
3
15-26
Withdrawn:
none
none
Added:
none
21-26
Claims 1, 2, and 4-14 are currently pending and outstanding.
Regarding the last reply:
Claims 1, 2, 4-7, 13, and 14 were amended.
Claim 3 was cancelled.
No claims were withdrawn.
No claims were added.
Claims 1, 2, and 4-14 are currently outstanding and subject to examination.
This is a non-final action and is the fifth action on the merits.
Allowable subject matter is not indicated below.
Often, in the substance of the action below, formal matters are addressed first, claim rejections second, and any response to arguments third.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 20, 2026 has been entered.
Special Definitions for Claim Language - MPEP § 2111.01(IV)
No special definitions are seen as present in the specification regarding the language used in the claims. Consequently, the words and phrases of the claims are given their plain meaning. MPEP §§ 2173.01, 2173.05(a), and 2111.01.
If special definitions are present, Applicant should bring those to the attention of the examiner and the prosecution history with its next response in a manner both specific and particular. In doing so, there will be no mistake, confusion, and/or ambiguity as to what constitutes the special definition(s).
To date, Applicant has provided no indication of special definitions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, and 4-14 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Application Publication No. 20060159387 of Handelman (Handelman, cited by Applicant).
With respect to claim 1, Handelman discloses an integrated circuit (IC) package (Fig. 1, ¶ 107 et seq., PIC device 10), comprising:
a configurable optical switch (¶ 110, "The embedded optical interconnect mesh 20 preferably includes a plurality of optical paths 65, a reflecting optical element 70, and a bi-directional coupler 80". ¶ 137, "Multicast to only some of the OE nodes may be obtained by broadcasting information with addresses of only some of the OE nodes. Although all the OE nodes receive the information, only OE nodes having one of the broadcasted addresses process the information and all other OE nodes ignore the information. Unicast may similarly be obtained by broadcasting information with an address of only one OE node.” The foregoing is seen as teaching addressable switching. Reconfiguration is disclosed in ¶ 141 where, "[f]or example, if initially the PIC device 10 is configured in the star network architecture, the PIC device 10 may later be reconfigured, for example in response to an instruction entered by an operator of the control and management system 190, from the star network architecture to the bus/broadcast network architecture or to the ring network architecture. Such reconfiguration is performed, for example, by changing operation modes of the optical transceivers 30 to correspond to the reconfigured network architecture.") having
a first interface (the lower half portion of bi-directional coupler 80 coupled to the optical paths 65 leading to ports 160, 170, 240, and 250) and
a second interface (the upper half portion of bi-directional coupler 80 the optical paths 65 leading to the connections/ports of interface unit 130),
the first interface (lower half 80) having a first plurality of intra-package optical ports (per above and Fig. 1),
the second interface (upper half 80) having a second plurality of intra-package optical ports (per above and Fig. 1);
a plurality of optical transceivers (¶ 108, "set of optical transceivers 30");
a plurality of intra-package optical fibers (¶ 41, fiber interconnect mesh) between the second interface of the configurable optical switch (upper part of bi-directional coupler 80) and the plurality of optical transceivers (30);
an optical connector (¶ 121, "link adder 140 is preferably operative to associate an external optical unit 150 with the optical interconnect mesh 20") comprising a plurality of exo-package optical ports (¶ 121, "ports 160 and 170 in the link adder 140") for connecting a plurality of external optical interconnects (220 and 230) to the IC package (10),
the plurality of exo-package optical ports (160, 170, 240, 250) operably coupled to the first interface (lower portion) of the configurable optical switch (80);
and an IC die comprising electronic circuitry (¶ 119, interface unit 130, "The interface unit 130 may, for example, include LSI electronic circuit components (not shown) interfacing the subsystems of the electronic chip and the electronic chips with the optical transceivers 30.") operably coupled to the plurality of optical transceivers (30);
wherein the configurable optical switch includes electronic logic circuitry (190) to receive configuration information to map the plurality of individual external optical interconnects to the plurality of individual intra-package optical fibers (¶ 141, "For example, if initially the PIC device 10 is configured in the star network architecture, the PIC device 10 may later be reconfigured, for example in response to an instruction entered by an operator of the control and management system 190, from the star network architecture to the bus/broadcast network architecture or to the ring network architecture. Such reconfiguration is performed, for example, by changing operation modes of the optical transceivers 30 to correspond to the reconfigured network architecture.” Reconfiguration of the network architecture is seen to inherently require mapping of external optical interconnects with intra-package optical fibers).
Handelman as set forth above does not disclose the use of external optical fibers per the following specific claim language:
connecting a plurality of external optical fibers to the IC package and
to map the plurality of individual external optical fibers.
Mere duplication of parts has no distinguishing significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP § 2144.04(VI)(B).
Handelman discloses a fiber mesh network which is seen to include fibers in the form of optical fibers.
Using optical fibers for external optical connections is seen as duplicating parts in the form of duplicating internal optical fibers.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use optical fibers for external optical interconnects along the lines of internal Handelman optical fibers in a system according to Handelman as set forth above in order to provide optical interconnection. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the reference) to yield predictable results (a photonic integrated circuit/PIC) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide the use of external optical fibers per the following specific claim language:
connecting a plurality of external optical fibers to the IC package and
to map the plurality of individual external optical fibers.
With respect to claim 2, Handelman as set forth above discloses the IC package of claim 1, including one further comprising
a first optical die comprising the configurable optical switch (80),
wherein a second optical die comprises the plurality of optical transceivers (30), and
the plurality of optical transceivers are operably coupled to the configurable optical switch (per Fig. 1).
Handelman, ¶ 118, provides:
"The PIC device 10 also preferably includes an interface unit 130. The interface unit 130 preferably associates the set of optical transceivers 30 with at least one of the following: subsystems of an electronic chip (not shown) which communicate with each other via the set of optical transceivers 30; and a set of electronic chips (not shown) which communicate with each other via the set of optical transceivers 30. The subsystems of the electronic chip and the set of electronic chips may be comprised in the PIC device 10 or associated with the PIC device 10."
This is seen to disclose that the circuitry of Handelman may be parcelled out into any number of chips and/or dies.
With respect to claim 4, Handelman as set forth above discloses the IC package of claim 1, including one wherein
the IC die (130) is a first die comprising the plurality of optical transceivers (30) electrically coupled to the electronic circuitry and optically coupled to a first optical port on the first die,
wherein a second die comprises the configurable optical switch (80) and a second optical port optically coupled to the configurable optical switch.
Optical ports are seen as present in the interfaces between circuit elements (30 et al.) and optical paths (65).
With respect to claim 5, Handelman as set forth above discloses the IC package of claim 1, including one further comprising
an optical die including the configurable optical switch and at least one of the plurality of optical transceivers.
Per claim 2, above, ¶ 118 is seen to disclose that the circuitry of Handelman may be parcelled out into any number of chips and/or dies.
With respect to claim 6, Handelman as set forth above discloses the IC package of claim 1, including one wherein
the IC die comprises an electronic logic circuit electrically coupled to the configurable optical switch; and
wherein the electronic logic circuit is to activate the electronic logic circuitry of the configurable optical switch to switch routing within the configurable optical switch.
¶ 126, "Preferably, the PIC device 10 is operatively associated with a control and management system 190. The control and management system 190 is external to the PIC device 10. Alternatively, part of the control and management system 190 may be comprised in the PIC device 10.” This disclosure is seen to enable combination of IC 190 with any other circuitry of Handelman, including IC die 130.
With respect to claim 7, Handelman as set forth above discloses the IC package of claim 6, including one wherein
the electronic logic circuit (190) is to configure the configurable optical switch (80) to re-route an optical signal on at least one of the plurality of exo-package optical ports (left hand side 160/170/240/250) to at least one of the second plurality of intra-package optical ports (upper half 80) .
Per the reconfigurable system of claim 1, and the circuit’s ability to change its network architecture via bidirectional/star coupler 80 and (per ¶ 141) "by changing operation modes of the optical transceivers 30 to correspond to the reconfigured network architecture."
Further, claim 7 requires a device constructed according to its immediate parent claim, claim 6, to be operated in a certain manner.
The manner of operating the device does not differentiate an apparatus claim from the prior art. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987) (The preamble of claim 1 recited that the apparatus was “for mixing flowing developer material” and the body of the claim recited “means for mixing ..., said mixing means being stationary and completely submerged in the developer material”. The claim was rejected over a reference which taught all the structural limitations of the claim for the intended use of mixing flowing developer. However, the mixer was only partially submerged in the developer material. The Board held that the amount of submersion is immaterial to the structure of the mixer and thus the claim was properly rejected.). MPEP § 2114(II).
Consequently, claim 7 is rejected on the same grounds as its immediate parent claim, claim 6, as not being differentiated from it.
With respect to claim 8, Handelman as set forth above discloses the IC package of claim 7, including one wherein
a nonvolatile memory is coupled to the electronic logic circuit (¶ 148, "Preferably, the control and management system 190 maintains an identification of the first sub-group and an identification of the second sub-group."),
the nonvolatile memory is operable to store binary data comprising switch configuration information readable by the electronic logic circuit (Id.), and
wherein the nonvolatile memory is programmable through a connection to an external logic device (¶ 141, "For example, if initially the PIC device 10 is configured in the star network architecture, the PIC device 10 may later be reconfigured, for example in response to an instruction entered by an operator of the control and management system 190, from the star network architecture to the bus/broadcast network architecture or to the ring network architecture.” Instructions are seen as programming).
With respect to claim 9, Handelman as set forth above discloses the IC package of claim 8, including one wherein
the electronic logic circuit (190) is to produce logic signals operably coupled to the configurable optical switch (per above, claim 6),
wherein the logic signals are to dynamically reconfigure the optical coupling according to the switch configuration information stored within the nonvolatile memory (¶ 141 re configurable architecture per claim 8, above).
With respect to claim 10, Handelman as set forth above discloses the IC package of claim 6, including one wherein
the electronic logic circuit is to detect a degradation in optical performance of one or more optical ports coupled to the configurable optical switch.
the electronic logic circuit is to detect a degradation in optical performance of one or more optical ports coupled to the configurable optical switch (intended use, see below).
Claim 10 requires a device constructed according to its immediate parent claim, claim 6, to be operated in a certain manner.
The manner of operating the device does not differentiate an apparatus claim from the prior art. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987) (The preamble of claim 1 recited that the apparatus was “for mixing flowing developer material” and the body of the claim recited “means for mixing ..., said mixing means being stationary and completely submerged in the developer material”. The claim was rejected over a reference which taught all the structural limitations of the claim for the intended use of mixing flowing developer. However, the mixer was only partially submerged in the developer material. The Board held that the amount of submersion is immaterial to the structure of the mixer and thus the claim was properly rejected.). MPEP § 2114(II).
Consequently, claim 10 is rejected on the same grounds as its immediate parent claim, claim 6, as not being differentiated from it.
Further, for product and apparatus claims, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP § 2112.01(I).
Below, this analysis is referred to as “intended use”. Subject matter in the claims directed to the intended use of a structure is not seen as providing a structural distinction over prior art.
With respect to claim 11, Handelman as set forth above discloses the IC package of claim 10, including one wherein
the electronic logic circuit is to produce logic signals to be sent to the configurable optical switch to switch a first optical connection from a second optical connection to a third optical connection (intended use, per above),
wherein the second optical connection has a degradation in operational performance detectable by the electronic logic circuit, and
the third optical connection is a substantially functional optical connection.
¶ 141 has "the star network, the bus/broadcast network and the ring network due to, inter alia, the structure of the optical interconnect mesh 20." which is seen to provide multiple configurations between several optical connections. Degradation would occur when one configuration is less preferable to another.
With respect to claim 12, Handelman as set forth above discloses the IC package of claim 1, including one wherein
the IC package (10) is electrically coupled to a printed circuit board (PCB; ¶ 105, "The photonic integrated circuit device is suitable for integration into a hybrid electrical-optical printed circuit board (PCB) or is integrated into a hybrid electrical-optical PCB."; ¶ 127), and
wherein the IC package is electrically coupled to power signal routing within the PCB wherein the IC package is electrically coupled to power signal routing within the PCB (as per usual/normal PCB/circuit operation).
With respect to claim 13, Handelman as set forth above discloses the IC package of claim 12, including one wherein
the IC package is a first IC package,
the IC die is a first IC die,
the configurable optical switch is a first configurable optical switch,
further comprising a second IC package optically coupled through one or more optical fibers to the at least one of the plurality of exo-package optical ports of the first IC package,
the second IC package comprising a second IC die and a second configurable optical switch.
Duplication of parts (see below) vie external optical unit 150 and/or adapter 180, ¶ 121 et seq. and ¶ 156.
Per ¶ 156:
It is appreciated that the PIC device 10 may be comprised in a photonic switch (not shown) and used to switch and route optical signals. For example, a first OE node in the PIC device 10 may receive an optical packet either from a first element of the photonic switch (not shown) or from a chip in the PIC device 10 which is associated with the first OE node and switch the optical packet either to a second OE node of the PIC device 10 or to a second element of the photonic switch. In such an application, the photonic switch replaces the external optical unit 150 and reception of the optical packet from the first element of the photonic switch and transmission of the optical packet to the second element of the photonic switch are preferably performed via the link adder 140. The optical packet may include a fixed-length optical packet, or an optical burst, that is a variable-length optical packet.
Mere duplication of parts has no distinguishing significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP § 2144.04(VI)(B). Here, Handelman is seen to provide for duplication of additional PIC device elements and other elements in a photonic switch.
With respect to claim 14, Handelman as set forth above discloses the IC package of claim 13, including one wherein
the first IC die comprises an electronic logic circuit optically coupled to the second configurable optical switch within the second IC package (per coordination between switches, see claim 13, above),
wherein the electronic logic circuit is coupled to a non-volatile memory (¶ 148, "Preferably, the control and management system 190 maintains an identification of the first sub-group and an identification of the second sub-group.") comprising configuration information (Id.) readable by the electronic logic circuit to produce logic signals to be sent to the second configurable optical switch (per claim 13, above, the duplication of parts therein and the photonic switch operation).
Response to Arguments
Applicant's arguments filed July 20, 2026 have been fully considered but they are not persuasive and the claim rejections are not rebutted.
Applicant argues that:
An optical switch having a having a first interface and a second interface, the first interface having a first plurality of intra-package optical ports, the second interface having a second plurality of intra-package optical ports, with a plurality of intra-package optical fibers between the second interface of the configurable optical switch and a plurality of optical transceivers and a plurality of exo-package optical ports operably coupled to the first interface of the configurable optical switch, is not found in Handelman.
Instead, Handelman describes an optical mesh 20 having a first side and a second side, with the first side having a plurality of ports coupled to optical transceivers 30 and a link adder 140, and the second side having a single port 100 coupled to a reflecting optical element 70 (see at least Figure 1 and paragraphs 0045 and 0121 [sic, “)”].
Examiner response: As indicated in the rejections, Handelman is seen to provide all claimed elements and relationships
Furthermore, a configurable optical switch including electronic logic circuitry to receive configuration information to map the plurality of individual external optical fibers to the plurality of individual intra-package optical fibers is not found in Handelman.
Examiner response: Such mapping is seen as inherent with the reconfigurable network architectures provided by Handelman.
Instead, configurability described by Handelman is performed by changing operation modes of optical transceivers 30 (see at least paragraph 0141), in contrast to configurability being provided by electronic logic circuitry within optical mesh 20. No description or suggestion of mapping individual external optical fibers to individual intra-package optical fibers is found in Handelman. In contrast, Handelman describes that transmission by one opto-electronic (OE) node is received by all other OE nodes (see at least paragraph 0136).
Examiner response: Mapping is seen as inherent for if there was no such mapping, there would be no successful network operation from configuration to configuration.
Applicant's arguments with regards to the remaining claims all rely upon the arguments set forth above. Consequently, these remaining arguments as seen as being addressed by the examiner's corresponding remarks.
Applicant’s remaining arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. As such, the examiner makes no remarks regarding them.
Conclusion
Applicant’s publication US 20220413216 A1 published December 29, 2022 was previously cited.
No new art is cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW JORDAN whose telephone number is (571) 270-1571. The examiner can normally be reached most days 1000-1800 PACIFIC TIME ZONE (messages are returned).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. While examiner does not examine over the phone (see 37 C.F.R. § 1.2), examiner is glad to clarify or discuss issues so long as it forwards prosecution.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas (Tom) HOLLWEG can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andrew Jordan/
Primary Examiner, Art Unit 2874
V: (571) 270-1571 (Pacific time)
F: (571) 270-2571
August 28, 2026
Prosecution Insights