Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 11/07/2025 on pages 13-14 of Remarks regarding the rejection under 35 U.S.C. 102 and pages 14-15 regarding the rejection under 35 U.S.C. 103 have been fully considered but are not persuasive.
Beginning on page 14, Applicant respectfully asserts under 35 U.S.C. 102 that Li fails to disclose “wherein each of the computing units comprises a resistive random access memory (ReRAM) crossbar”. However, Shafiee teaches “wherein each of the computing units comprises a resistive random access memory (ReRAM) crossbar” in paragraphs [0028-0029], ““FIG. 4 is an example of a processing apparatus 400 comprising a plurality of processing units 402, wherein each of the processing units 402 comprises a plurality of resistive memory arrays 404, a buffer 406 and a control unit 408. Each of the resistive memory arrays 404 is for use in performing a processing operation in a layer of a multilayer processing task”; and “Each processing unit 402 may comprises a processing ‘tile’ (level 2 computing node), and there may be at least one such tile on a die or a chip (if there a multiple tiles, some components, for example a buffer, may be shared in some examples). The buffer 406 may comprise an embedded memory, and may be to receive data for processing by the resistive memory arrays of the same processing unit 402.”
Applicant asserts that Li lacks the level 2 nodes, however see 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.) Examiner notes that the processing elements are level 1 and the cores are the level 2 computing nodes.)
Beginning on page 15, Applicant respectfully asserts under 35 U.S.C. 103 that Shafiee fails to disclose requiring level 2 nodes. However in paragraph [0029], Shafiee discloses “Each processing unit 402 may comprises a processing ‘tile’, and there may be at least one such tile on a die or a chip (if there a multiple tiles, some components, for example a buffer, may be shared in some examples). The buffer 406 may comprise an embedded memory, and may be to receive data for processing by the resistive memory arrays of the same processing unit 402. In some examples, the buffer 406 may be connected to the resistive memory arrays 404 of the processing unit 402 via a data bus which is configured to handle the maximum bandwidth to carry the buffered data to the arrays 404 within one data operation period (termed a ‘stage’ herein after) of the arrays 404. In some examples, the buffer 406 comprises a “first in first out” (FIFO) data buffer, and provides data storage in a column-wise manner. As data is received, this may be stored in the buffer 406. When the buffer 406 is full, the data may be overwritten such that new data will overwrite oldest data.” Examiner notes that the processing tile is a level 2 node.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitation(s) is/are:
“computing units” in claims 1, 2, 4-14, 17, 19 and 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-21 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks); hereinafter Li in view of Shafiee Ardestani et al. (US20180113649A1); hereinafter Shafiee
Claim 1 is rejected over Li and Shafiee. Regarding claim 1, Li teaches a neural network (NN) system comprising: (“SynergyFlow can adaptively adjust the computing capacity of the C-Engine and F-Engine to better accommodate various NN models.”; 3.3 and Fig. 6(b) and Fig. 11)
a plurality of NN chips, wherein each of the NN chips comprises level 2 computing nodes, and wherein each of the level 2 computing nodes comprises: (See 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.) Examiner notes that the processing elements are level 1 and the cores are the level 2 computing nodes.)
P computing units, [wherein each of the P computing units comprises a resistive random-access memory (ReRAM) crossbar,] configured to: (See Table 2; 4.2.3 Analytical Model for SynergyFlow: Nc: total amount of cores in C-Engine (P computing units).)
receive first input data (See Table 1: N0: number of input feature maps (first input data);) totaling a first data volume, and (See Table 1. Workload Characterization for NN Models to see that while R represents the height of output feature maps and C represents the width of output feature maps, it is reasonable to view that R and C are tied to the first data volume as the output feature maps derive from the input feature maps.)
perform computing on the first input data based on N configured first weights (Note: Allocating more cores implies duplicating the kernel weights (N configured first weights.)) to obtain first output data; and (“(only in the final CONV layer (C-Engine), the feature maps are flattened into a feature vector (first output data), serving as the input of the FC layers (F-Engine); 3.3 SynergyFlow Architecture)
Q computing units, [wherein each of the Q computing units comprises a ReRAM crossbar] configured to: (See Table 2; 4.2.3 Analytical Model for SynergyFlow: Nc: total amount of cores in F-Engine (Q computing units).)
receive second input data totaling a second data volume, wherein the second input data includes the first output data; (“For example, the F-Engine takes the output of the C-Engine (first output data) as input (second input data)”; 4.1.1 Out-of-Order Layer Scheduling, par. 1; Note: The second input data totaling a second data volume is the flattened CONV output from Table 1.)
perform computing on the second input data based on M configured second weights (“(only in the final CONV layer (C-Engine), the feature maps are flattened into a feature vector, serving as the input of the FC layers (F-Engine)”; 3.3 SynergyFlow Architecture and “The MB is designed with Tn ×Tn banks to support the bank-parallel data access of each core. VBi and VBo have Tn banks, storing the feature maps and feature vectors. According to the access patterns, the feature maps and kernels are stored in a column-first manner, while feature vectors and weights (M configured second weights) are stored in a row-first manner.)”; 5.1 Dataflow Control Instructions) to obtain second output data (See Table 1: M1 and N1: number of output feature vectors (second output data)); and
determine, based on a deployment requirement and network model information, a first output data volume and a second output data volume, (“Given the workload characterization and platform specifications, we can roughly evaluate the system performance by theoretical estimation. We start with a neural network composed of a single CONV layer and a single FC layer; the total computation demand and memory access demand of the network is estimated as follows (deployment requirement):”; 4.2.3 Analytical Model for SynergyFlow; Note: See Table 1. Workload Characterization for NN Models to see that M0, R and C are the first output data volume M1 x N1 are the second output data volume which are also the network model information. The workload characterization is the network model information.)
wherein a first ratio of N to M corresponds to a second ratio of the first data volume to the second data volume, (Note: The first ratio of the kernel weights (N) to the FC weights (M) correspond to the second ratio of the CONV layer’s C-Engine output size (first data volume) to the output of the FC layer’s F-Engine input size (second data volume).) wherein P, Q, N, and M are positive integers. (Note: Implicit as there can’t be a negative number of computing units and weights.)
Li does not teach wherein each of the P computing units comprises a resistive random-access memory (ReRAM) crossbar,
wherein each of the Q computing units comprises a ReRAM crossbar
However, Shafiee teaches wherein each of the P computing units comprises a resistive random-access memory (ReRAM) crossbar,
wherein each of the Q computing units comprises a ReRAM crossbar (“FIG. 4 is an example of a processing apparatus 400 comprising a plurality of processing units 402, wherein each of the processing units 402 comprises a plurality of resistive memory arrays 404, a buffer 406 and a control unit 408. Each of the resistive memory arrays 404 is for use in performing a processing operation in a layer of a multilayer processing task”; [0028] and “Each processing unit 402 may comprises a processing ‘tile’ (level 2 computing node), and there may be at least one such tile on a die or a chip (if there a multiple tiles, some components, for example a buffer, may be shared in some examples). The buffer 406 may comprise an embedded memory, and may be to receive data for processing by the resistive memory arrays of the same processing unit 402.”; [0029])
It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention to have performed this in combination of Li processing second output data using the computing units of the F-Engine and C-Engine and Shafiee applying resistive memory arrays to the computing units for efficient parallel processing of data (Shafiee, [0024]). Li and Shafiee are analogous art because they both teach a method for allocating computational resources in a neural network system.
Claim 3 is rejected over Li and Shafiee with the incorporation of claim 1.
Li teaches wherein the network model information comprises first output data volume of a first NN layer and second output data volume of a second NN layer, and wherein the network model information is based on the deployment requirement. (“To simplify discussion, we assume the maximal time period of processing a CONV task or FC task as one “logical” cycle, or simply cycle unless otherwise specified, to differentiate from the actual clock cycle of cores.”; 4.1 Working Principles and “Given the workload characterization and platform specifications, we can roughly evaluate the system performance by theoretical estimation. We start with a neural network composed of a single CONV layer and a single FC layer; the total computation demand and memory access demand of the network is estimated as follows (deployment requirement):”; 4.2.3 Analytical Model for SynergyFlow; Note: See Table 1. Workload Characterization for NN Models to see that M0, R and C are the first output data volume of the first CONV layer and M1 x N1 are the second output data volume of the second FC layer which are also the network model information. The workload characterization is the network model information. The clock cycle of cores is also considered to be part of the deployment requirement as it determines computational throughput.)
Claim 4 is rejected over Li and Shafiee with the incorporation of claim 1.
Li teaches wherein the deployment requirement comprises a specified computing delay, (“To simplify discussion, we assume the maximal time period of processing a CONV task or FC task as one “logical” cycle, or simply cycle unless otherwise specified, to differentiate from the actual clock cycle of cores.”; 4.1 Working Principles and “Suppose that we have achieved an optimal state under these design parameters; then we can estimate the computation time of both layers as follows”; 4.2.3 Analytical Model for SynergyFlow; Note: The clock cycle of cores are associated with Equation (6) where the computation time of the layers is estimated and Equation (7) where the memory bandwidth requirement is calculated. Those contribute to the computing delay.)
wherein the P computing units are configured to perform an operation of a first NN layer which is a beginning layer of all NN layers in the NN system, (“(only in the final CONV layer (P computing units of C-Engine), the feature maps are flattened into a feature vector (first output data), serving as the input of the FC layers (F-Engine).”; 3.3 SynergyFlow Architecture)
wherein M is based on N and the second ratio. (Note: The first ratio of the kernel weights (N) to the FC weights (M) correspond to the second ratio of the CONV layer’s C-Engine output size (first data volume) to the output of the FC layer’s F-Engine input size (second data volume).)
wherein N is based on the first data volume, (See Table 1. Workload Characterization for NN Models to see that while R represents the height of output feature maps and C represents the width of output feature maps, it is reasonable to view that R and C are tied to the first data volume as the output feature maps derive from the input feature maps.) the computing delay, and (“To simplify discussion, we assume the maximal time period of processing a CONV task or FC task as one “logical” cycle, or simply cycle unless otherwise specified, to differentiate from the actual clock cycle of cores.”; 4.1 Working Principles and “Suppose that we have achieved an optimal state under these design parameters; then we can estimate the computation time of both layers as follows”; 4.2.3 Analytical Model for SynergyFlow; Note: The clock cycle of cores are associated with Equation (6) where the computation time of the layers is estimated and Equation (7) where the memory bandwidth requirement is calculated. Those contribute to the computing delay.)
Li does not teach a computing frequency of one of the ReRAM crossbars in one of the P computing units or one of the Q computing units, and
However, Shafiee teaches a computing frequency of one of the ReRAM crossbars in one of the P computing units or one of the Q computing units, and (“Each processing unit 402 may comprises a processing ‘tile’ (level 2 computing node), and there may be at least one such tile on a die or a chip (if there a multiple tiles, some components, for example a buffer, may be shared in some examples). The buffer 406 may comprise an embedded memory, and may be to receive data for processing by the resistive memory arrays of the same processing unit 402 and See 3.3 SynergyFlow Architecture: According to the access patterns, the feature maps and kernels are stored in a column-first manner, while feature vectors and weights (M configured second weights) are stored in a row-first manner.”; 3.3 SynergyFlow Architecture; and “A method which may for example be used in setting up a processing apparatus to carry out the method of FIG. 1 is now described with reference to FIG. 2. In block 202, a number of resistive memory arrays to be allocated to a processing layer is determined based on the relative processing rates of the layers, wherein the determining is to balance processing rates of the layers.”; [0023])
It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention to have performed this in combination of Li processing second output data using the computing units of the F-Engine and C-Engine and Shafiee applying resistive memory arrays to the computing units for efficient parallel processing of data (Shafiee, [0024]). Li and Shafiee are analogous art because they both teach a method for allocating computational resources in a neural network system.
Claim 5 is rejected over Li and Shafiee with the incorporation of claim 1.
Li teaches wherein the deployment requirement comprises a first quantity of the NN chips, wherein the P computing units are further configured to perform an operation of a first NN layer which is a beginning layer of all NN layers in the NN system, (“(only in the final CONV layer (P computing units of C-Engine), the feature maps are flattened into a feature vector (first output data), serving as the input of the FC layers (F-Engine)”; 3.3 SynergyFlow Architecture; Note: See 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.))
a data volume ratio of output data of adjacent NN layers, and wherein M is based on N and the second ratio. (Note: Feature vector weights (M) correspond to the kernel weights (N) and to the second ratio of the kernels (first data volume) to the output of the F-Engine (second data volume).)
Li does not teach wherein N is based on the first quantity, a second quantity of the ReRAM crossbars in one of the P computing units or one of the Q computing units in each of the NN chips, a third quantity of the ReRAM crossbars in one of the P computing units or one of the Q computing units for deploying a weight of each of the NN layers, and
However, Shafiee teaches wherein N is based on the first quantity, a second quantity of the ReRAM crossbars in one of the P computing units or one of the Q computing units in each of the NN chips, a third quantity of the ReRAM crossbars in one of the P computing units or one of the Q computing units for deploying a weight of each of the NN layers, and (Each processing unit 402 may comprises a processing ‘tile’ (level 2 computing node), and there may be at least one such tile on a die or a chip (if there a multiple tiles, some components, for example a buffer, may be shared in some examples). The buffer 406 may comprise an embedded memory, and may be to receive data for processing by the resistive memory arrays of the same processing unit 402 and see [0048]: FIG. 7 comprises a method including block 602 of FIG. 6. In this example, blocks 702 and 704 are an example of determining a distribution of resistive memory arrays as described in block 604 by allocating a synaptic weight memory capacity to each of the layers, the memory capacity being for storing synaptic weights.”; [0029]; and “at least one processing operation of the first and second layers may be performed in an overlapping time frame. This method may therefore provide a pipeline of data processing in which processing layers are carried out at least partially concurrently.”; [0019]; Note: The first and second layers contain P and Q computing units.)
It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention to have performed this in combination of Li processing second output data using the computing units of the F-Engine and C-Engine and Shafiee applying resistive memory arrays to the computing units for efficient parallel processing of data (Shafiee, [0024]). Li and Shafiee are analogous art because they both teach a method for allocating computational resources in a neural network system.
Claim 6 is rejected over Li and Shafiee with the incorporation of claim 1.
Li teaches wherein one of the P computing units (See Table 2; 4.2.3 Analytical Model for SynergyFlow: Nc: total amount of cores in C-Engine (P computing units).) and one of the Q computing units (See Table 2; 4.2.3 Analytical Model for SynergyFlow: Nc: total amount of cores in F-Engine (Q computing units).)
are disposed in one of the level 2 computing nodes. (See 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.))
Claim 7 is rejected over Li and Shafiee with the incorporation of claim 1.
Li teaches wherein one of the level 2 computing nodes to which the P computing units belong (See Table 2; 4.2.3 Analytical Model for SynergyFlow: Nc: total amount of cores in C-Engine (P computing units).) and one of level 2 computing nodes to which the Q computing units belong (See Table 2; 4.2.3 Analytical Model for SynergyFlow: Nc: total amount of cores in F-Engine (Q computing units).) are disposed in one of the NN chips. (See 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.))
Claim 8 is rejected over Li and Shafiee.
Regarding claim 8, Li teaches a data processing method implemented by a neural network (NN) system and comprising: (“SynergyFlow can adaptively adjust the computing capacity of the C-Engine and F-Engine to better accommodate various NN models.”; 3.3 and Fig. 6(b) and Fig. 11)
The remainder of claim 8 is claim 1 in the form of a method and is rejected for the same reasons as claim 1 stated above.
Dependent claim 9 is claim 4 in the form of a method and is rejected for the same reasons as claim 4 stated above. For the rejection of the limitations specifically pertaining to the method of claim 8, see the rejection of claim 8 above.
Dependent claim 10 is claim 5 in the form of a method and is rejected for the same reasons as claim 5 stated above. For the rejection of the limitations specifically pertaining to the method of claim 8, see the rejection of claim 8 above.
Claim 11 is rejected over Li and Shafiee with the incorporation of claim 8.
Li teaches wherein one of the P computing units and one of the Q computing units are disposed in one of the level 2 computing nodes. (See 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.))
Dependent claim 12 is claim 7 in the form of a method and is rejected for the same reasons as claim 7 stated above. For the rejection of the limitations specifically pertaining to the method of claim 8, see the rejection of claim 8 above.
Claim 13 is rejected over Li and Shafiee.
Regarding claim 13, Li teaches a computer program product comprising instructions that are stored on a computer-readable medium and that, when executed by a processor, cause a neural network (NN) system to: (“SynergyFlow can adaptively adjust the computing capacity of the C-Engine and F-Engine to better accommodate various NN models.”; 3.3 and Fig. 6(b) and Fig. 11)
The remainder of claim 13 is claim 1 in the form of a non-transitory computer-readable medium and is rejected for the same reasons as claim 1 stated above.
Claim 14 is rejected over Li and Shafiee with the incorporation of claim 13.
Regarding claim 14, Li teaches wherein the P computing units are configured to perform an operation of a first NN layer comprising a beginning layer of all NN layers in the NN system. (“(only in the final CONV layer (P computing units of C-Engine), the feature maps are flattened into a feature vector (first output data), serving as the input of the FC layers (F-Engine).”; 3.3 SynergyFlow Architecture)
Claim 15 is rejected over Li and Shafiee with the incorporation of claim 13.
Li teaches wherein N is based on the first data volume (“(See Table 1. Workload Characterization for NN Models to see that while R represents the height of output feature maps and C represents the width of output feature maps, it is reasonable to view that R and C are tied to the first data volume as the output feature maps derive from the input feature maps.”; See 5.1 Dataflow Control Instructions), a specified computing delay of the NN system, and (“(“To simplify discussion, we assume the maximal time period of processing a CONV task or FC task as one “logical” cycle, or simply cycle unless otherwise specified, to differentiate from the actual clock cycle of cores.”; 4.1 Working Principles and “Suppose that we have achieved an optimal state under these design parameters; then we can estimate the computation time of both layers as follows”; 4.2.3 Analytical Model for SynergyFlow; Note: The clock cycle of cores are associated with Equation (6) where the computation time of the layers is estimated and Equation (7) where the memory bandwidth requirement is calculated. Those contribute to the computing delay.)
Li does not teach a computing frequency of one of the ReRAM crossbars in one of the P computing units or one of the Q computing units.
However, Shafiee teaches a computing frequency of one of the ReRAM crossbars in one of the P computing units or one of the Q computing units. (“Each processing unit 402 may comprises a processing ‘tile’ (level 2 computing node), and there may be at least one such tile on a die or a chip (if there a multiple tiles, some components, for example a buffer, may be shared in some examples). The buffer 406 may comprise an embedded memory, and may be to receive data for processing by the resistive memory arrays of the same processing unit 402”; [0029] and “A method which may for example be used in setting up a processing apparatus to carry out the method of FIG. 1 is now described with reference to FIG. 2. In block 202, a number of resistive memory arrays to be allocated to a processing layer is determined based on the relative processing rates of the layers, wherein the determining is to balance processing rates of the layers.”; [0023])
It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention to have performed this in combination of Li processing second output data using the computing units of the F-Engine and C-Engine and Shafiee applying resistive memory arrays to the computing units for efficient parallel processing of data (Shafiee, [0024]). Li and Shafiee are analogous art because they both teach a method for allocating computational resources in a neural network system.
Claim 16 is rejected over Li and Shafiee with the incorporation of claim 13.
Li teaches wherein M is based on N and the second ratio. (Note: The first ratio of the kernel weights (N) to the FC weights (M) correspond to the second ratio of the CONV layer’s C-Engine output size (first data volume) to the output of the FC layer’s F-Engine input size (second data volume).)
Claim 17 is rejected over Li and Shafiee with the incorporation of claim 13.
Li teaches wherein the P computing units are further configured to perform an operation of a first NN layer which is a beginning layer in the NN system. (“(only in the final CONV layer (P computing units of C-Engine), the feature maps are flattened into a feature vector (first output data), serving as the input of the FC layers (F-Engine).”; 3.3 SynergyFlow Architecture:)
Dependent claim 18 is claim 5 in the form of a computer-readable medium and is rejected for the same reasons as claim 5 stated above. For the rejection of the limitations specifically pertaining to the computer-readable medium of claim 13, see the rejection of claim 13 above.
Claim 19 is rejected over Li and Shafiee with the incorporation of claim 13.
Regarding claim 19, Li teaches wherein the NN system comprises NN chips, wherein each of the NN chips comprises level 2 computing nodes, wherein each of the level 2 computing nodes comprises computing units, and (See 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.))
wherein one of the P computing units (See Table 2; 4.2.3 Analytical Model for SynergyFlow: Nc: total amount of cores in C-Engine (P computing units).) and one of the Q computing units (See Table 2; 4.2.3 Analytical Model for SynergyFlow: Nc: total amount of cores in F-Engine (Q computing units).) are located in one of the level 2 computing nodes. (See 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.))
Claim 20 is rejected over Li and Shafiee with the incorporation of claim 13.
Regarding claim 20, Li teaches wherein one of the level 2 computing nodes to which the P computing units belong and one of the level 2 computing nodes to which the Q computing units belong are disposed in one of the NN chips. (See 5.1 Dataflow Control Instructions Fig. 11: Architecture of each core and PE architecture (level 2 computing nodes.))
Dependent claim 21 is claim 3 in the form of a method and is rejected for the same reasons as claim 3 stated above. For the rejection of the limitations specifically pertaining to the method of claim 8, see the rejection of claim 8 above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DAVID H TRAN/Examiner, Art Unit 2147
/VIKER A LAMARDO/Supervisory Patent Examiner, Art Unit 2147