Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In the previous Office Action issued 8-8-2025 (hereinafter “the previous Office Action”), claims 1, 3-7, 9-16, and 18-20 were pending.
This action is in response to the amendment and remarks filed 11-6-2025. In the amendment, claims 1, 4-7, 10-16, and 19-20 were amended, claims 2-3, 8-9, and 17-18 were canceled, and no claims were added. Thus, claims 1, 4-7, 10-16, and 19-20 are pending.
The objections of claims 7, 9-16, and 18-20, set forth in the previous Office Action, have been withdrawn in view of Applicant’s amendments and remarks.
The interpretation of claims 1, 3-7, 9-16, and 18-20 under 35 U.S.C. § 112(f), set forth in the previous Office Action, have been withdrawn in view of Applicant’s amendments and remarks. Furthermore, the rejections of claims 1, 3-7, 9-16, and 18-20 under 35 U.S.C. § 112(a) and 35 U.S.C. § 112(b) have been withdrawn in view of Applicants amendments and remarks.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-7, 10-16, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 1, 7, and 16:
Claims 1, 7, and 16 recites the limitation "the digital circuitry". There is insufficient antecedent basis for this limitation in the claims. Applicant is advised to amend “the digital circuitry” to “the plurality of digital circuitry”.
Claims 4-6 are rejected for inheriting the deficiencies of claim 1.
Claims 10-15 are rejected for inheriting the deficiencies of claim 7.
Claims 19-20 are rejected for inheriting the deficiencies of claim 16.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4-5, 7, 10-11, 16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Busch et al. (US 20190034790), hereinafter Busch, in view of Moradi et al. (“An Event-Based Neural Network Architecture with an Asynchronous Programmable Synaptic Memory”), hereinafter Moradi, and further in view of Lehmann (“Teaching Pulsed Integrated Neural Systems: A Psychobiological Approach”).
Regarding Claim 1:
Busch discloses:
A system comprising:
Busch, [0002], “embodiments of the disclosure relate to, but are not limited to, systems and methods for partial digital retraining of artificial neural networks disposed in analog multiplier arrays of neuromorphic integrated circuits.”
a plurality of analog arrays that comprise all synaptic weights of a neural network
Busch, [0015], “disclosed herein is a neuromorphic integrated circuit including, in some embodiments, a multi-layered analog-digital hybrid neural network…[the] neural network includes a number of analog layers configured to include synaptic weights between neural nodes of the neural network for decision making by the neural network.”
In para. 15, Busch discloses a neural network including a number of analog layers [a plurality of analog arrays] which includes the neural network’s synaptic weights [comprise all synaptic weights of a neural network]. The analog layers correspond to the analog arrays because, as cited above in 2, the analog layers are disclosed to be analog multiplier arrays [analog arrays].
when the neural network is in a production environment
Busch, [0063], “decision making by the hybrid neural network 500 can include predicting discrete classes for one or more classification problems.”
Busch discloses using the neural network for classification problems [neural network is in a production environment].
to correct one or more of the synaptic weights of one or more connections to the one or more neurons responsive to determining that the one or more synaptic weights of the one or more connections are associated with an inaccuracy
Busch, [0057], “weight drifts occurring via electrostatic discharge from the cells can cause the number of analog layers of the hybrid neural network 500 to begin to arrive at incorrect decisions…When the incorrect decisions of the hybrid neural network 500 become known, the digital layer of the hybrid neural network 500 can be programmed through a partial digital retraining process to correct or compensate for the weight drifts, which allows the hybrid neural network 500 to arrive at correct decisions…”
Busch discloses using the digital layer(s) of the neural network to correct or compensate for weight drifts [correct one or more of the synaptic weights of one or more connections to one or more neurons] when incorrect decisions of the neural network become known [responsive to determining that the one or more synaptic weights of the one or more connections are associated with an inaccuracy].
Busch does not explicitly disclose:
a plurality of digital circuitry that are concurrently co-trained along with the plurality of analog arrays in generating the neural network
intermittently connecting the digital circuitry to one or more neurons within the neural network…
However, in the same field, analogous art Moradi teaches:
a plurality of digital circuitry that are concurrently co-trained along with the plurality of analog arrays in generating the neural network
Moradi, pg. 1, col. 2, “In this specific scenario, this suggests the design of full custom analog/digital Very Large Scale Integration (VLSI) neuromorphic systems.”
Pg. 2, col. 1, “By including the VLSI device in the training loop, the circuit non-idealities and variability can be potentially adapted away through the PC-based learning algorithms. Once the network has been trained and the synaptic weight values stored in the SRAM, the VLSI device can be used in stand-alone mode to carry out neural computation in real-time, exploiting its low-power, and compact size properties.”
Pg. 2, col. 2, “The architecture of the chip is illustrated in Fig. 1. It comprises five main blocks: the asynchronous controller…The asynchronous controller manages the communication between the external digital asynchronous signals and the on-chip ones.”
On pg. 1, col. 2, Moradi discloses a custom analog/digital VLSI neuromorphic system. The analog/digital VLSI is construed as Moradi disclosing a plurality of digital circuitry and a plurality of analog arrays. Further on pg. 2, col. 1, Moradi discloses that the VLSI device is used in training neural networks [co-trained…in generating the neural network]. Lastly, pg. 2, col. 2 discloses the chip architecture includes an asynchronous controller that manages asynchronous communication [concurrently] between the digital signals [digital] and the on-chip signals [analog]. Putting it together, Moradi is construed as disclosing a custom, hybrid analog/digital VLSI device used for training neural networks, and the chip architecture includes an asynchronous controller that manages asynchronous communication between the digital and analog signals.
Busch, Moradi, and the instant application are analogous art because they are all directed to neuromorphic systems.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch with Moradi to concurrently perform the digital and analog computations in order to achieve reasonable computation times and use less energy. “In order to apply this computational paradigm to compact efficient neural processing and sensory-motor systems, that compute on real-world sensory signals and interact with the environment in real-time, it is necessary to develop dedicated hardware implementations of spiking neural networks which are low-power and can operate with biologically plausible time-constants” (Moradi, pg. 1, col. 2).
Busch in view of Moradi do not explicitly disclose:
intermittently connecting the digital circuitry to one or more neurons within the neural network…
However, in the same field, analogous art Lehmann teaches:
intermittently connecting the digital circuitry to one or more neurons within the neural network…
Lehmann, pg. 189, “it is crucial for the learning process that that no weight change takes place when either of the inputs to the weight change multiplier is zero. To ensure this, it is preferable to completely disconnect the weight change circuit from the memory capacitor in that case; i.e., by using a switch controlled by an AND gate as indicated in figure 3.”
Pgs. 189-190, “The weight change circuit has been laid out in a 1 μm digital CMOS technology...”
On pg. 189, Lehmann teaches a weight change circuit (specified on pgs. 189-190 to be digital) [digital circuitry] that is to be disconnected when the weight change multiplier is zero [intermittently connected]; it is also interpreted as the weight change circuit is connected when the weight change multiplier is non-zero. Furthermore, as the weight change circuit deals with neurons of the neural network (as cited on pg. 189 above), the weight change circuit is connected to the neurons of the neural network.
Busch, Moradi, Lehmann, and the instant application are analogous art because they are all directed to neuromorphic systems.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch, Moradi, Lehmann to disconnect/connect the weight compensation accordingly in order to accurately compensate for weight drifts. “[It] is crucial for the learning process that that no weight change takes place when either of the inputs to the weight change multiplier is zero. To ensure this, it is preferable to completely disconnect the weight change circuit from the memory capacitor in that case (Lehmann, pg. 189)” Lehmann states that if the weight change multiplier is zero, it is crucial that no weight change actually occurs. Thereby, disconnecting the weight change circuit maintains the accuracy of the weights by preventing unnecessary weight changes.
Regarding Claim 4:
As discussed above, Busch, Moradi, and Lehmann teach [the] system of claim 1, and Busch further discloses:
wherein the connecting is performed responsive to detecting that the analog arrays have failed a performance criterion
Busch, [0057], “incorrect decisions can be tested for on a periodic basis with test data…such as generated test data provided by a test data generator. When the incorrect decisions of the hybrid neural network 500 become known, the digital layer of the hybrid neural network 500 can be programmed through a partial digital retraining process to correct or compensate for the weight drifts”
Busch discloses using the digital layer of the hybrid neural network [connecting is performed responsive to] when incorrect decisions of the hybrid neural network become known [detecting that the analog arrays have failed a performance criterion].
Regarding Claim 5:
As discussed above, Busch, Moradi, and Lehmann teach [the] system of claim 1, and Busch further discloses:
wherein the connecting is performed responsive to detecting that a waiting period has elapsed
Busch, [0057], “incorrect decisions can be tested for on a periodic basis with test data…such as generated test data provided by a test data generator. When the incorrect decisions of the hybrid neural network 500 become known, the digital layer of the hybrid neural network 500 can be programmed through a partial digital retraining process to correct or compensate for the weight drifts”
[0066], “The test data generator can be configured to generate the test data for testing with any desired frequency including, but not limited to, once an hour or once a day for measuring an accuracy of the hybrid neural network 500 and subsequent partial digital retraining, if needed.”
In para. 57, Busch discloses periodically using the digital layer to correct or compensate for weight drifts when incorrect decisions become known. Incorrect decisions are known based on incorrect decisions made based on test data, and para. 66 specifies that the test generator can perform testing for any desired period of time such as once an hour or once a day [in response to a waiting period elapsing].
Regarding Claim 7:
Claim 7 is a computer-implemented method claim corresponding to system claim 1 and is rejected for at least the same reasons as given in the rejection of claim 1, with the exception of the following limitations.
Busch discloses:
A computer-implemented method comprising:
Busch, [0002], “embodiments of the disclosure relate to, but are not limited to, systems and methods for partial digital retraining of artificial neural networks disposed in analog multiplier arrays of neuromorphic integrated circuits.”
training a plurality of analog arrays that comprise all synaptic weights of a neural network
Busch, [0015], “disclosed herein is a neuromorphic integrated circuit including, in some embodiments, a multi-layered analog-digital hybrid neural network…[the] neural network includes a number of analog layers configured to include synaptic weights between neural nodes of the neural network for decision making by the neural network.”
In 15, Busch discloses a neural network including a number of analog layers [a plurality of analog arrays] which includes the neural network’s synaptic weights [comprise all synaptic weights of a neural network]. The analog layers correspond to the analog arrays because, as cited above in 2, the analog layers are disclosed to be analog multiplier arrays [analog arrays].
[0045], “FIG. 1 illustrates a system 100 for designing and updating neuromorphic integrated circuits (“ICs”) is provided in accordance with some embodiments…updating neuromorphic ICs can include creating a machine learning architecture with the simulator 110 based on a particular problem…While the initially fabricated neuromorphic IC 102 can include an initial firmware with custom synaptic weights between the neural nodes, the initial firmware can be updated as needed by the cloud 130 to adjust the weights.”
In para. 45, Busch further discloses designing and updating the neuromorphic ICs which includes adjusting the weights of the neuromorphic IC as needed. This corresponds to claimed language of training because training consists of adjusting weights to ‘teach’ the neural network to solve a particular machine learning problem as disclosed by Busch.
Regarding Claims 10-11:
Claims 10-11 are method claims corresponding to system claims 4-5 and are rejected for at least the same reasons as given in the rejection of claim 4-5. In particular, 10:4, 11:5.
Regarding Claim 16:
Claim 16 is a system claim corresponding to method claim 7 and is rejected for at least the same reasons as given in the rejection of claim 7, with the exception of the following limitations.
Busch discloses:
A system comprising: a processor; and a memory in communication with the processor, the memory containing instructions that, when executed by the processor, cause the processor to:
Busch, [0002], “embodiments of the disclosure relate to, but are not limited to, systems and methods for partial digital retraining of artificial neural networks disposed in analog multiplier arrays of neuromorphic integrated circuits.”
[0039], “Examples of such circuitry may include, but are not limited or restricted to…one or more processor cores…semiconductor memory”
In para. 2, Busch discloses a system, and 39 discloses a processor and memory.
Regarding Claims 19-20:
Claims 19-20 system claims corresponding to system claims 4-5 and is rejected for the same reasons as given in the rejection of claims 4-5. In particular, 19:4, 20:5.
Claims 6 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Busch and Moradi in view of Lehmann, and further in view of Himebaugh et al. (US 20160328642), hereinafter Himebaugh.
Regarding Claim 6:
As discussed above, Busch, Moradi, and Lehmann teach [the] system of claim 1, but do not explicitly disclose:
wherein the connecting is performed responsive to detecting that an energy criterion has been satisfied
However, in the same field, analogous art Himebaugh teaches:
wherein the connecting is performed responsive to detecting that an energy criterion has been satisfied
Himebaugh, [0047], “After the configured weights 118 are loaded onto the analog neural network 106, the analog neural network 106 may begin receiving analog signals associated with the sensor signals output by the sensors 102, 104. When receiving one or more analog signals, the analog neural network 106 determines whether the received analog signal is indicative of an event of interest by determining the similarity of the received analog signal and one or more analog signals that correspond to an event of interest. As described above, the configured weights 118 loaded on to the analog neural network 106, and applied to the neurons of the analog neural network 106, will elicit an analog output that is, for example, a non-zero voltage if a received analog signal is similar to an analog signal that corresponds to an event of interest. If a received analog signal is not similar to an analog signal indicative of an event of interest, the configured weights 118 will elicit an analog output that is, for example, approximately a zero voltage.”
[0026], “ An event of interest, as used herein, may be an operation and/or occurrence of a mechanical, electrical, optical, chemical and/or biological system that a sensor senses that is a significant event for the system and/or not part of the normal operation of the system. The digital processor, operating in a higher-power state may then be utilized for further data processing, system control, data communication, and/or data storage once an event of interest is determined.”
Under broadest reasonable interpretation, operation or occurrence that is a significant event and not part of the normal operation is interpreted as “energy criterion being satisfied”.
Busch, Moradi, Lehmann Himebaugh, and the instant application are analogous art because they are all directed to neuromorphic systems.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch, Moradi, and Lehmann with Himebaugh to activate in response to an energy criterion in order to operate in an energy efficient manner. “In embodiments, the analog neural network 106 may determine whether an event of interest has occurred and output corresponding analog signals continuously or near continuously, which allows the digital processor 108 to remain inactive or otherwise in a low-power state until an event of interest has been determined. As such, devices that incorporate the system 100 therein operate in an energy efficient manner thus increasing implementation possibilities, extending device battery life and providing other benefits” (Himebaugh, [0043]).
Regarding Claims 12:
Claim 12 is a method claim corresponding to system claim 6 and is rejected for the same reasons as given in the rejection of claim 6.
Regarding Claim 13:
As discussed above, Busch, Moradi, and Lehmann teach [the] computer-implemented method of claim 7, but do not explicitly disclose:
further comprising detecting that the plurality of analog arrays has been trained within the neural network, wherein the plurality of digital circuitry is co-trained in response to detecting that the plurality of analog arrays has been trained
However, in the same field, analogous art Himebaugh teaches:
further comprising detecting that the plurality of analog arrays has been trained within the neural network, wherein the plurality of digital circuitry is co-trained in response to detecting that the plurality of analog arrays has been trained
Himebaugh, ¶ [0042], “After the neurons included in the analog neural network 106, and weights applied thereto, process the inputted analog signals, the analog neural network 106 will output an analog signal. If the analog signal that is output is not the desired output, the weights applied to the neurons are adjusted so that the analog neural network 106 outputs a desired analog signal.”
The weights being adjusted if the analog signal is not the desired signal shows that when there is a desired signal the neural network is trained.
Also in ¶ [0046], Himebaugh states, “in embodiments, the digital processor 108 may also update the configured weights 118 and/or the weights loaded onto the analog neural network 106 during training loops, which could be implemented with a feedback loop from the digital processor 108 and a multiplexer (see FIG. 2, 128) on one or more inputs (see FIG. 2, 130) of the analog neural network 106.”
The said training loops that affect the analog and digital components of the neural network are interpreted as training the neural network.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch, Moradi, and Lehmann with Himebaugh in order to train the neural network with the analog arrays and a digital processor. “In general, the analog neural network consumes less power than the digital processing device. In some circumstances, however, a system may need the processing power of the digital processor. As such, it is sometimes advantageous for the analog neural network to be operating while the digital processor is in a lower-power state and it is sometimes advantageous for the digital processor to operate in a higher-power state to perform processing functions” (Himebaugh, [0026]).
Regarding Claim 14:
As discussed above, Busch, Moradi, and Lehmann teach [the] computer-implemented method of claim 7, but do not explicitly disclose:
wherein the plurality of digital circuitry and the plurality of analog arrays are co-trained together from a beginning of the neural network
However, in the same field, analogous art Himebaugh teaches:
wherein the plurality of digital circuitry and the plurality of analog arrays are co-trained together from a beginning of the neural network
Himebaugh, [0042], “After the neurons included in the analog neural network 106, and weights applied thereto, process the inputted analog signals, the analog neural network 106 will output an analog signal. If the analog signal that is output is not the desired output, the weights applied to the neurons are adjusted so that the analog neural network 106 outputs a desired analog signal.”
The weights being adjusted if the analog signal is not the desired signal shows that when it is the desired signal the neural network is trained from the beginning.
Also in [0046], Himebaugh states, “in embodiments, the digital processor 108 may also update the configured weights 118 and/or the weights loaded onto the analog neural network 106 during training loops, which could be implemented with a feedback loop from the digital processor 108 and a multiplexer (see FIG. 2, 128) on one or more inputs (see FIG. 2, 130) of the analog neural network 106.”
The said training loops that affect the analog and digital components of the neural network is interpreted as being trained together from the beginning of the neural network.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch, Moradi, and Lehmann with Himebaugh in order to train the neural network with the analog arrays and a digital processor. “In general, the analog neural network consumes less power than the digital processing device. In some circumstances, however, a system may need the processing power of the digital processor. As such, it is sometimes advantageous for the analog neural network to be operating while the digital processor is in a lower-power state and it is sometimes advantageous for the digital processor to operate in a higher-power state to perform processing functions” (Himebaugh, [0026]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Busch and Moradi in view of Lehmann, and further in view of Jantscher et al. (US 20220309331), hereinafter Jantscher.
Regarding Claim 15:
As discussed above, Busch, Moradi, and Lehmann teach [the] computer-implemented method of claim 7, and Moradi teaches:
co-train the plurality of analog arrays and the plurality of digital circuitry to run the neural network
Moradi, pg. 1, col. 2, “In this specific scenario, this suggests the design of full custom analog/digital Very Large Scale Integration (VLSI) neuromorphic systems.”
Pg. 2, col. 1, “By including the VLSI device in the training loop, the circuit non-idealities and variability can be potentially adapted away through the PC-based learning algorithms. Once the network has been trained and the synaptic weight values stored in the SRAM, the VLSI device can be used in stand-alone mode to carry out neural computation in real-time, exploiting its low-power, and compact size properties.”
On pg. 1, col. 2, Moradi discloses a custom analog/digital VLSI neuromorphic system. The analog/digital VLSI is construed as Moradi disclosing a plurality of digital circuitry and a plurality of analog arrays. Further on pg. 2, col. 1, Moradi discloses that the VLSI device is used in training neural networks [co-trained the plurality of analog arrays and the plurality of digital circuitry to run the neural network]. Putting it together, Moradi is construed as disclosing a custom, hybrid analog/digital VLSI device used for training neural networks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch with Moradi to concurrently perform the digital and analog computations in order to achieve reasonable computation times and use less energy. “In order to apply this computational paradigm to compact efficient neural processing and sensory-motor systems, that compute on real-world sensory signals and interact with the environment in real-time, it is necessary to develop dedicated hardware implementations of spiking neural networks which are low-power and can operate with biologically plausible time-constants” (Moradi, pg. 1, col. 2).
Busch, Moradi, and Lehmann do not explicitly disclose:
detecting that the neural network has been generated and trained with a set of digital circuitry
transferring the neural network to the plurality of the analog arrays in response to detecting that the neural network has been generated
However, in the same field, analogous art Jantscher teaches:
detecting that the neural network has been generated and trained with a set of digital circuitry
Jantscher, [0073], “At the first step 202, the system loads weights of a trained digital neural network into the analog neural network implemented in the analog neural network chip. The digital neural network is a simulated version of the analog neural network (e.g., the digital neural network has the same architecture as the analog neural network) and has been trained on a particular machine learning task that the analog neural network is configured to perform.”
Jantscher discloses loading weights of a trained digital network. This corresponds to the claimed language because Jantscher’s system determined a trained digital neural network [detecting that the neural network has been generated and trained with a set of digital circuitry] in order to load its weights.
transferring the neural network to the plurality of the analog arrays in response to detecting that the neural network has been generated
As cited above in para. 73, Jantscher discloses loading the digital weights into the analog neural network from the digital neural network [transferring the neural network to the plurality of analog arrays in response to detecting that the neural network has been generated].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch, Moradi, and Lehmann with Jantscher in order to increase the speed of production testing of analog neural networks. “Thus, the techniques described herein does not require any measurements of physical properties of chip components or hardware-in-the-loop training. As a result, the described techniques can increase the speed of production testing of analog neural network chips, thereby allowing for mass production of analog neural network chips. In addition, the described techniques can simplify equipment needed for production testing as no analog measurements are needed for error compensation. Further, using the described techniques, the speed of device characterization process during production and adaptation of the trained analog neural network for each chip using retraining techniques can be increased” (Jantscher, [0048]).
Response to Arguments
Applicant's arguments filed 11-6-2025 (“Remarks”) have been fully considered but they are not persuasive.
Applicant’s arguments filed 11-6-2025, with respect to the rejections of claims 1, 7, and 16 in view of the limitations involving “intermittently connecting” under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Lehmann ("Teaching Pulsed Integrated Neural Systems: A Psychobiological Approach").
35 U.S.C. § 103:
Remarks, pg. 10-11. Applicant’s arguments regarding Busch’s digital layer connection and the claim limitations involving “intermittently connecting” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Remarks, pg. 11. Applicant argues Busch’s digital layer does not connect or activate with respect to any specific neurons or connections of neurons that are associated with an inaccuracy. Examiner respectfully disagrees with Applicant’s claim interpretation. As stated by Applicant, Busch’s digital layer corrects the neural network when an incorrect decision has been made. Busch reads on the claimed limitation because Busch discloses correcting [to correct] all of the nodes and connections of the neural network [one or more of the synaptic weights of one or more connections of the one or more neurons] by the digital layer when an inaccurate output caused by weight drifts is identified [responsive to determining that the one or more synaptic weights of the one or more connections are associated with an inaccuracy]. More specifically, Busch retraining ‘all’ the neurons still reads under ‘one or more’ of the neurons.
Remarks, pgs. 11-12. Applicant argues one of ordinary skill in the art would understand training takes place in a training phase, not a production environment, and that Busch does not teach or suggest a pre-training step as occurring in a production environment, and thus Busch fails to teach when the digital circuitry is in a production environment. Examiner respectfully disagrees. It is unclear how Busch would need to teach pre-training as occurring in production in order to more applicably read on the claim limitation since Busch does not disclose any pre-training. Furthermore, as stated by Applicant in the Remarks, one of ordinary skill would understand inference to take place during an inference phase/production environment. Therefore, under broadest reasonable interpretation, Busch teaches the claimed limitation.
Remarks, pg. 12. As discussed above, Applicant’s arguments regarding “intermittently connecting” have been fully considered and are persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.H.P./Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
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