Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 16, 2026 has been entered.
Response to Amendment
In the previous Office Action issued February 3, 2026 (hereinafter “the previous Office Action”), claims 1, 4-7, 10-16, and 19-20 were pending.
This action is in response to the amendment and remarks filed March 16, 2026. In the amendment, claims 1, 4-5, 7, 10-11, 16, and 19-20 were amended, claims 6, 12, and 14-15 were canceled, claims 2-3, 8-9, and 17-18 were previously canceled, and no claims were added. Thus, claims 1, 4-5, 7, 10-11, 13, 16, and 19-20 are pending.
The rejections of claims 1, 4-7, 10-16, and 19-20 under 35 U.S.C. § 112(b), set forth in the previous Office Action, have been withdrawn in view of Applicant’s amendments and remarks.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-5, 7, 10-11, 13, 16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Busch et al. (US 20190034790), hereinafter Busch, in view of Moradi et al. ("An Event-Based Neural Network Architecture with an Asynchronous Programmable Synaptic Memory"), hereinafter Moradi, further in view of Lee et al. ("Intermittent Learning: On-Device Machine Learning on Intermittently Powered System"), hereinafter Lee, and further in view of Himebaugh et al. (US 20160328642), hereinafter Himebaugh.
Regarding Claim 1:
Busch discloses:
A system comprising:
Busch, [0002], “embodiments of the disclosure relate to, but are not limited to, systems and methods for partial digital retraining of artificial neural networks disposed in analog multiplier arrays of neuromorphic integrated circuits.”
a plurality of analog arrays that comprise all synaptic weights of a neural network
Busch, [0015], “disclosed herein is a neuromorphic integrated circuit including, in some embodiments, a multi-layered analog-digital hybrid neural network…[the] neural network includes a number of analog layers configured to include synaptic weights between neural nodes of the neural network for decision making by the neural network.”
In para. 15, Busch discloses a neural network including a number of analog layers [a plurality of analog arrays] which includes the neural network’s synaptic weights [comprise all synaptic weights of a neural network]. The analog layers correspond to the analog arrays because, as cited above in 2, the analog layers are disclosed to be analog multiplier arrays [analog arrays].
responsive to determining that one or more synaptic weights of one or more connections are associated with an inaccuracy and…
Busch, [0057], “weight drifts occurring via electrostatic discharge from the cells can cause the number of analog layers of the hybrid neural network 500 to begin to arrive at incorrect decisions…When the incorrect decisions of the hybrid neural network 500 become known, the digital layer of the hybrid neural network 500 can be programmed through a partial digital retraining process to correct or compensate for the weight drifts, which allows the hybrid neural network 500 to arrive at correct decisions…”
Busch discloses that when incorrect decisions of the neural network become known [responsive to determining that one or more synaptic weights of one or more connections are associated with an inaccuracy].
connecting the plurality of activated digital circuitry to one or more neurons within the neural network when the neural network is in a production environment to correct one or more of the synaptic weights of one or more connections to the one or more neurons
Busch, [0063], “decision making by the hybrid neural network 500 can include predicting discrete classes for one or more classification problems. The digital layer through its configuration for programmatically compensating for weight drifts of the synaptic weights of the hybrid neural network 500 is, thus, further configured to maintain a correctly projected decision boundary for predicting the discrete classes by the hybrid neural network 500.”
In para. 57, cited above, and further in view of para. 63 Busch discloses using the digital layer(s) of the neural network to correct or compensate for weight drifts [connecting the plurality of activated digital circuitry to one or more neurons within the neural network…to correct one or more of the synaptic weights of one or more connections to one or more neurons] in order to maintain correct decision boundaries for predicting discrete classes in classification problems [when the neural network is in a production environment]. The hybrid neural network being used to predict classes for one or more classification problems is interpreted as a production environment because both refer to situations in which the neural network/model are providing classifications/outputs/predictions as opposed to training the neural network/model.
Busch does not explicitly disclose:
a plurality of digital circuitry that are concurrently co-trained along with the plurality of analog arrays in generating the neural network
…an energy consumption of the neural network is below a threshold
activating one or more of the plurality of digital circuitry by providing power to the one or more of the plurality of digital circuitry
However, in the same field, analogous art Moradi teaches:
a plurality of digital circuitry that are concurrently co-trained along with the plurality of analog arrays in generating the neural network
Moradi, pg. 1, col. 2, “In this specific scenario, this suggests the design of full custom analog/digital Very Large Scale Integration (VLSI) neuromorphic systems.”
Pg. 2, col. 1, “By including the VLSI device in the training loop, the circuit non-idealities and variability can be potentially adapted away through the PC-based learning algorithms. Once the network has been trained and the synaptic weight values stored in the SRAM, the VLSI device can be used in stand-alone mode to carry out neural computation in real-time, exploiting its low-power, and compact size properties.”
Pg. 2, col. 2, “The architecture of the chip is illustrated in Fig. 1. It comprises five main blocks: the asynchronous controller…The asynchronous controller manages the communication between the external digital asynchronous signals and the on-chip ones.”
On pg. 1, col. 2, Moradi discloses a custom analog/digital VLSI neuromorphic system. The analog/digital VLSI is construed as Moradi disclosing a plurality of digital circuitry and a plurality of analog arrays. Further on pg. 2, col. 1, Moradi discloses that the VLSI device is used in training neural networks [co-trained…in generating the neural network]. Lastly, pg. 2, col. 2 discloses the chip architecture includes an asynchronous controller that manages asynchronous communication [concurrently] between the digital signals [digital] and the on-chip signals [analog]. Putting it together, Moradi is construed as disclosing a custom, hybrid analog/digital VLSI device used for training neural networks, and the chip architecture includes an asynchronous controller that manages asynchronous communication between the digital and analog signals.
Busch, Moradi, and the instant application are analogous art because they are all directed to neural networks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch with Moradi to concurrently perform the digital and analog computations in order to achieve reasonable computation times and use less energy. “In order to apply this computational paradigm to compact efficient neural processing and sensory-motor systems, that compute on real-world sensory signals and interact with the environment in real-time, it is necessary to develop dedicated hardware implementations of spiking neural networks which are low-power and can operate with biologically plausible time-constants” (Moradi, pg. 1, col. 2).
Busch in view of Moradi do not explicitly disclose:
…an energy consumption of the neural network is below a threshold
activating one or more of the plurality of digital circuitry by providing power to the one or more of the plurality of digital circuitry
However, in the same field, analogous art Lee teaches:
…an energy consumption of the neural network is below a threshold
Lee, p. 11 “Figure 5 shows that when the dynamic action planner decides to launch a learn action, each of them layers of the original neural network {l1,l2,...,lm} gets executed sequentially in the forward direction (feed-forward) and then in the backward direction (back-propagation) to complete one cycle of learning. The system continues to execute each layer li as long as the current energy level is higher than required. Once a cycle is completed, the dynamic action planner gets back the control and chooses the next action.”
Lee teaches continuing the execution of the neural network as long as the current energy level is higher than required [determining that… an energy consumption of the neural network is below a threshold]. This corresponds to the claimed language because both refer to a scenario in which the energy consumption/level is determined for neural network processing.
Busch, Moradi, Lee, and the instant application are analogous art because they are all directed to neural networks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch and Moradi with Lee because “To complement and advance the state-of-the-art of the batteryless machine learning systems, we propose the intermittent learning framework which explicitly takes into account the dynamics of a machine learning task, in order to improve the energy and learning efficiency of an intermittent learner in a systemic fashion.” (Lee, p. 4).
Busch in view of Moradi, further in view of Lee do not explicitly disclose:
activating one or more of the plurality of digital circuitry by providing power to the one or more of the plurality of digital circuitry
However, in the same field, analogous art Himebaugh teaches:
activating one or more of the plurality of digital circuitry by providing power to the one or more of the plurality of digital circuitry
Himebaugh, [0032], “Using the analog signals, the analog neural network 106 determines whether an event of interest has been sensed by the sensors 102, 104. Further, the analog neural network 106 outputs an analog signal indicative of whether an event of interest has been sensed by the sensors 102, 104. If the analog neural network 106 determines an event of interest has been sensed by the sensors 102, 104, the analog signal output by the analog neural network 106 is sent to the digital processor 108, which initiates an activation of the digital processor 108 from a lower-power state to a higher-power state.”
Himebaugh teaches determining analog signals that correspond to events of interest, and then activating the digital processor from a lower-power state to a higher-power state [activating one or more of the plurality of digital circuitry by providing power to the one or more of the plurality of digital circuitry].
Busch, Moradi, Lee, Himebaugh, and the instant application are analogous art because they are all directed to neural networks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch, Moradi, and Lee with Himebaugh to activate in response to an energy criterion in order to operate in an energy efficient manner. “In embodiments, the analog neural network 106 may determine whether an event of interest has occurred and output corresponding analog signals continuously or near continuously, which allows the digital processor 108 to remain inactive or otherwise in a low-power state until an event of interest has been determined. As such, devices that incorporate the system 100 therein operate in an energy efficient manner thus increasing implementation possibilities, extending device battery life and providing other benefits” (Himebaugh, [0043]).
Regarding Claim 4:
As discussed above, Busch, Moradi, Lee, and Himebaugh teach [the] system of claim 1, and Busch further discloses:
wherein the connecting is performed responsive to detecting that the analog arrays have failed a performance criterion
Busch, [0057], “incorrect decisions can be tested for on a periodic basis with test data…such as generated test data provided by a test data generator. When the incorrect decisions of the hybrid neural network 500 become known, the digital layer of the hybrid neural network 500 can be programmed through a partial digital retraining process to correct or compensate for the weight drifts”
Busch discloses using the digital layer of the hybrid neural network [connecting is performed responsive to] when incorrect decisions of the hybrid neural network become known [detecting that the analog arrays have failed a performance criterion].
Regarding Claim 5:
As discussed above, Busch, Moradi, Lee, and Himebaugh teach [the] system of claim 1, and Busch further discloses:
wherein the connecting is performed responsive to detecting that a waiting period has elapsed
Busch, [0057], “incorrect decisions can be tested for on a periodic basis with test data…such as generated test data provided by a test data generator. When the incorrect decisions of the hybrid neural network 500 become known, the digital layer of the hybrid neural network 500 can be programmed through a partial digital retraining process to correct or compensate for the weight drifts”
[0066], “The test data generator can be configured to generate the test data for testing with any desired frequency including, but not limited to, once an hour or once a day for measuring an accuracy of the hybrid neural network 500 and subsequent partial digital retraining, if needed.”
In para. 57, Busch discloses periodically using the digital layer to correct or compensate for weight drifts when incorrect decisions become known. Incorrect decisions are known based on incorrect decisions made based on test data, and para. 66 specifies that the test generator can perform testing for any desired period of time such as once an hour or once a day [in response to a waiting period elapsing].
Regarding Claim 7:
Claim 7 is a computer-implemented method claim corresponding to system claim 1 and is rejected for at least the same reasons as given in the rejection of claim 1, with the exception of the following limitations.
Busch discloses:
A computer-implemented method comprising:
Busch, [0002], “embodiments of the disclosure relate to, but are not limited to, systems and methods for partial digital retraining of artificial neural networks disposed in analog multiplier arrays of neuromorphic integrated circuits.”
training a plurality of analog arrays that comprise all synaptic weights of a neural network
Busch, [0015], “disclosed herein is a neuromorphic integrated circuit including, in some embodiments, a multi-layered analog-digital hybrid neural network…[the] neural network includes a number of analog layers configured to include synaptic weights between neural nodes of the neural network for decision making by the neural network.”
In 15, Busch discloses a neural network including a number of analog layers [a plurality of analog arrays] which includes the neural network’s synaptic weights [comprise all synaptic weights of a neural network]. The analog layers correspond to the analog arrays because, as cited above in 2, the analog layers are disclosed to be analog multiplier arrays [analog arrays].
[0045], “FIG. 1 illustrates a system 100 for designing and updating neuromorphic integrated circuits (“ICs”) is provided in accordance with some embodiments…updating neuromorphic ICs can include creating a machine learning architecture with the simulator 110 based on a particular problem…While the initially fabricated neuromorphic IC 102 can include an initial firmware with custom synaptic weights between the neural nodes, the initial firmware can be updated as needed by the cloud 130 to adjust the weights.”
In para. 45, Busch further discloses designing and updating the neuromorphic ICs which includes adjusting the weights of the neuromorphic IC as needed. This corresponds to claimed language of training because training consists of adjusting weights to ‘teach’ the neural network to solve a particular machine learning problem as disclosed by Busch.
Regarding Claims 10-11:
Claims 10-11 are method claims corresponding to system claims 4-5 and are rejected for at least the same reasons as given in the rejection of claim 4-5. In particular, 10:4, 11:5.
Regarding Claim 13:
As discussed above, Busch, Moradi, Lee, and Himebaugh teach [the] computer-implemented method of claim 7, and Himebaugh further discloses:
further comprising detecting that the plurality of analog arrays has been trained within the neural network, wherein the plurality of digital circuitry is co-trained in response to detecting that the plurality of analog arrays has been trained
Himebaugh, [0042], “After the neurons included in the analog neural network 106, and weights applied thereto, process the inputted analog signals, the analog neural network 106 will output an analog signal. If the analog signal that is output is not the desired output, the weights applied to the neurons are adjusted so that the analog neural network 106 outputs a desired analog signal.”
The weights being adjusted if the analog signal is not the desired signal shows that when there is a desired signal the neural network is trained.
[0046], “in embodiments, the digital processor 108 may also update the configured weights 118 and/or the weights loaded onto the analog neural network 106 during training loops, which could be implemented with a feedback loop from the digital processor 108 and a multiplexer (see FIG. 2, 128) on one or more inputs (see FIG. 2, 130) of the analog neural network 106.”
The said training loops that affect the analog and digital components of the neural network are interpreted as training the neural network.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Busch, Moradi, Lee, and Himebaugh further with Himebaugh in order to train the neural network with the analog arrays and a digital processor. “In general, the analog neural network consumes less power than the digital processing device. In some circumstances, however, a system may need the processing power of the digital processor. As such, it is sometimes advantageous for the analog neural network to be operating while the digital processor is in a lower-power state and it is sometimes advantageous for the digital processor to operate in a higher-power state to perform processing functions” (Himebaugh, [0026]).
Regarding Claim 16:
Claim 16 is a system claim corresponding to method claim 7 and is rejected for at least the same reasons as given in the rejection of claim 7, with the exception of the following limitations.
Busch discloses:
A system comprising: a processor; and a memory in communication with the processor, the memory containing instructions that, when executed by the processor, cause the processor to:
Busch, [0002], “embodiments of the disclosure relate to, but are not limited to, systems and methods for partial digital retraining of artificial neural networks disposed in analog multiplier arrays of neuromorphic integrated circuits.”
[0039], “Examples of such circuitry may include, but are not limited or restricted to…one or more processor cores…semiconductor memory”
In para. 2, Busch discloses a system, and 39 discloses a processor and memory.
Regarding Claims 19-20:
Claims 19-20 system claims corresponding to system claims 4-5 and is rejected for the same reasons as given in the rejection of claims 4-5. In particular, 19:4, 20:5.
Response to Arguments
Applicant's arguments filed March 16, 2026 (“Remarks”) have been fully considered but they are not persuasive.
35 U.S.C. § 103:
Remarks, p. 8, Applicant argues with respect to the independent claims that the references cited (Busch, Moradi, Lehmann, and Himebaugh) do not teach the claim limitations (1) responsive to a power consumption and (2) activating the digital circuitry.
Regarding (1), Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding (2), Examiner respectfully disagrees. As discussed in detail under the 103 rejections, Himebaugh explicitly discloses activating digital processors from a lower power state to a higher power state.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN PHUNG whose telephone number is (703) 756-1499. The examiner can normally be reached Monday-Thursday: 9:00AM-4:00PM ET.
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/STEVEN PHUNG/Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
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