DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/18/2026 has been entered.
Response to Amendment
This office action is responsive to amendment filed on 05/04/2026. Claims 1, 3, and 8-10 are pending.
Response to Arguments
In respond to rejection 35 U.S.C. 112(a) on Remarks page 4-5, Applicant asserted “claim 1 is amended to comply with the written description requirement. Specifically, the “generating” step is corrected.”
Examiner respectfully disagrees because the amended claim does not comply with the written description requirement under 112(a) as explained in the rejection below. Furthermore, Examiner requests applicant to use the specification as filed when citing support for the amended claims (such as page and line number), instead of using paragraph numbers from the publication as the specification as filed does not include the corresponding paragraph numbers.
In respond to applicant’s argument regarding rejection 35 U.S.C. 101 on Remarks page 5, “The amended claims recite a Physically Unclonable Function (PUF) method that increases the number of usable path delays on a chip by applying a server-generated linear transformation to the chip's delay characteristics, thereby generating an expanded path delay distribution. This expanded distribution enables the generation of additional, distinct authentication bitstrings, improving the security of device-server authentication.”
Examiner respectfully disagrees because any arguably improvement, such as increases the number of usable path delays and expanded distribution, are a direct consequence of performing the abstract idea, such as selecting a set of path delays and perform a sequence of mathematical operations, including linear transformation in specification page 12 line 22 – page 13 line 1, also see figure 1 right side. MPEP 2106.05(I) “a claim for a new abstract idea is still an abstract idea” and MPEP 2106.05(a) states “it is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements”). In other words, the expanded path delay distribution is obtained by performing a linear transformation to generate a set of offset values and adding the offset values to the path delay to generate the expanded path delay distribution that increases the number of path delays for generating bitstrings, and as stated above in MPEP 2106.05(a), the judicial exception [i.e., the bitstring generation process that includes linear transformation and adding offset values] alone cannot provide the improvement. Moreover, the limitation of applying a server-generated linear transformation to the chip’s delay characteristics is not recited in the claim as MPEP 2106.04(d)(1) states “the claim must be evaluated to ensure that the claim itself reflects the disclosed improvement.” Accordingly, if the improvement is from applying linear transformation to the chip’s delay characteristics, then such limitation needs to be recited in the claim to reflects the disclosed improvements.
Applicant further asserted on page 5, “These amendments clarify that the invention is rooted in hardware, solves a hardware-specific technical problem, and provides a technical security improvement. Under the USPTO's 2019 Revised Patent Subject Matter Eligibility Guidance, such claims are not abstract.”
Examiner respectfully disagrees because the invention is not rooted in hardware, but rather rooted in mathematical operation, such as applying the sequence of mathematical operations to expand the path delay distribution to provide expand the path delay distribution. The PUF and security device-server authentication is recited at most as mere generally linking the use of the judicial exception into a particular technological environment or field of use.
Applicant further asserted that the claimed invention provide an improvement to PUF chip on page 5-6 by increasing the number of CRPs, thereby improving entropy, unpredictability, resistance to modeling attacks, and overall authentication robustness.
Examiner respectfully disagrees because as explained above, any arguably improvement is a direct result of performing the mathematical operations of creating path delay distribution and modify it to generate expanded path delay distribution by performing a sequence of mathematical operations.
Applicant further asserted on page 6, “The claimed operations are not well-understood, routine, or conventional. Modifying physical PUF delay characteristics using an expanded path delay distribution, or producing different bit values from the same physical path delay are routine or conventional. These steps are non-conventional and non-routine in the field of PUF-based authentication. The claims recite a specific, ordered sequence of technical operations. The claims do not merely recite a result. They require using distributions of a chip's measured path delays to construct authentication bitstrings. Using an expanded path delay distribution increases a number of challenge-response pairs (CRPs) available for PUF-based authentication.”
Examiner respectfully disagrees because the operations are not well-understood, routine, or conventional are the mathematical operations, such as modifying the path delay distribution to generate expanded path delay distribution and generate bitstring as the specification page 12 describes such operations to generate bitstring is done by performing a sequence of mathematical operation includes applying linear transformation. MPEP 2106.04(I) “The Supreme Court’s decisions make it clear that judicial exceptions need not be old or long-prevalent, and that even newly discovered or novel judicial exceptions are still exceptions” and MPEP 2106.05(I) “a claim for a new abstract idea is still an abstract idea”. Accordingly, the specific ordered sequence operations are non-conventional and non-routine, such operations are still an abstract idea.
Applicant further asserted on page 7, “The invention produces a new, hardware-based security capability. The expanded path delay distribution enables the generation of additional CRPs, which increases authentication capacity, enhances unpredictability, and strengthens cryptographic security. Such improvements constitute an inventive concept. The amended claims are directed to a specific technological improvement in PUF-based authentication systems, are not abstract, and recite significantly more than any alleged abstract idea.”
Examiner respectfully disagrees because as explained above, any arguably improvement is a result of performing the abstract idea to generate the expanded path delay distribution. Furthermore, the limitation of increasing the number of CRPs available for PUF-based authentication recited in the amended claim is at most considered as a result of performing the abstract idea or mere generally linking the use of the judicial exception into a particular technological environment or field of use, such as PUF (see MPEP 2106.05(h)).
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 3, and 8-10 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 line 24-26 recites “constructing, by the server, a bitstring from the path delays of the path delay distribution and the path delays of the expanded path delay distribution, wherein the same path delay that is a member of both the path delay distribution and the expanded path delay distribution generates different bit values for the bitstring”. Examiner is unable to find support for the limitation that construct a bitstream using both the path delays of the path delay distribution and the expanded path delay distribution in the specification because figure 1 page 5 describes the HELP bitstring generation algorithm and page 15-16 ([0049] published application) describes a technique referred to as DHD scheme that further describes the generation of bitstring by either the token or verifier based on modPNDco (e.g., the expanded path delay distribution). Furthermore, page 9 ([0021] published application) also describes the token and verifier add the offset to the path delays before computing the corresponding bit, wherein page 15 ([0047] published application) describes offsets are added to modPNDc to generate modPNDco (e.g., expanded path delay distribution). However, the claim requires the bitstring (e.g., one bitstring) generated from the path delays of path delay distribution and the path delays of the expanded path delay distribution (e.g., both distributions). Accordingly, from the at least cited sections above, the specification fails to provide sufficient description of the claimed limitation in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 10 recites “a path delay that is included in two distributions, which have different means and ranges, generates a different bit value in the bitstring”. However, as explained above, Examiner is unable to find support for the limitation that two distributions is used to generate a single bitstring. The closest description found on page 7 first paragraph describes a fixed path delay that is a memory of two different distributions, with different mean and range values, will have different standardized values, which can generate different bit value, but the specification does not describe such different bit value generated is for the same bitstring or the single bitstring. Page 23 second paragraph describes different distributions for bitstring generation step and also describes “for uchip shifts equal to the Modulus, the exact same bitstring is generated by both distributions”, at most such recitation is interpreted as two same bitstrings are generated by both distributions, but does not describe using two distributions to generate a single bitstring. Accordingly, the specification fails to provide sufficient description for the claimed limitation.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 line 4 recites “the chip”. It is unclear whether the chip is referring the chip recited in claim 1 line 2 or the chip recited in claim 1 line 5-6. For examination purposes, examiner interprets as the chip recited in claim 1 line 2.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3 and 8-10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Claim 1 recites a PUF method for using path delays to generate bitstrings for authentication between a device and a server.
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites limitations cover mathematical calculations, relationship, and/or formula, such as changing one or more path delays of the path delay distribution with path delays selected from the group (see at least figure 2 describing the TVCOMP process, which is a mathematical process and page 17 describes the modifying one or more path delays. Thus, changing is part of the mathematical manipulation of path delay data as page 12 describes, once the path delay are selected a sequence of mathematical operations are applied to produce bitstring data); constructing a bitstring from the path delays of the path delay distribution and the path delays of the expanded path delay distribution, wherein the same path delay that is a member of both the path delay distribution and the expanded path delay distribution generates different bit values for the bitstring (see figure 1 illustrates step bit generation to generate bitstring. Page 12 describe once the PN (e.g., path delays) are collected, a sequence of mathematical operations is applied to produce the bitstring. Page 15-16 further describes the mathematical method to generate bitstring using comparison operation, see page 24 line 13-14 describes the bit can change based on number of u and Rng). Furthermore, the claim also recites limitation that under BRI cover the performance of using pen and paper, such as creating a path delay distribution by selecting the path delays from the group (see page 6 describes step of selecting a set of k paths). Therefore, the claim includes limitations that fall within the “Mathematical Concepts/ Mental processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a device, a server, a chip, a secure database. However, the additional elements are recited at a high level of generality, i.e., as computer components performing computer functions of processing data and storing data. The claim further recites storing a group of path delays from a chip of a device, such step of storing is at most considered as insignificant extra solution activities because it is merely recited as data gathering. The claim further recites thereby creating an expanded path delay distribution that increases a number of challenge-response pairs (CRPs) available for PUF-based authentication, such limitation is merely recited as a result of performing the mathematical operations as recited in the claim. Furthermore, the claim recites the PUF method for authentication between device and the server, such limitation is at most considered as mere generally linking the use of the judicial exception into a particular technological environment or field of use, such as authentication. Accordingly, the additional elements in combination fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to the step 2A prong two, the additional elements in the claim amount to no more mere instructions to apply the exception, and the step of storing data is determined to be well-understood, routine and conventional (see MPEP 2106.05(d)(II)(iv) storing and retrieving information in memory). Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 3 further recites the path delay distribution depends on lengths of the path delays selected. Such limitation merely describes the dependency of the path delay distribution to the length of the path delays and at most is considered as describing the data (e.g., path delay distribution) to be operated on the mathematical operation. Thus, such limitation covers mathematical calculations, relationship. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 8 further recites the definition of the path delays of both the path delay distribution and the expanded path delay distribution as the amount of time for set of 0 to 1 and 1 to 0 transition introduced on primary inputs of the chip to propagate through a logic gate network and emerge on a primary output. Such limitation merely describes the data, such as the path delays, to be operated on the mathematical operations to generate bitstring. Thus, such limitation covers mathematical calculations, relationship. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 9 further recites wherein each path delay of each distribution is a difference value between a rising path delay and a falling path delay, such limitation covers mathematical calculations, relationship, and/or formula (such as performing subtraction to calculate the difference value). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 10 further recites wherein a path delay that is included in two distributions, which have different means and ranges, generates a different bit value in the bitstring, such limitation covers mathematical calculations, relationship, and/or formula (merely describes the data within two distributions to have means and ranges to generate bitstream as described in equations 1-2). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Conclusion
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
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