DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to amendment filed on 10/09/2025. Claims 1-3, and 6-8 are pending. The amendment has overcome the claim objection and rejection under 35 U.S.C. 112(b) as set forth in previous office action.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-3 and 6-8 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 line 20-21 recites “generating, by the server, a bitstring from a comparison of the path delays of the path delay distribution”. Examiner is unable to find support for such limitation in the specification because page 15-16 ([0049] published application) describes a second technique referred to as DHD scheme that further describes the generation of bitstring by either the token or verifier based on modPNDco, which is the expanded path delay distribution. Furthermore, page 9 ([0021] published application) also describes the token and verifier add the offset to the path delays before computing the corresponding bit, wherein page 15 ([0047] published application) describes offsets are added to modPNDc to generate modPNDco (e.g., expanded path delay distribution). However, the claim requires the bitstring generated by the server is from a comparison of the path delay distribution, which is the distribution without adding the offset values. Accordingly, from the at least cited sections above, the specification fails to provide sufficient description the limitation of generating, by the server, a bitstring from a comparison of the path delays of the path delay distribution in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Response to Arguments
In respond to applicant’s argument regarding rejection 35 U.S.C. 101 on Remarks page 8, “Applicant’s invention is not an abstract idea, a mathematical concept, a method of organizing human activity, or a mental process. The server computes a set of offsets that are used to fine tune the device’s digitized path delays as a means of maximizing entropy and reproducibility in the generated bitstrings. (p. 4, lines 23-24). The offsets are derived from data stored by the server. (p. 4, lines 24-25). Specifically, the linear transformation according to the invention is used for dealing with changes in delay introduced by adverse temperature-voltage (environmental) variations. (p. 4, lines 11-13).”
Examiner respectfully disagrees because the claimed invention recites limitation that cover the mathematical concept / mental processes groupings of the abstract idea as analyzed under step 2A prong one, such as calculating mean value and range value, applying linear transformation that includes the steps of subtracting and dividing to generate offset values, and adding offset values to obtain an expanded path delay distribution and generating bitstrings. Furthermore, page 12 line 22-23 explicitly recites, once the path delay (e.g., PN) are selected, a sequence of mathematical operations are applied as shown on the right side of fig. 1 to produce the bitstring. Accordingly, the claimed invention recites mathematical concept. Moreover, MPEP 2106.04(a)(2)(III)(C) recites “Claims can recite a mental process even if they are claimed as being performed on a computer … if the claimed invention is described as a concept that is performed in the human mind and applicant is merely claiming that concept performed 1) on a generic computer, or 2) in a computer environment, or 3) is merely using a computer as a tool to perform the concept”. Thus, even though the claimed invention recites a device and a server to implementing the method, such computer components are recited at a high level of generality, merely performing the concept on generic computers that amount to no more than mere instructions to apply the judicial exception using computer elements (also see MPEP 2106.05(f)).
Applicant further asserted on page 8, “More specifically, bitstrings … An advantage of the Applicant’s invention is to expand the number of path delays that can be compared to produce bitstrings, which expands the challenge-response space dramatically”, and on page 6 line 18-20.
Examiner respectfully disagrees because any arguably improvement, such as expanding the number of path delays and expand the challenge-response space dramatically, are a direct consequence of performing the abstract idea, such as selecting a set of path delays and perform a sequence of mathematical operations as recited in the claims and described in specification page 12 line 22 – page 13 line 1, also see figure 1 right side. MPEP 2106.05(I) “a claim for a new abstract idea is still an abstract idea” and MPEP 2106.05(a) states “it is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements”). In other words, the expanded path delay distribution is obtained by performing a linear transformation to generate a set of offset values and adding the offset values to the path delay to generate the expanded path delay distribution that increases the number of path delays for generating bitstrings as recited in claim 1 and as stated above in MPEP 2106.05(a), the judicial exception [i.e., the bitstring generation process that includes linear transformation and adding offset values] alone cannot provide the improvement.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3 and 6-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Claim 1 recites a PUF method for increasing a number of path delays for generating bitstrings used for authentication between a device and a server.
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites limitations cover mathematical calculations, relationship, and/or formula, such as calculating both a mean value and a range value of the path delay distribution (see page 6 line 20 first computes the mean and range of the distribution, page 13 describes a histogram distribution of the 2048 PND is created and parsed to obtain its mean and range parameters); apply a linear transformation to the path delay distribution, wherein the linear transformation comprises the steps of subtracting the mean value from each path delay of the path delay distribution and dividing each path delay of the path delay distribution by the range value to provide a set of offset values from each path delay (see page 6 step of applying a linear transformation, also page 6 describes after the step of selecting, a series of simple mathematical operations are being performed on the path delays. Also see page 13 equation 1); adding the set of offset values to the path delays to shift the path delay distribution to obtain an expanded path delay distribution (page 9 describes the step of adding the offset values to the path delays, and page 15 line 5 describes offsets are added to PNDc to produce PNDco, page 25 line 11-12 describes offset method to shift individual PNDc); and generating a bitstring from a comparison of the path delays of the path delay distribution; generating a bitstring from a comparison of the path delays of the expanded path delay distribution, wherein the same path delay of both the path delay distribution and the expanded path delay distribution, when used for the comparisons, generates different bit values for each bitstring (see figure 1 illustrates step bit generation to generate bitstring. Page 12 describe once the PN (e.g., path delays) are collected, a sequence of mathematical operations is applied to produce the bitstring. Page 15-16 further describes the mathematical method to generate bitstring using comparison operation, see page 24 line 13-14 describes the bit can change based on number of u and Rng). Furthermore, the claim also recites limitation that under BRI cover the performance of using pen and paper, such as selecting the path delays that defines a path delay distribution (see page 6 describes step of selecting a set of k paths). Therefore, the claim includes limitations that fall within the “Mathematical Concepts/ Mental processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a device, a server, a chip, a secure database. However, the additional elements are recited at a high level of generality, i.e., as computer components performing computer functions of processing data and storing data. The claim further recites storing path delays from a chip of a device and transmitting the set of offset values to the device, such steps of storing and transmitting are at most considered as insignificant extra solution activities because they merely recite as data gathering. The claim further recites the method for increasing a number of path delays for generating bitstrings, such limitation is merely recited as a result of performing the mathematical operations as recited in the claim. Furthermore, the claim recites the method for authentication between device and the server, such limitation is at most considered as mere generally linking the use of the judicial exception into a particular technological environment or field of use, such as authentication. Accordingly, the additional elements fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to the step 2A prong two, the additional elements in the claim amount to no more mere instructions to apply the exception, and the steps of storing and transmitting data are determined to be well-understood, routine and conventional (see MPEP 2106.05(d)(II)(i) receiving and transmitting and (iv) storing and retrieving information in memory). Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 2 further recites the linear transformation creates a dependency between both the path delay distribution and the expanded path delay distribution produced based on the linear transformation. Such limitation covers the mathematical concepts grouping of the abstract idea (see at least page 17 describes the mathematical TVCOMP process creates the dependency). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 3 further recites the path delay distribution depends on lengths of the path delays selected. Such limitation merely describes the dependency of the path delay distribution to the length of the path delays and at most is considered as describing the data (e.g., path delay distribution) to be operated on the mathematical operation. Thus, such limitation covers mathematical calculations, relationship. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claims 6-7 further describes the mathematical equations to perform the linear transformation step. Such limitation covers mathematical calculations, relationship, and/or formula. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 8 further recites the definition of the path delays of both the path delay distribution and the expanded path delay distribution as the amount of time for set of 0 to 1 and 1 to 0 transition introduced on primary inputs of the chip to propagate through a logic gate network and emerge on a primary output. Such limitation merely describes the data, such as the path delays, to be operated on the mathematical operations to generate bitstring. Thus, such limitation covers mathematical calculations, relationship. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182