DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/10/2026 has been entered.
Response to Amendment
The amendment filed on 03/10/2026 has been entered. Claims 21-24, 26-40 remain pending in the application. Claims 33-39 are withdrawn. However, the applicant did not amend or address the drawings objections made on pages 2-3 of the previous office action. The objections are repeated here.
Drawings
The drawings are objected to because it is not clear which part of the drawing is referred to by these following limitations. The applicant is requested to identify the following limitations in the drawings for compact prosecution:
a semiconductor device
a first semiconductor device
a second semiconductor device
a third semiconductor device
a fourth semiconductor device
a fifth semiconductor device
The applicant is requested to submit corrected drawing sheets clearly marking all the claimed devices in the figures.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed probe and water sensing cable must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. It is noted that Fig. 3 of the original disclosure describes probe or cable, not both probe and cable together.
PNG
media_image1.png
279
481
media_image1.png
Greyscale
Fig. 3 of the original disclosure
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the claims cite the following structures
a semiconductor device
a first semiconductor device
a second semiconductor device
a third semiconductor device
a fourth semiconductor device
a fifth semiconductor device
However, Specification and Drawings do not describe any structure referenced as above. Specification and Drawing describe numerous semiconductor devices with different specific reference numbers but there is no mapping between claimed devices and devices described in original disclosure. The applicant is requested to submit correction mapping each claimed device to respective reference number from Specification.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-24, 26-32, and 40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 21 and 40 recite “at a probe”. However, page 2 of the specification describes
PNG
media_image2.png
111
853
media_image2.png
Greyscale
Fig. 3 of original disclosure describes
PNG
media_image1.png
279
481
media_image1.png
Greyscale
The original disclosure describes detecting presence of water with a probe but not “at a probe”.
Claims 21-24, 26-32, and 40 cite one or more of the following structures:
a semiconductor device
a first semiconductor device
a second semiconductor device
a third semiconductor device
a fourth semiconductor device
a fifth semiconductor device
However, Specification and Drawings do not describe any structure referenced as above. Specification and Drawing describe numerous semiconductor devices with different specific reference numbers but there is no mapping between claimed devices and devices described in original disclosure. It is not clear if the applicant had possession of the claimed invention.
Claims 21, 40 recite “an amount of water contacting a surface of the water sensing cable”. However, page 2 of the specification describes
PNG
media_image3.png
111
853
media_image3.png
Greyscale
Page 8 of the specification describes “The water leak detector may incorporate a sensing cable to cover an area sensed for water.” Fig. 3 of the original disclosure also does not describe any cable surface in contact with water. Thus, the claimed limitation does not have support in the original disclosure.
Claims 22-24, 26-32 are rejected based on their dependency to claim 21.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-24, 26-32, and 40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 21-24, 26-32, and 40 cite one or more of the following structures:
a semiconductor device
a first semiconductor device
a second semiconductor device
a third semiconductor device
a fourth semiconductor device
a fifth semiconductor device
However, Specification and Drawings do not describe any structure referenced as above. Specification and Drawing describe numerous semiconductor devices with different specific reference numbers but there is no mapping between claimed devices and devices described in original disclosure. It is not clear which embodiment is claimed by the structures referenced above. The metes and bounds of claims are not reasonably conveyed to one skilled in the relevant art.
Claim 21 recites
PNG
media_image4.png
141
890
media_image4.png
Greyscale
There is insufficient antecedent basis for “the first semiconductor device”.
Claims 22-24, 26-32 are rejected based on their dependency to claim 21.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 21, 22, 27, 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown, US 5345224 (hereafter Brown) and further in view of Utke, US 6683535 (hereafter Utke).
Regarding claim 21,
A circuit comprising: a semiconductor device comprising a first gate terminal configured to receive a first electrical signal indicating a presence of water at a probe, (Here “at a probe” is interpreted as probe detects presence of water, gate terminal is interpreted as triggering terminal.
PNG
media_image5.png
490
556
media_image5.png
Greyscale
Fig. 1 in Brown
PNG
media_image6.png
555
545
media_image6.png
Greyscale
Fig. 1 in Brown teaches electrical switch and electrically controlled solenoid valves
Brown teaches an electrical switch 18 in a water heater in Fig. 1. When a water leak occurs, the switch is triggered as taught in abstract “A float is disposed at least partially within the liquid pan 14 and causes an electrical shut-off signal from an electrical switch to be generated when it is elevated in response to the collection of water within the liquid pan 14.” It is implied that the switch has a gate terminal that receives the triggering signal. Switch corresponds to semiconductor device, float corresponds to probe.)
the first electrical signal causing the first semiconductor device to change state; and (Column 4, lines 50-55 teaches “Electrical current from an AC current source, or alternatively a DC battery, is then supplied through the switch 18 and forms an electrical shut-off signal which is transmitted to the electrical junction box 22.”)
..wherein in response to the semiconductor device receiving the first electrical signal, the circuit is configured to cause a heat source to operate in an extinguished state. (Abstract in Brown teaches “The electrical shut-off signal causes electrically controlled solenoid valves disposed in the water supply and gas lines to the hot water heater 12 to be closed, thereby interrupting the flow of cold water and natural gas into the hot water heater 12”)
Brown is silent about a water sensing cable configured to: generate a second electrical signal based on an amount of water contacting a surface of the water sensing cable; and cause the first gate terminal of the semiconductor device to receive the first electrical signal by generating a second electrical signal,
Utke teaches a water sensing cable configured to: generate a second electrical signal based on an amount of water contacting a surface of the water sensing cable; (Fig. 2 teaches that resistance between sensors 22a and 22b changes based on an amount of water contacting the surfaces. Here the resistance is the second electrical signal. )
PNG
media_image7.png
558
369
media_image7.png
Greyscale
Fig. 2 in Utke
and cause the first gate terminal of the semiconductor device to receive the first electrical signal by generating a second electrical signal, ( Fig. 2 teaches when resistance between 22a and 22b is low, a current flows through amplifying transistor 32 and triggers switching transistor 34 to change state.)
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the sensors and switch circuit from Utke to the circuit in Brown. One of ordinary skill in the art would have been motivated to do so because “The water sensor includes a solid state switching and amplifying circuit for detecting low levels of current flow and amplifying the signal to activate the alarm relay” as taught in abstract in Utke.
Regarding claim 22,
The circuit of claim 21, further comprising: a second semiconductor device configured to change state from a first state to a second state in response to the first semiconductor device operating in a first state; and a third semiconductor device configured to change state from a first state to a second state in response to the first semiconductor device operating in the first state, (Here first semiconductor device operating in a first state is interpreted as no leak signal is detected by semiconductor device.
Brown teaches electrically controlled solenoid valves 24 and 26 in Fig. 1. Abstract teaches “The electrical shut-off signal causes electrically controlled solenoid valves disposed in the water supply and gas lines to the hot water heater 12 to be closed, thereby interrupting the flow of cold water and natural gas into the hot water heater 12”.)
PNG
media_image8.png
490
711
media_image8.png
Greyscale
Fig. 1 in Brown
wherein the second semiconductor device and the third semiconductor device are configured to cause the heat source to operate in an ignited state while the second semiconductor device operates in the second state and the third semiconductor device operates in the second state. (Column 6, lines 20-26 in Brown teaches “It should also be appreciated that the solenoid valves 24 and 26 are preferably normally open valves which do not interrupt or otherwise affect the flow of cold water and gas into the hot water heater 12 at times when no water leak is occurring.”)
Regarding claim 27,
“The circuit of claim 21, further comprising: boost circuitry configured to receive the first electrical signal indicating the presence of the water; and alarm circuitry connected to the boost circuitry, wherein the boost circuitry is configured to provide an alarm signal to the alarm circuitry based on the boost circuitry receiving the electrical signal.” (Brown is silent about this.
Fig. 2 in Utke teaches boost circuit providing alarm to alarm circuitry.
PNG
media_image9.png
558
369
media_image9.png
Greyscale
Fig. 2 in Utke
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the boost circuitry as taught in Utke to the circuit in Brown. One of ordinary skill in the art would have been motivated to do so because “The water sensor includes a solid state switching and amplifying circuit for detecting low levels of current flow and amplifying the signal to activate the alarm relay” as taught in abstract in Utke.
Regarding claim 40,
“A system comprising: a heat source;” (Column 1, lines 20-25 in Brown teaches a water heater that is heated by gas. Here gas is heat source and water heater is the system.)
“a first semiconductor device comprising a first gate terminal configured to receive a first electrical signal indicating a presence of water at a probe, the first electrical signal causing the first semiconductor device to change state; (Similar scope to claim 21 and therefore rejected under the same argument.)
a second semiconductor device configured to operate in a first state in response to the first semiconductor device changing state; a third semiconductor device configured to operate in the first state in response to the first semiconductor device changing state, (Here first semiconductor device changing state is interpreted as leak signal is detected by semiconductor device.
Brown teaches electrically controlled solenoid valves 24 and 26 in Fig. 1. Abstract teaches “The electrical shut-off signal causes electrically controlled solenoid valves disposed in the water supply and gas lines to the hot water heater 12 to be closed, thereby interrupting the flow of cold water and natural gas into the hot water heater 12”.)
wherein the second semiconductor device and the third semiconductor device are configured to cause the heat source to operate in an extinguished state while the second semiconductor device and the third semiconductor device operate in the first state.” (Brown teaches electrically controlled solenoid valves 24 and 26 in Fig. 1. Abstract teaches “The electrical shut-off signal causes electrically controlled solenoid valves disposed in the water supply and gas lines to the hot water heater 12 to be closed, thereby interrupting the flow of cold water and natural gas into the hot water heater 12”.)
and a water sensing cable configured to: generate a second electrical signal based on an amount of water contacting a surface of the water sensing cable; and cause the first gate terminal of the first semiconductor device to receive the first electrical signal by generating the second electrical signal. (Similar scope to claim 21 and therefore rejected under the same argument.)
Claim(s) 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown, and Utke as applied to claim 21 above, and further in view of Low side MOSFET drive, https://tahmidmc.blogspot.com/2012/12/low-side-mosfet-drive-circuits-and_23.html, Nov 2016 (hereafter Low side MOSFET drive), and Lopez et al., Current sharing of paralleled power MOSFETs at PWM operation, 37th IEEE PESC, 2006 (hereafter Lopez).
Regarding claim 23,
“The circuit of claim 21, wherein: the semiconductor device further comprises a set of load terminals, wherein a first load terminal of the set of load terminals is electrically connected to a ground,” (Primary combination of references is silent about this limitation.
Low side MOSFET drive teaches a circuit in Fig. 1 with a NPN BJT driving a N channel MOSFET. Annotated Fig. 1 teaches a ground terminal. Here NPN BJT corresponds to the first semiconductor device.
PNG
media_image10.png
891
1766
media_image10.png
Greyscale
Low side MOSFET drive teaches a circuit in Fig. 1
“and wherein a second load terminal of the set of load terminals is electrically connected to a node; a second semiconductor device comprises a second gate terminal, wherein the second gate terminal is electrically connected to the node;” (Annotated Fig. 1 of Low side MOSFET drive teaches a node connected to second gate terminal. Here N-MOSFET is the second semiconductor device.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the semiconductor devices as taught in low side MOSFET drive to the circuit in Brown to control valves. One of ordinary skill in the art would have been motivated to do so because “Fig. 1 shows an inverting driver. Here, the MOSFET is turned on when Vin is low and turned off when Vin is high. When the MOSFET is on, the load is on and vice versa” as taught in page 4 of low side MOSFET drive. )
“and a third semiconductor device comprises a third gate terminal, wherein the third gate terminal is electrically connected to the node.” (Primary combination of references is silent about this limitation.
Lopez teaches paralleling multiple MOSFETs and driving them by a single gate drive in page 1, column 2 and Figure 1.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add two N-MOSFETs in parallel as taught in Lopez to Fig. 1 in low side MOSFET drive to parallel MOSFET Q2. Hence, both gate terminals would be connected the node and driven by the same node. This would allow lower resistance and increase current through load that is connected to the drain of MOSFET. One of ordinary skill in the art would have been motivated to do so because “Paralleling of transistors is a basic concept to cope with high current requirements. In automotive electronics for example, inverter applications may require load currents of several hundred amperes or more. Regarding costs and reliability, the employment of multiple standard MOSFETs in standard package types (like TO220) can be preferable to solutions using single large MOSFET dies” as taught in page 1, column 1 in Lopez.)
Regarding claim 24,
“ The circuit of claim 23, wherein by operating in a first state, the semiconductor device is configured to: create an electrical connection between the … gate terminal and the ground in order to apply a ground voltage to the … gate terminal, causing the …semiconductor device to operate in second state;” (Annotated Fig. 1 of Low side MOSFET drive teaches that when Q1 is on it drives the node to ground, hence the gate signal for MOSFET Q2 is ground. Q2 is a N-MOSFET so when the gate signal is ground it turns MOSFET Q2 off.)
and create an electrical connection between the … gate terminal and the ground in order to apply a ground voltage to the … gate terminal, causing the …semiconductor device to operate in the second state;” (Annotated Fig. 1 of Low side MOSFET drive teaches that when Q1 is on it drives the node to ground, hence the gate signal for MOSFET Q2 is ground. Q2 is a N-MOSFET so when the gate signal is ground it turns MOSFET Q2 off.)
“wherein a magnitude of the ground voltage is lower than a magnitude of a voltage applied to the …gate terminal while the semiconductor device operates in the second state,” (Annotated Fig. 1 of Low side MOSFET drive teaches that when Q1 is off it drives the node to about +V_DRIVE voltage. This high voltage turns MOSFET Q2 on.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the semiconductor switches as taught in low side MOSFET drive to the circuit in Brown to control valves. One of ordinary skill in the art would have been motivated to do so because “Fig. 1 shows an inverting driver. Here, the MOSFET is turned on when Vin is low and turned off when Vin is high. When the MOSFET is on, the load is on and vice versa” as taught in page 4 of low side MOSFET drive. )
“the second gate terminal ….the third gate terminal” (Primary combination of references is silent about this limitation.
Lopez teaches paralleling multiple MOSFETs and driving them by a single gate drive in page1, column 2 and Figure 1.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add two N-MOSFETs in parallel as taught in Lopez to Fig. 1 in low side MOSFET drive to parallel MOSFET Q2. Hence, both gate terminals would be connected the node and driven by the same node. This would allow lower resistance and increase current through load that is connected to the drain of MOSFET. One of ordinary skill in the art would have been motivated to do so because “Paralleling of transistors is a basic concept to cope with high current requirements. In automotive electronics for example, inverter applications may require load currents of several hundred amperes or more. Regarding costs and reliability, the employment of multiple standard MOSFETs in standard package types (like TO220) can be preferable to solutions using single large MOSFET dies” as taught in page 1, column 1 in Lopez.)
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown, Utke, Low side MOSFET drive, and Lopez as applied to claim 23 above, and further in view of PMOSFET drive, https://electronics.stackexchange.com/questions/208935/controlling-higher-voltage-and-load-via-high-side-switch-from-a-microcontroller, Jan 2016 (hereafter PMOSFET drive).
“The circuit of claim 23, wherein the node comprises a first node,” (Annotated Fig. 1 of Low side MOSFET drive teaches a node.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the semiconductor switches as taught in low side MOSFET drive to the circuit in Brown to control valves. One of ordinary skill in the art would have been motivated to do so because “Fig. 1 shows an inverting driver. Here, the MOSFET is turned on when Vin is low and turned off when Vin is high. When the MOSFET is on, the load is on and vice versa” as taught in page 4 of low side MOSFET drive. )
“and wherein the circuit further comprises: a fourth semiconductor device comprising a fourth gate terminal, wherein the fourth gate terminal is configured to receive the …electrical signal,” (Primary combination of references is silent about this limitation.
PMOSFET drive teaches an NPN BJT driving a PMOSFET in annotated figure below. Here input of BJT receives input signal. BJT corresponds to the fourth semiconductor device.)
PNG
media_image11.png
826
1775
media_image11.png
Greyscale
Annotated figure of PMOSFET drive
“and wherein a load terminal of the fourth semiconductor device is electrically connected to a second node;” (Annotated figure of PMOSFET drive teaches the second node at the collector of BJT.)
“a fifth semiconductor device comprising a fifth gate terminal, wherein the fifth gate terminal is electrically connected to the second node,” (Annotated figure of PMOSFET drive teaches a PMOSFET connected to the collector of BJT. Here PMOSFET is the fifth semiconductor device.)
“…wherein by operating in the second state, the fourth semiconductor device is configured to cause the fifth semiconductor device to operate in the second state,” (Annotated figure of PMOSFET drive teaches when NPN BJT is on, it grounds the gate of PMSOFET and thus turns on the PMOSFET.)
“wherein the fourth gate terminal is configured to receive the second electrical signal from the water sensing cable… wherein the second electrical signal is configured to cause the fourth semiconductor device to operate in the second state when the fourth gate terminal receives the second electrical signal ….and wherein the fifth semiconductor device is configured to output the first electrical signal to the semiconductor device when the fifth semiconductor device operates in the second state.” (Annotated figure of PMSOFET drive teaches that BJT turns on when it receives an electrical signal at the input. This turns the PMSOFET on and generates a high signal at the output.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the BJT and PMSOFET as taught in PMOSFET drive in the switch circuit in Brown. In this combination, the BJT would receive the second electrical signal from the sensor indicating leak, BJT and PMOSFET would activate, and the PMOSFET would output the first electrical signal. One of ordinary skill in the art would have been motivated to do so in order to control “higher voltage and load via high-side switch” as taught in PMOSFET drive.)
Claim(s) 28, 30-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown, and Utke as applied to claim 27 above, and further in view of Furr, US 5334973 (hereafter Furr).
Regarding claim 28,
“The circuit of claim 27, wherein the boost circuitry comprises: timer circuitry configured to receive the first electrical signal indicating the presence of the water;” (Primary combination of references is silent about this.
Fig. 2A in Furr teaches boost circuit 182 comprises a timer IC TLC555 as reference 25.)
PNG
media_image12.png
414
904
media_image12.png
Greyscale
Fig. 2A in Furr
“ and signal generation circuitry electrically connected to the timer circuitry,” (Primary combination of references is silent about this.
Fig. 2A in Furr teaches a signal generation circuitry comprising transistors 22, 20, capacitor 23, and resistors connected to timer 25.)
“ wherein the timer circuitry causes the signal generation circuitry to deliver the alarm signal to the alarm circuitry based on the timer circuitry receiving the electrical signal.” (Column 7, lines 30-52 teaches that when timer 25 is triggered, transistors 20, 22 are activated and LED 21 illuminates. This LED displays alarm status as taught in column 4, lines 60-65 in Furr.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the timer, signal generation circuitry as taught in Furr to the circuit in Brown to indicate alarm status. One of ordinary skill in the art would have been motivated to do so because “Circuitry controls the sensor that provides for accurate detection of even small amounts of moisture so that any potential leak problems can be remedied before a major spill occurs. The device also features a water shut off control mechanism plus audible alarm in the event a leak is detected” as taught in abstract in Furr.)
Regarding claim 30,
“The circuit of claim 28, wherein the alarm signal alternates the alarm circuitry between operating in the second state and operating in the first state.” (The claim is interpreted as the presence of alarm signal operates the alarm circuitry in on state, and absence of alarm signal operates the alarm circuitry in off state.
Primary combination of references is silent about this.
Column 7, lines 30-52 in Furr teaches that when timer 25 is triggered, transistors 20, 22 are activated and LED 21 illuminates. This LED displays alarm status as taught in column 4, lines 60-65 in Furr. It is implied that when timer 25 is not triggered, transistors 20, 22 are not activated and LED 21 is off.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the timer, signal generation circuitry as taught in Furr to the circuit in Brown to indicate alarm status. One of ordinary skill in the art would have been motivated to do so because “Circuitry controls the sensor that provides for accurate detection of even small amounts of moisture so that any potential leak problems can be remedied before a major spill occurs. The device also features a water shut off control mechanism plus audible alarm in the event a leak is detected” as taught in abstract in Furr.)
Regarding claim 31,
“The circuit of claim 27, wherein by providing the alarm signal to the alarm circuitry, the boost circuitry is configured to cause the alarm circuitry to emit one or more sounds indicating the presence of the water.” (Primary combination of references is silent about this.
Fig. 1 in Furr teaches sensor/alarm status board 182 that corresponds to boost circuitry in the instant claim. Circuit 182 is connected to buzzer 34. Here buzzer corresponds to the alarm circuitry. Column 4, lines 65-68 teaches “Sensor/alarm status board 182 senses an alarm condition and distributes signals to the control panel 390, electronic control board 183, alarm accessory trigger board 170 and buzzer 34.” Abstract teaches “The device also features a water shut off control mechanism plus audible alarm in the event a leak is detected.”
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the sensor/alarm status board and buzzer as taught in Furr to the circuit in Brown. One of ordinary skill in the art would have been motivated to do so because “Circuitry controls the sensor that provides for accurate detection of even small amounts of moisture so that any potential leak problems can be remedied before a major spill occurs. The device also features a water shut off control mechanism plus audible alarm in the event a leak is detected” as taught in abstract in Furr.)
Regarding claim 32,
“The circuit of claim 27, wherein the alarm circuitry comprises: an alarm driver electrically connected to the boost circuitry, wherein the alarm driver is configured to receive the alarm signal from the boost circuitry;” (Column 8, lines 30-35 in Furr teaches “The buzzer 34 is activated by the flow of current from the collector of transistor 38”. Figure 2A teaches transistor 38 is connected to boost circuitry 182 and receives the alarm signal from boost circuitry 182. Here transistor 38 corresponds to the alarm driver in the instant claim.)
“ and an alarm electrically connected to the alarm driver, wherein the alarm is configured to emit one or more sounds in response to the alarm driver receiving the alarm signal from the boost circuitry.”(Figure 2A teaches buzzer 34 connected to transistor 38. Column 8, lines 30-35 in Furr teaches “The buzzer 34 is activated by the flow of current from the collector of transistor 38 and produces a pulsating audio output at 95 decibels.”
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the sensor/alarm status board and buzzer as taught in Furr to the circuit in Brown. One of ordinary skill in the art would have been motivated to do so because “Circuitry controls the sensor that provides for accurate detection of even small amounts of moisture so that any potential leak problems can be remedied before a major spill occurs. The device also features a water shut off control mechanism plus audible alarm in the event a leak is detected” as taught in abstract in Furr.)
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown, Utke, Furr as applied to claim 28 above, and further in view of Breunig et al., US 20010023488 (hereafter Breunig).
“The circuit of claim 28, wherein the signal generation circuitry comprises: …and a transistor configured to cause the … to discharge the stored energy to the alarm circuitry based on receiving the first electrical signal.” (Furr teaches a capacitor 23 discharging through transistor 22. When a leak is detected and timer 25 is triggered, capacitor discharges through transistor 22 and sends the alarm signal to alarm circuitry in column 7, lines 35-52.
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to add the timer, signal generation circuitry as taught in Furr to the circuit in Brown to indicate alarm status. One of ordinary skill in the art would have been motivated to do so because “Circuitry controls the sensor that provides for accurate detection of even small amounts of moisture so that any potential leak problems can be remedied before a major spill occurs. The device also features a water shut off control mechanism plus audible alarm in the event a leak is detected” as taught in abstract in Furr.)
“an inductor configured to store energy; a transistor configured to cause the inductor to discharge” (Primary combination of references is silent about this.
Breunig teaches a circuit 6 comprising a FET 62, inductor 64, and capacitor 68. Paragraph [20] teaches during regular operation FET 62 is off. In the case of a triggering event, FET 62 is switched on by a PWM signal, “thereby storing energy in the inductor 64 when the PWM signal is high. When the PWM signal is low, the stored energy in the inductor 64 charges the capacitor 68 via the Schottky diode 66. This boosts the charge in the capacitor 68”. Thus, Breunig is solving the same problem of storing energy in an inductor and discharging the inductor by a transistor as in the instant claim.
PNG
media_image13.png
519
690
media_image13.png
Greyscale
Figure 2B in Breunig teaches inductor for storing energy
Before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to use an inductor to store energy as taught in Breunig in the circuit of Brown. One of ordinary skill in the art would have been motivated to do so because “the microprocessor 4 outputs a pulse width modulation (PWM) signal to the boost subsystem 6 to periodically turn on and off the FET 62 according to a predetermined PWM duty cycle so as to boost the charge in the capacitor 68 while providing a higher averaged voltage supply to the voltage regulator 12” as taught in paragraph [23] in Breunig.)
Response to Arguments
Applicant’s arguments filed on 03/10/2026 with respect to claim(s) 21-24, 26-32, and 40 have been considered but are not persuasive.
The applicant stated on page 9 that drawings are clear without any explanation. The argument is not persuasive.
The applicant amended the claims and argued that this makes the claimed invention distinguishable from prior art. However, upon further consideration, a new ground(s) of rejection is made in view of prior art as discussed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAHMIDA FERDOUSI whose telephone number is (303)297-4341. The examiner can normally be reached Monday-Friday; 9:00AM-3:00PM; PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Crabb can be reached on (571)270-5095. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAHMIDA FERDOUSI/ Examiner, Art Unit 3761
Prosecution Insights