DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/04/2025 has been entered.
Claim Amendments
Acknowledgment of receiving amendments to the claims, which were received by the Office on 12/04/2025.
Response to Arguments
Applicant’s arguments with respect to claims 1 have been considered but are moot because the arguments do not apply to the same combination of references being used in the current rejection. Applicant’s arguments are directed solely to the claimed invention as amended 12/04/2025, which has been rejected under new ground of rejection necessitated by amendment. See rejection below for full detail.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-10, 12-14 and 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/0098012 A1) in view of obviousness.
Regarding claim 1, Takado teaches an imaging device (Takado, Figs. 5) comprising:
a first plurality of pixel circuits, each pixel circuit including a light-receiving element (Takado, Figs. 2 and 5, pixels 105, photoelectric converter PD); and a second plurality of pixel circuits, each of a first pixel circuit and a second pixel circuit (Takado, Fig. 5, pixels 110) including
a first terminal (Takado, Fig. 2, The first terminal is the gate of the transfer transistor M1, Paragraph 0039),
a second terminal (Takado, Fig. 2, The second terminal is the gate of the reset transistor M2, Paragraph 0039),
a third terminal (Takado, Fig. 2, The third terminal is the source of the transfer transistor M1, Paragraph 0039),
accumulation circuitry configured to accumulate an electric charge (Takado, Fig. 2, amplifier transistor M3, Paragraphs 0044),
a first transistor configured to supply a first voltage signal (Takado, Fig. 5-6, Paragraphs 0077-0079, 0082 and 0086, Va/112) to the accumulation circuitry by coupling the third terminal to the accumulation circuitry based on a voltage of the first terminal (Takado, Fig. 2, transfer transistor M1, Signal Line TX, Paragraphs 0042-0044),
a second transistor configured to supply a first predetermined voltage (Takado, Fig. 2, voltage VDD) to the accumulation circuitry based on a voltage of the second terminal (Takado, Fig. 2, reset transistor M2, Paragraph 0044), and
an output circuitry configured to output a signal corresponding to a voltage in the accumulation circuitry (Takado, Fig. 2, select transistor M4, Paragraph 0044),
a first control line extending in a first direction, the first control line coupled to the first terminal (Takado, Fig. 2, signal line TX, Paragraph 0042, The first control line may be considered to be signal line TX of a single row or may be interpreted to be signal line TX for all rows. The first direction is the horizontal direction.),
a second control line extending in the first direction, the second control line coupled to the second terminal (Takado, Fig. 2, signal line RES, Paragraph 0042, The second control line may be considered to be signal line RES of a single row or may be interpreted to be signal line RES for all rows.),
a first voltage supply line, the first voltage supply line coupled to the third terminal the first transistor (Takado, Figs. 2 and 5, voltage supply line 112/Va, Paragraph 0032-0033); and
a controller (Takado, Fig. 5, Column Circuit 103, Control Unit 107, output circuit 115, and voltage switch 13) configured to apply the first voltage signal to the first voltage supply line, the first voltage signal having a first signal portion at a first predetermined voltage level and a second signal portion at a floating voltage level (Takado, Fig. 5-6, Paragraphs 0077-0079, 0082 and 0086, Va/112 is the first voltage supply line. The first predetermined voltage level may be V1.) within each horizontal period (Takado, Figs. 3B and 6B, Paragraph 0088, During a horizontal period (Fig. 3B), the first voltage signal is the first voltage (V1) from times T13-T15 (first signal portion) and the first voltage signal is the second voltage (floating) before T13 and/or after T15 (second signal portion). Alternatively, the first signal portion at a first predetermined voltage level may be T16-T17 at floating voltage level and the second signal portion at a second predetermined voltage level may be times T13-T15 at voltage V1.),
wherein the first voltage signal is separate and distinct from the first predetermined voltage (Takado, Paragraph 0064,The first voltage signal (Va/112) is separate and distinct from the first predetermined voltage VDD.).
However, Takado does not teach the floating voltage level is a second predetermined voltage level that is different from the first predetermined voltage level.
Official notice is taken that it is well known that inputs or signal lines not in use that are in a floating state may be biased to be fixed voltage or grounded (see conclusion). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Takado to ground or bias the floating state to a predetermined voltage since it is a known alternative state to a floating state and to prevent charge build up on the signal lines.
Regarding claim 6, Takado teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the first signal portion occurs in a first period in which the first transistor and the second transistor are both turned on (Takado, Fig. 3B, Times T16-T17, first transistor (PTX) and second transistor (PRES) of the shutter row are both turned on.), and the second signal portion occurs in a second period outside the first period (Takado, Fig. 3B, Times T13-T15).
Regarding claim 7, Takado teaches the imaging device according to claim 1 (see claim 1 analysis), wherein
the first plurality of pixel circuits and the second plurality of pixel circuits each belongs to one of a plurality of pixel lines (Takado, Fig. 5, Each pixel belongs to one of the pixel lines.),
the first pixel circuit, the second pixel circuit, and a third pixel circuit (Takado, Fig. 5, The third pixel circuit is a pixel in the same row as the first and second pixel circuit (for example, the second row).) of the first plurality of pixel circuits belong to a first pixel line of the plurality of pixel lines (Takado, Fig. 5, A first pixel line may be a pixel line with two VA pixels.),
a predetermined number of the second plurality of pixel circuits, the respective third terminals of which are coupled to the first voltage supply line, belong to the one of the plurality of pixel lines, the predetermined number is greater than or equal to two (Takado, Fig. 5, A predetermined number of pixel circuits of the pixel circuits 110 belonging to the one of the plurality of pixel lines is greater than or equal to two.) and
a number of the plurality of pixel lines is less than or equal to a number that is expressible by a coupling combination of the respective third terminals with the first voltage supply line in the predetermined number of pixel circuits (Takado, Fig. 5, The predetermined number of pixel circuits may be the number of pixel circuits 110 and 111 belonging to a row. In Fig. 5, the shown number of pixel circuits 110 and 111 in a row is three (note: Paragraph 0037 states the number of columns is not limited to three). The expressible combination of three binary units is 8. The plurality of pixel lines maybe be considered to be any number of pixel lines (for example, the first 3 rows of pixel lines or the first 7 rows of pixel lines.).).
Regarding claim 8, Takado teaches the imaging device according to claim 7 (see claim 7 analysis), wherein first information includes second information, the first information indicated by the coupling combination of the respective third terminals with the first voltage supply line in the predetermined number of pixel circuits (Takado, Paragraphs 0031 and 0103, The first information is the pixel values from the AD conversion of the voltages V0 and V1.), the predetermined number of pixel circuits belonging to the first pixel line (Takado, Fig. 5, The predetermined number of pixel circuits may be the number of pixel circuits 110 and 111 belonging to a row. In Fig. 5, the shown number of pixel circuits 110 and 111 in a row is three), the second information configured to identify the first pixel line (Takado, Fig. 8, Paragraphs 0036 and 0104-0106, The pattern of the first information is the second information. Therefore, the first information includes second information.).
Regarding claim 9, Takado teaches the imaging device according to claim 8 (see claim 8 analysis), wherein the first information further includes third information, the third information indicating an attribute of the first pixel line (Takado, Fig. 8, Step S840, Paragraph 0104-0106, The third information is whether the pixel row is operating normally or if there is an abnormality. Operating normally or abnormally is considered to be an attribute of the pixel line.).
Regarding claim 10, Takado teaches the imaging device according to claim 1 (see claim 1 analysis), further comprising:
a second voltage supply line (Takado, Fig. 2, VDD);
a third plurality of pixel circuits (Takado, Figs. 2 and 5, pixels 111), each pixel circuit including
a fourth terminal (Takado, Fig. 2, The first terminal is the gate of the transfer transistor M1, Paragraph 0039),
a fifth terminal (Takado, Fig. 2, The second terminal is the gate of the reset transistor M2, Paragraph 0039),
a sixth terminal (Takado, Fig. 2, The third terminal is the source of the transfer transistor M1, Paragraph 0039),
a second accumulation circuitry configured to accumulate a second electric charge (Takado, Fig. 2, amplifier transistor M3, Paragraphs 0044),
a third transistor configured to couple the sixth terminal to the second accumulation circuitry based on a second voltage of the fourth terminal (Takado, Fig. 2, transfer transistor M1, Signal Line TX, Paragraphs 0042-0044),
a fourth transistor configured to supply a third predetermined voltage (Takado, Fig. 2, voltage VDD) to the second accumulation circuitry based on a third voltage of the fifth terminal (Takado, Fig. 2, reset transistor M2, Paragraph 0044), and
a second output circuitry configured to output a second signal corresponding to a voltage in the second accumulation circuitry (Takado, Fig. 2, select transistor M4, Paragraph 0044);
the fourth terminal is coupled to the first control line (Takado, Fig. 2, signal line TX, Paragraph 0042),
the fifth terminal is coupled to the second control line (Takado, Fig. 2, signal line RES, Paragraph 0042), and
the sixth terminal is coupled to the second voltage supply line (Takado, Figs. 2 and 5, VDD is connected to the sixth terminal indirectly.);
a plurality of signal lines, a first signal line is coupled to the output circuitry and a second signal line is coupled the second output circuitry, the second signal line being separate and distinct from the first signal line (Takado, Figs. 2 and 5, vertical output lines 108, A first signal line is a vertical output line 108 coupled to a pixel 110 in a first column. A second signal line is a vertical output line 108 coupled to a pixel 111 in a second column different from the first column.),
wherein the controller is further configured to apply only the first predetermined voltage to the second voltage supply line within the each horizontal period (Takado, Fig. 2, Paragraph 0039, power source voltage terminal VDD is a constant supply.).
Regarding claim 12, Takado teaches the imaging device according to claim 1 (see claim 1 analysis), further comprising:
a third voltage supply line (Takado, Fig. 5-6, Paragraphs 0077-0079, 0082 and 0086, Vb/113 is the third voltage supply line.); and
a fourth plurality of pixel circuits (Takado, Fig. 5, pixels 111), each pixel circuit including
a fourth terminal (Takado, Fig. 2, The first terminal is the gate of the transfer transistor M1, Paragraph 0039),
a fifth terminal (Takado, Fig. 2, The second terminal is the gate of the reset transistor M2, Paragraph 0039),
a sixth terminal (Takado, Fig. 2, The third terminal is the source of the transfer transistor M1, Paragraph 0039),
a second accumulation circuitry configured to accumulate a second electric charge (Takado, Fig. 2, amplifier transistor M3, Paragraphs 0044),
a third transistor configured to couple the sixth terminal to the second accumulation circuitry based on a second voltage of the fourth terminal (Takado, Fig. 2, transfer transistor M1, Signal Line TX, Paragraphs 0042-0044),
a fourth transistor configured to supply a third predetermined voltage (Takado, Fig. 2, voltage VDD) to the second accumulation circuitry based on a third voltage of the fifth terminal (Takado, Fig. 2, reset transistor M2, Paragraph 0044), and
a second output circuitry configured to output a second signal corresponding to a voltage in the second accumulation circuitry (Takado, Fig. 2, select transistor M4, Paragraph 0044),
the fourth terminal is coupled to the first control line (Takado, Fig. 2, signal line TX, Paragraph 0042),
the fifth terminal is coupled to the second control line (Takado, Fig. 2, signal line RES, Paragraph 0042), and
the sixth terminal is coupled to the third voltage supply line (Takado, Figs. 2 and 5, voltage supply line 113/Vb, Paragraph 0032-0033); and
wherein the controller is further configured to apply a third voltage signal to the third voltage supply line, the third voltage signal having the first signal portion and a third signal portion within the each horizontal period (Takado, Fig. 5-6, Paragraphs 0077-0079, 0082 and 0086, Vb/113 is the third voltage supply line.), the third signal portion being separate and distinct from the first signal portion and the second signal portion (Takado, Figs. 3B, The first signal portion is times T13-T15. The second signal portion may be considered to be before T13 and the third signal portion may be considered to be after T15.).
Regarding claim 13, Takado teaches the imaging device according to claim 1 (see claim 1 analysis), further comprising:
first driving circuitry configured to drive the first control line (Takado, Fig. 5, vertical scanning circuit 102, Paragraph 0028), wherein
the first driving circuitry is disposed in a control circuitry region (Takado, Fig. 5, vertical scanning circuit 102),
the first plurality of pixel circuits is disposed in a normal pixel region (Takado, Fig. 5, first region 10, Paragraph 0023),
the second plurality of pixel circuits is disposed in a verification pixel region (Takado, Fig. 5, second region 11, Paragraph 0024),
the first control line has a first end to which the first driving circuitry is coupled, and a second end (Takado, Fig. 1, The first end is the side of the vertical scanning circuit 102. The second end is the other side closer to pixels 110 and 111.), and
the verification pixel region, the normal pixel region, and the control circuitry region are disposed in this order in a direction from the second end to the first end (Takado, Fig. 5).
Regarding claim 14, Takado teaches the imaging device according to claim 13 (see claim 13 analysis), further comprising a second driving circuitry (Takado, Fig. 5, Control Unit 107) coupled to the second end of the first control line (Takado, Fig. 5, Control Unit 107 is indirectly coupled to the second end of the first control line.), the second driving circuitry configured to drive the first control line (Takado, Fig. 5, Control Unit 107 controls vertical scanning circuit 102 which controls the first control line.).
Regarding claim 22, Takado teaches the imaging device according to claim 13 (see claim 12 analysis), wherein the first voltage supply line is directly adjacent to the third voltage supply line in a second direction that traverses the first direction (Takado, Fig. 5, The second direction is the vertical direction.
Regarding claim 23, Takado teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the first voltage signal has a single falling edge between the first signal portion and the second signal portion within each horizontal period (Takado, Figs. 3B, The first voltage signal has a single falling edge at time T15 between the first signal portion (T13-T15) and the second signal portion (after T15).), and
wherein, after an initial horizontal period, the first voltage signal has a plurality of rising edges from the second signal portion to the first signal portion that correspond with an end of one horizontal period and a beginning of a next horizontal period (Takado, Fig. 3B, Rising edges would occur for horizontal periods of each row and for subsequent image captures.).
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/0098012 A1) in view of obviousness in view of Makino et al. (US 2012/0008027 A1).
Regarding claim 2, Takado teaches the imaging device according to claim 1 (see claim 1 analysis), further comprising:
driving circuitry (Takado, vertical scanning circuit 102, Paragraph 0028),
wherein the controller is further configured to
perform a first diagnosis process based on a pixel row (Takado, Figs. 1, 4 or 5, Paragraph 0029, A first diagnosis process may be amplifying pixel signals or correlated double sampling.), a first signal, and a second signal, the first signal is output from the output circuitry of the first pixel circuit, the second signal is output from the output circuitry of the second pixel circuit (Takado, Paragraph 0029, The first pixel signal and second pixel signal output by the first pixel circuit and second pixel circuit are processed by amplifying pixel signals and correlated double sampling), and
perform a second diagnosis process based on the first signal and the second signal (Takado, Paragraph 0031, A second diagnosis process is AD conversion of the pixel signals.); and
wherein the driving circuitry is configured to drive the first control line and the second control line based on a selected pixel row (Takado, vertical scanning circuit 102, Paragraph 0028).
However, Takado does not explicitly state the controller configured to generate an address signal; perform a first diagnosis process based on the address signal, a first signal, and a second signal; nor wherein the driving circuitry is configured to drive the first control line and the second control line based on the address signal (Examiner notes Paragraph 0028 states the vertical scanning circuit 102 includes an address decoder which is well known in the art for use in decoding an address signal.).
In reference to Makino et al. (hereafter referred as Makino), Makino teaches a controller configured to generate an address signal (Makino, Fig. 1, sensor controller 150, Paragraph 0103);
selecting a pixel row based on the address signal (Makino, Paragraph 0077); and
driving circuitry (Makino, Fig. 1, vertical selection circuit 170, Paragraph 0077) configured to drive a first control line (Makino, Fig. 2, control line LTR, Paragraph 0068-0069) and a second control line (Makino, Fig. 2, control line LRST, Paragraph 0071-0072) based on the address signal (Makino, Paragraph 0051-0053 and 0077).
These arts are analogous since they are both related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the invention of Takado with the explicit teaching of using an address signal to select pixel rows as seen in Makino.
"A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense" KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007).
It would have been obvious to a person of ordinary skill, when pursuing the known options within his or her technical grasp (See KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007)), to have modified the invention of Takado with the explicit teaching of using an address signal to select pixel rows as seen in Makino since it is a known method of driving the image sensor and would provide similar and expected results for selecting pixel rows for processing. Further, the claim language “perform a first diagnosis process based on the address signal, a first signal, and a second signal” is met since the pixel row selected for performing the first diagnosis process is selected based on the address signal.
Regarding claim 3, the combination of Takado and Makino teaches the imaging device according to claim 2 (see claim 2 analysis), wherein the controller further includes a conversion circuit (Takado, Fig. 1, output circuit 115, Paragraph 0031) configured to
generate a first digital code by performing AD conversion based on the first signal (Takado, Paragraph 0031, AD conversion of the first signal produces a first digital signal which is a first digital code.), and
generate a second digital code by performing AD conversion based on the second signal (Takado, Paragraph 0031, AD conversion of the second signal produces a second digital signal which is a second digital code.), and
a diagnosis circuit configured to perform a third diagnosis process based on the address signal, the first digital code, and the second digital code (Takado, Fig. 8, Step S840, Paragraphs 0104-0106, Matching the expected values to the actual output values is a third diagnosis process. The expected values and actual values are based on the address signal.).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/009012 A1) in view of obviousness in view of Makino et al. (US 2012/0008027 A1) in view of Shimizu et al. (US 2020/0059620 A1).
Regarding claim 4, the combination of Takado and Makino teaches the imaging device according to claim 2 (see claim 2 analysis). However, the combination of Takado and Makino does not teach wherein the first control line, the second control line, the first voltage supply line, the first plurality of pixel circuits, and the second plurality of pixel circuits are formed on a first semiconductor substrate, and the controller and the driving circuitry are formed on a second semiconductor substrate, the second semiconductor substrate bonded to the first semiconductor substrate.
In reference to Shimizu et al. (hereafter referred as Shimizu) Shimizu teaches wherein a first control line (Shimizu, Fig. 5, first control lines 302), a second control line (Shimizu, Fig. 5, second control lines 303), the plurality of pixel circuits (Shimizu, Fig. 1, Pixel Array 12), are formed on a first semiconductor substrate (Shimizu, Figs. 1 and 5, first semiconductor substrate 10), and
the controller (Shimizu, Fig. 1, Control circuit 27, Paragraph 0060) and the driving circuitry (Shimizu, Fig. 1, vertical scanner 21, Paragraph 0053) are formed on a second semiconductor substrate, the second semiconductor substrate bonded to the first semiconductor substrate (Shimizu, Fig. 1 and 5, second semiconductor substrate 20, Paragraphs 0051 and 0103).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Takado and Makino with the teaching of using separate substrates for the pixel array and the peripheral circuitry as seen in Shimizu to increase the proportion of the imaging area to the chip size, and a downsizing of the chip (Shimizu, Paragraph 0015). Further, since the first voltage supply line is part of the pixel array, it would have been obvious to one of ordinary skill in the art to form the first voltage supply line in the first semiconductor substrate since the semiconductor substrate contains the pixel array. Alternatively,
"A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense" KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007).
It would have been obvious to a person of ordinary skill, when pursuing the known options within his or her technical grasp (See KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007)), to form the first voltage supply line in the first semiconductor substrate since there is a finite number of identified, predictable potential solutions to the placement of the first voltage supply line (either placed on the first substrate or placed on the second substrate). Therefore, it would have been obvious to try placing the first voltage supply line in the first semiconductor substrate since it would provide the predicted results of supplying the voltages to the pixel array.
Alternatively, claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/009012 A1) in view of obviousness in view of Sohn (US 2014/0368710 A1).
Regarding claim 10, Takado teaches the imaging device according to claim 1 (see claim 1 analysis), further comprising:
a second voltage supply line (Takado, Fig. 2, VDD);
a third plurality of pixel circuits (Takado, Figs. 2 and 5, pixels 106), each pixel circuit including
a fourth terminal (Takado, Fig. 2, The first terminal is the gate of the transfer transistor M1, Paragraph 0039),
a fifth terminal (Takado, Fig. 2, The second terminal is the gate of the reset transistor M2, Paragraph 0039),
a sixth terminal (Takado, Fig. 2, The third terminal is the source of the transfer transistor M1, Paragraph 0039),
a second accumulation circuitry configured to accumulate a second electric charge (Takado, Fig. 2, amplifier transistor M3, Paragraphs 0044),
a third transistor configured to couple the sixth terminal to the second accumulation circuitry based on a second voltage of the fourth terminal (Takado, Fig. 2, transfer transistor M1, Signal Line TX, Paragraphs 0042-0044),
a fourth transistor configured to supply a third predetermined voltage (Takado, Fig. 2, voltage VDD) to the second accumulation circuitry based on a third voltage of the fifth terminal (Takado, Fig. 2, reset transistor M2, Paragraph 0044), and
a second output circuitry configured to output a second signal corresponding to a voltage in the second accumulation circuitry (Takado, Fig. 2, select transistor M4, Paragraph 0044);
the fourth terminal is coupled to the first control line (Takado, Fig. 2, signal line TX, Paragraph 0042),
the fifth terminal is coupled to the second control line (Takado, Fig. 2, signal line RES, Paragraph 0042), and
a plurality of signal lines, a first signal line is coupled to the output circuitry and a second signal line is coupled the second output circuitry, the second signal line being separate and distinct from the first signal line (Takado, Figs. 2 and 5, vertical output lines 108, A first signal line is a vertical output line 108 coupled to a pixel 110 in a first column. A second signal line is a vertical output line 108 coupled to a pixel 106 in a second column different from the first column.),
wherein the controller is further configured to apply only the first predetermined voltage to the second voltage supply line, within the each horizontal period (Takado, Fig. 2, Paragraph 0039, power source voltage terminal VDD is a constant supply.).
However, Takado does not teach the sixth terminal is coupled to the second voltage supply line.
In reference to Sohn, Sohn teaches a sixth terminal (Sohn, Fig. 3C, source of the transfer transistor) is coupled to a second voltage supply line (Sohn, Fig. 3C, voltage V, Paragraph 0048);
These arts are analogous since they are both related to imaging devices with light shielded pixels. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Takado with the light-shield pixel type as seen in Sohn since it is a known type of pixel used as a reference pixel.
Alternatively, claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/0098012 A1) in view of obviousness in view of Watanabe (US 2013/0235242 A1).
Regarding claim 14, Takado teaches the imaging device according to claim 13 (see claim 13 analysis). However, Takado does not teach further comprising: a second driving circuitry coupled to the second end of the first control line, the second driving circuitry configured to drive the first control line.
In reference to Watanabe, Watanabe teaches a first driving circuitry configured to drive the first control line (Watanabe, Fig. 1, vertical scanning circuits 21-1, Paragraph 0037), wherein
a first control line has a first end to which the first driving circuitry is coupled, and a second end (Watanabe, Paragraphs 0037-0041); and
a second driving circuitry coupled to a second end of a first control line, the second driving circuitry configured to drive the first control line (Watanabe, Fig. 1, vertical scanning circuits 21-2, Paragraph 0037).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Takado with the second driving circuitry as seen in Watanabe since if the vertical scanning circuits are arranged on both sides of the pixels for high speed, the driving performance of the CMOS image sensors can be improved as compared with the case that the vertical scanning circuit is arranged on only one side of the pixels (Watanabe, Paragraph 0006).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/0098012 A1) in view of obviousness in view of Suzuki et al. (US 2010/0134667 A1).
Regarding claim 15, Takado teaches the imaging device according to claim 13 (see claim 13 analysis), further comprising:
a third plurality of pixel circuits disposed in a first shielded pixel region, each pixel circuit including a shielded light-receiving element, (Takado, Fig. 5, Pixels 106, Paragraph 0023), wherein
the verification pixel region, the first shielded pixel region, the normal pixel region, and the control circuitry region are disposed in this order in the direction from the second end to the first end (Takado, Fig. 5).
However, Takado does not teach a second shielded pixel region, wherein
the verification pixel region, the first shielded pixel region, the normal pixel region, the second shielded pixel region, and the control circuitry region are disposed in this order in the direction from the second end to the first end.
In reference to Suzuki et al. (hereafter referred as Suzuki), Suzuki teaches a third plurality of pixel circuits disposed in a first shielded pixel region and a second shielded pixel region, each pixel circuit including a shielded light-receiving element (Suzuki, Fig. 3, optical black pixel regions 112d and 112c, Paragraph 0058-0059),
wherein the first shielded pixel region (Suzuki, Fig. 3, optical black pixel regions 112d), the normal pixel region (Suzuki, Fig. 3, effective pixel region 111), the second shielded pixel region (Suzuki, Fig. 3, optical black pixel regions 112c), and the control circuitry region (Suzuki, Fig. 3, vertical drive section 12, Paragraph 0033) are disposed in this order in the direction from the second end to the first end (Suzuki, Fig. 3).
These arts are analogous since they are both related to imaging devices with light shielded pixels. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Takado with the teaching of providing light-shielded pixels on both sides of the normal pixels as seen in Suzuki to obtain black levels from both sides of the pixel array. Further, by providing light-shielded pixels on both sides of the normal pixels, the limitation “wherein the verification pixel region, the first shielded pixel region, the normal pixel region, the second shielded pixel region, and the control circuitry region are disposed in this order in the direction from the second end to the first end” is met.
Allowable Subject Matter
Claims 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
With regard to claim 24, prior art of record neither anticipates nor renders obvious:
“The imaging device according to claim 12, further comprising: a fourth voltage supply line; and a fifth plurality of pixel circuits including a fifth pixel circuit and a sixth pixel circuit, each of the fifth pixel circuit and the sixth pixel circuit including a seventh terminal, an eighth terminal, a ninth terminal, a third accumulation circuitry configured to accumulate a third electric charge, a fifth transistor configured to couple the ninth terminal to the third accumulation circuitry based on a third voltage of the seventh terminal, a sixth transistor configured to supply a fourth predetermined voltage to the third accumulation circuitry based on a third voltage of the eighth terminal, and a third output circuitry configured to output a third signal corresponding to a voltage in the third accumulation circuitry the seventh terminal is coupled to the first control line, the eighth terminal is coupled to the second control line, and the ninth terminal is coupled to the fourth voltage supply line; and wherein the controller is further configured to apply a fourth voltage signal to the fourth voltage supply line, the fourth voltage signal having the first signal portion and a fourth signal portion within the each horizontal period, the fourth signal portion being separate and distinct from the first signal portion, the second signal portion, and the third signal portion.”
Claim 25 depends on and further limits claim 24. Therefore, claim 25 is allowable for the same reasons as claim 24.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Raynor (US 2016/0150171 A1): Raynor discloses inputs are preferably not left floating and are preferred to be connected to ground of a fixed voltage (Paragraph 0122).
Song et al. (US 2017/0336909 A1): Song et al. discloses sensor lines may be in floating states or grounded when not being driven (Paragraph 0126).
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/WESLEY J CHIU/ Examiner, Art Unit 2639
/TWYLER L HASKINS/ Supervisory Patent Examiner, Art Unit 2639