The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4, 6-14, 21, 23-26 and 28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the specification for the claimed limitation of “the die and the capacitor are stacked on top of the planar inductor”, as recited in claims 1, 21 and 23.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 10-14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (11,728,293) in view of Hill et al. (2020/0015348).
Regarding claims 1 and 21, Yun et al. teach in figures 4, 1B and related text a semiconductor device apparatus comprising:
a die 402 comprising an input port 408 and an output port 408; and
a multilayer package substrate (see figure 1A) comprising:
an input port 414/410 coupled (at least electrically coupled) to the output port 408 of the die:
an output port 414/410 coupled (at least electrically coupled) to the input port 408 of the die
contacts (pads) 410 on (above) a first surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board (PCB, since traces 126 are connected a PCB); and
a passive filter 422 comprising a planar inductor 416/128 coupling a given contact 134 (see figure 1B) of the contacts of the multilayer package substrate to the output port 414/410 of the multilayer package substrate 114, and
a capacitor 420 coupling another pad of the pads of the multilayer package substrate to the output port of the multilayer package substrate 414/410.
Yun et al. do not teach that the die and the capacitor are stacked on top of the planar inductor.
Hill et al. teach in figure 1A and related text that die 116 and a capacitor (located inside the die, see paragraph [0034]) are stacked on top of the inductor 104.
Yun et al. and Hill et al. are analogous art because they are directed to semiconductor devices comprising dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yun et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to stack the die and the capacitor on top of the planar inductor, as taught by Hill et al., in Yun et al.’s device, in order to reduce the real state size of the device.
Regarding claim 2, Yun et al. teach in figure 1B and related text that the planar inductor 128 is a spiral inductor formed on an interior layer of the multilayer package substrate.
Regarding claim 4, Yun et al. teach in figure 4 and related text that the capacitor 420 comprises a surface mount technology capacitor.
Regarding claim 10, Yun et al. teach in figure 4 and related text that the planar inductor is coupled to the given pad of the pads of the multilayer package substrate with a third via.
Regarding claim 11, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the planar inductor having an inductance of at least 200 nanohenries in Yun et al.’s device, in order to use the device in application which requires specific capacitance values.
Regarding claims 12-13, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a die comprises a power converter module, wherein the power converter module is a buck converter and wherein the output port of the die is configured to be coupled to a load mounted on the PCB in Yun et al.’s device, in order to use the device in application which requires specific electronic elements.
Regarding claim 14, Yun et al. teach in figure 14 and related text that the passive filter is configured to be coupled to a bulk filter mounted of the PCB, whereby the bulk filter is a first section filter of a two-section input filter for the power converter module and the passive filter is a second section filter of the two-section input filter for the power converter module.
Regarding claim 21, Yun et al. teach in figure 4 and related text connecting the apparatus to a printed circuit board (PCB, since traces 126 are connected a PCB).
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (11,728,293) and Hill et al. (2020/0015348), as applied to the claims above, and further in view of Nakahara (5,502,421).Regarding claim 6, Yun et al. and Hill et al. teach substantially the entire claimed structure, as applied to the claims above, except using a second spiral inductor coupled to the second input port of the die with a first via and to another pad of the pads of the multilayer package substrate with a second via.
Nakahara teaches in figure 3 and related text a second inductor 4b (see figure 2) coupled to a second input port of the die 100 with a third via 13a and to another pad (the square contact) of the pads of the multilayer package substrate with a fourth via 13b.
Yun et al. and Hill are analogous art because they are directed to semiconductor devices comprising dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yun et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a second spiral inductor coupled to the second input port of the die with a first via and to another pad of the pads of the multilayer package substrate with a second via, as taught by Nakahara, such that the passive filter in Yun et al.’s device comprising a second spiral inductor coupled to the second input port of the die with a first via and to another pad of the pads of the multilayer package substrate with a second via, in prior art’s device in order to use the device in an application which requires specific band width.
Regarding claims 7 and 9, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first spiral inductor and the second spiral inductor having about equal inductance and to form the first spiral inductor and the second spiral inductor having a combined inductance of at least 20 nanohenries, in prior art’s device in order to use the device in an application which requires specific capacitance.
Regarding claim 8, in the combined device, first spiral inductor and the second spiral inductor are spaced apart.
Claims 23-25 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (11,728,293) in view of Hill et al. (2020/0015348). Regarding claim 23, Yun et al. teach in figure 4 and related text a semiconductor device comprising:
a multilayer package substrate 100, 102 (see also figure 1A) or MCM 400 (see figure 4 and related text “package substrate in a chip module or multi-chip module (MCM).) that includes pads (un-numbered) on a first surface for connecting the semiconductor device to a printed circuit board (since traces 126 are connected a PCB), and
a passive filter 422 comprising a planar inductor 416 coupled to a first pad (un-numbered) of the pads of the multilayer package substrate with a first via (un-numbered) and to an output port 408 of the multilayer package substrate and a capacitor 420 coupling another pad of the pads of the multilayer package substrate to the output port of the multilayer package substrate, with a second via (un-numbered and to the output port of the multilayer package substrate; and
a die 402 attached to the multilayer package substrate, the die 402 comprising an input port 408 coupled to the output port 408 of the multilayer package substrate and an output port 414/410 coupled to a third pad (un-numbered) of the pads of the multilayer package substrate, wherein the die is stacked on top of the planar inductor
Yun et al. do not teach stacking the die and the capacitor on top of the planar inductor.
Hill et al. teach in figure 1A and related text that die 116 and a capacitor (located inside the die) are stacked on top of the inductor 104.
Yun et al. and Hill et al. are analogous art because they are directed to semiconductor devices comprising dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yun et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to stack the die and the capacitor on top of the planar inductor, as taught by Hill et al., in Yun et al.’s device, in order to reduce the real state size of the device.
Regarding claim 24, Yun et al. teach in figure 4 and related text that the multilayer package substrate 114, 102 further comprises: a first metal plating pattern 412 forming a first layer of the multilayer package substrate; and a dielectric layer (un-numbered) applied to the first metal plating pattern to form a second layer of the multilayer package substrate.
Regarding claim 25, Yun et al. teach in figure 4 and related text that the planar inductor is a spiral inductor (see figure 1A), and the second layer includes the spiral inductor 418.
Regarding claim 28, Yun et al. teach in figure 4 and related text a molding material 426 adhering to the die to the multilayer package substrate.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (11,728,293) and Hill et al. (2020/0015348), as applied to the claims above, and further in view of Nakahara (5,502,421).Regarding claim 26, Yun et al. and Hill et al. teach substantially the entire claimed structure, as applied to the claims above, except using a second spiral inductor coupled to the second input port of the die with a third via and to another pad of the pads of the multilayer package substrate with a fourth via.
Nakahara teaches in figure 3 and related text a second inductor 4b (see figure 2) coupled to a second input port of the die 100 with a third via 13a and to another pad (the square contact) of the pads of the multilayer package substrate with a fourth via 13b.
Hill et al., Yun et al. and Nakahara are analogous art because they are directed to devices comprising filters and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yun et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a second spiral inductor coupled to the second input port of the die with a third via and to another pad of the pads of the multilayer package substrate with a fourth via, as taught by Nakahara, such that the passive filter in prior art’s device comprising a second spiral inductor coupled to the second input port of the die with a third via and to another pad of the pads of the multilayer package substrate with a fourth via, in order to use the device in an application which requires specific band width.
Response to Arguments
Applicants argue that prior art does not teach
Hill et al. teach in figure 1A and related text that die 116 and a capacitor (located inside the die, see paragraph [0034]) are stacked on top of the inductor 104.
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O.N. /ORI NADAV/
7/31/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
