DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 8, 9, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0028278) hereinafter “Lee” in view of Tang et al. (US 2020/0327941) hereinafter “Tang”, Gao et al. (US 2020/0350440) hereinafter “Gao”, Nowak (US 2008/0122519) hereinafter “Nowak” and Hsu (US 2020/0343299) hereinafter “Hsu” and in further view of Fuller et al. (US 10497866) hereinafter “Fuller”.
Regarding claim 1, Fig. 1 of Lee teaches an ion controllable transistor-based neuromorphic synaptic device (Paragraph 0033) comprising: a channel area (Item C1) formed in a semiconductor substrate (SUB1); a source area (Item S1) and a drain area (Item D1) formed at both sides of the channel area (Item C1), respectively; an interlayer insulating film (Item GI1) provided in direct contact with the channel area (Item C1); an ionic species moving layer (Item M1) provided in direct contact with the interlayer insulating film (Item GI1); and a gate area (Item G1) provided in direct contact with the ionic species moving layer (Item M1); where the ion controllable transistor-based nueromorphic synaptic device is configured as a 3-terminal that includes a terminal of the gate area (Item G1), the terminal of the source area (Item S1) and the terminal of the drain area (Item D1); where, in response to a voltage pulse being applied to the gate area, the ion controllable transistor-based neuromorphic synaptic device analogically updates channel conductance by movement of ions present (Paragraph 0028) in the ionic species moving layer (Item M1).
Lee does not explicitly teach where the ionic species moving layer is a solid electrolyte layer.
Tang teaches an ion controllable transistor based neuromorphic synaptic device (Paragraph 0023), where a solid electrolyte layer (Item 60; Paragraph 0030) which is an ionic species moving layer (Paragraph 0030) provided in direct contact with a gate area (Item 70) and a interlayer insulating film (Item 50).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ionic species moving layer of Lee be a solid electrolyte layer because a solid state is known to allow for the movement of ions toward a interlayer insulating dielectric which changes the conductance for synaptic weight update (Tang Paragraph 0030) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Lee does not teach where the channel area includes carbon nanotube, MoSo2 or graphene.
Gao teaches a transistor comprising an electrolyte where a channel area includes graphene or MoS2 (Paragraph 0035).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the channel area include MoS2 or graphene because this material is known to act as a channel in a transistor having an electrolyte layer (Paragraph 0035) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Lee does not teach where the neuromorphic synaptic device is a 4-terminal device comprising a body terminal.
Fig. 2 of Nowak teaches a transistor which is a 4-terminal device which includes a body terminal, along with a terminal for a gate area, a terminal for a source area and a terminal for a drain area (Paragraph 0012).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a body terminal into the device of Lee such that the transistor is a 4 terminal device because the body terminal enables threshold voltage adjustment of the transistor (Nowak Paragraph 0012) and uniform threshold voltage for each like transistor in an integrated circuit (Nowak Paragraph 0013).
Lee does not teach where the ion controllable transistor based neuromorphic synaptic device further comprises an insulating film formed of germanium oxide provided in direct contact with the source area and the drain area.
Hsu teaches an insulating film (Item 209) formed of germanium oxide (Paragraph 0022) provided in direct contact with a source area (Item 203) and a drain area (Item 205).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ion controllable transistor based neuromorphic synaptic device further comprise an insulating film formed of germanium oxide provided in direct contact with the source area and the drain area because a germanium oxide insulating film electrically isolates the source and drain areas from other elements in the device (Hsu Paragraph 0022).
Lee does not teach where the solid electrolyte layer comprises an ion conductive polymer including polyethylene glycol (PEG), polyethylene glycol dimethacrylate (PEGDMA), polytetrafluoroethylene (PTFE), polyether ether ketone (PEEK), or nafion (C7HF1305S-C2F4).
Fuller teaches where a solid electrolyte layer in a transistor comprises an ion conductive polymer including nafion (Column 5, Lines 27-29).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the solid electrolyte layer comprise an ion conductive polymer including nafion because nafion is known to prevent electrons from passing through but allows ions to pass through (Nafion Column 5, Lines 24-27) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Lee does not explicitly teach where the ion controllable transistor-based neuromorphic synaptic device analogically updates the channel conductance by movement of ions present in the solid electrolyte layer, using a characteristic of the solid electrolyte layer in which ions are linearly and analogically distributed.
Fuller teaches an ion controllable transistor based neuromorphic synaptic device where in response to a voltage pulse being applied to the gate area (Column 6, Lines 24-33), the ion controllable transistor-based neuromorphic synaptic device analogically updates channel conductance by movement of ions present in the solid electrolyte layer (Column 9, Lines 9-13) and linearly distributed (Column 1, Lines 52-56).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ion controllable transistor-based neuromorphic synaptic device analogically updates the channel conductance by movement of ions present in the solid electrolyte layer, using a characteristic of the solid electrolyte layer in which ions are linearly and analogically distributed because neuromorphic computers can theoretically overcome efficiency bottlenecks that are inherent to digital computers by using analog memory to both process and store weights in a neural network (Fuller Column 1, Lines 38-42) and linear programming is needed for programming accuracy (Fuller Column 1, Lines 52-56).
Lee does not explicitly teach where the ion controllable transistor-based neuromorphic synaptic device analogically expresses a synaptic weight by analogically updating the channel conductance.
Fuller further teaches where the ion controllable transistor-based neuromorphic synaptic device analogically expresses a synaptic weight by analogically updating the channel conductance (Column 1, Lines 38-42).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ion controllable transistor-based neuromorphic synaptic device analogically expresses a synaptic weight by analogically updating the channel conductance because neuromorphic computers can theoretically overcome efficiency bottlenecks that are inherent to digital computers by using analog memory to both process and store weights in a neural network (Fuller Column 1, Lines 38-42).
Regarding claim 6, Lee further teaches wherein the channel area (Item C1), the source area (Item S1), and the drain area (Item D1) form a semiconductor area (Paragraph 0069 where Item SUB1 is a semiconductor) in a structure formed in a horizontal direction.
Regarding claim 8, Fig. 1 of Lee further teaches where the source area (Item S1) and the drain area (Item D1) are formed in a form in which impurity ions are implanted (Paragraph 0069) into a semiconductor material forming the channel area (Item C1).
Further, the process limitation of “where the source area and the drain area are formed in a form in which impurity ions are implanted into a semiconductor material forming the channel area” found in product claim 8 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 8 does not require the impurity ions are implanted into a semiconductor material forming the channel area, but simply that impurity ions are present in a semiconductor material forming the channel area. However, Tang further does disclose the source and drain areas formed in a form in which impurity ions are implanted into a semiconductor material forming a channel area (Paragraph 0048 where the conductive material may further comprise dopants that are incorporated during or after deposition).
Regarding claim 9, the combination of Lee, Tang, Gao, Nowak, Hsu and Fuller teaches all of the elements of the claimed invention as stated above except where the interlayer insulating film comprises at least one material of silicon oxide (SiO2), germanium oxide (GeO2), a solid oxide film, and a low-k dielectric film capable of insulating between the gate area and the channel area, when the ion controllable transistor-based neuromorphic synaptic device updates a synaptic weight update or a transistor operation.
Tang further teaches where an interlayer insulating film (Item 50) comprises at a solid oxide film (Paragraph 0029) capable of insulating between the gate area (Item 70) and the channel area (Top portion of Item 10), when the ion controllable transistor-based neuromorphic synaptic device updates a synaptic weight update (Paragraph 0030).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the interlayer insulating film comprises a solid oxide film capable of insulating between the gate area and the channel area, when the ion controllable transistor-based neuromorphic synaptic device updates a synaptic weight update because this allows the device to act as an ion controllable memory (Tang Paragraph 0022).
Regarding claim 14, Figs. 1 and 16 of Lee teaches a synaptic array comprising a plurality of ion controllable transistor-based neuromorphic synaptic devices (Paragraph 0033), where each of the plurality of ion controllable transistor based neuromorphic synaptic devices comprises: a channel area (Item C1) formed in a semiconductor substrate (SUB1); a source area (Item S1) and a drain area (Item D1) formed at both sides of the channel area (Item C1), respectively; an interlayer insulating film (Item GI1) provided in direct contact with the channel area (Item C1); an ionic species moving layer (Item M1) provided in direct contact with the interlayer insulating film (Item GI1); and a gate area (Item G1) provided in direct contact with the ionic species moving layer (Item M1); where the ion controllable transistor-based nueromorphic synaptic device is configured as a 3-terminal that includes a terminal of the gate area (Item G1), the terminal of the source area (Item S1) and the terminal of the drain area (Item D1); where, in response to a voltage pulse being applied to the gate area, the ion controllable transistor-based neuromorphic synaptic device analogically updates channel conductance by movement of ions present (Paragraph 0028) in the ionic species moving layer (Item M1).
Lee does not explicitly teach where the ionic species moving layer is a solid electrolyte layer.
Tang teaches an ion controllable transistor based neuromorphic synaptic device (Paragraph 0023), where a solid electrolyte layer (Item 60; Paragraph 0030) which is an ionic species moving layer (Paragraph 0030) provided in direct contact with a gate area (Item 70) and a interlayer insulating film (Item 50).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ionic species moving layer of Lee be a solid electrolyte layer because a solid state is known to allow for the movement of ions toward a interlayer insulating dielectric which changes the conductance for synaptic weight update and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Lee does not teach where the channel area includes carbon nanotube, MoSo2 or graphene.
Gao teaches a transistor comprising an electrolyte where a channel area includes graphene or MoS2 (Paragraph 0035).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the channel area include MoS2 or graphene because this material is known to act as a channel in a transistor having an electrolyte layer (Paragraph 0035) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Lee does not teach where the neuromorphic synaptic device is a 4-terminal device comprising a body terminal.
Fig. 2 of Nowak teaches a transistor which is a 4-terminal device which includes a body terminal, along with a terminal for a gate area, a terminal for a source area and a terminal for a drain area (Paragraph 0012).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a body terminal into the device of Lee such that the transistor is a 4 terminal device because the body terminal enables threshold voltage adjustment of the transistor (Nowak Paragraph 0012) and uniform threshold voltage for each like transistor in an integrated circuit (Nowak Paragraph 0013).
Lee does not teach where the ion controllable transistor based neuromorphic synaptic device further comprises an insulating film formed of germanium oxide provided in direct contact with the source area and the drain area.
Hsu teaches an insulating film (Item 209) formed of germanium oxide (Paragraph 0022) provided in direct contact with a source area (Item 203) and a drain area (Item 205).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ion controllable transistor based neuromorphic synaptic device further comprise an insulating film formed of germanium oxide provided in direct contact with the source area and the drain area because a germanium oxide insulating film electrically isolates the source and drain areas from other elements in the device (Hsu Paragraph 0022).
Lee does not teach where the solid electrolyte layer comprises an ion conductive polymer including polyethylene glycol (PEG), polyethylene glycol dimethacrylate (PEGDMA), polytetrafluoroethylene (PTFE), polyether ether ketone (PEEK), or nafion (C7HF1305S-C2F4).
Fuller teaches where a solid electrolyte layer in a transistor comprises an ion conductive polymer including nafion (Column 5, Lines 27-29).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the solid electrolyte layer comprise an ion conductive polymer including nafion because nafion is known to prevent electrons from passing through but allows ions to pass through (Nafion Column 5, Lines 24-27) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Lee does not explicitly teach where the ion controllable transistor-based neuromorphic synaptic device analogically updates the channel conductance by movement of ions present in the solid electrolyte layer, using a characteristic of the solid electrolyte layer in which ions are linearly and analogically distributed.
Fuller teaches an ion controllable transistor based neuromorphic synaptic device where in response to a voltage pulse being applied to the gate area (Column 6, Lines 24-33), the ion controllable transistor-based neuromorphic synaptic device analogically updates channel conductance by movement of ions present in the solid electrolyte layer (Column 9, Lines 9-13) and linearly distributed (Column 1, Lines 52-56).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ion controllable transistor-based neuromorphic synaptic device analogically updates the channel conductance by movement of ions present in the solid electrolyte layer, using a characteristic of the solid electrolyte layer in which ions are linearly and analogically distributed because neuromorphic computers can theoretically overcome efficiency bottlenecks that are inherent to digital computers by using analog memory to both process and store weights in a neural network (Fuller Column 1, Lines 38-42) and linear programming is needed for programming accuracy (Fuller Column 1, Lines 52-56).
Lee does not explicitly teach where the ion controllable transistor-based neuromorphic synaptic device analogically expresses a synaptic weight by analogically updating the channel conductance.
Fuller further teaches where the ion controllable transistor-based neuromorphic synaptic device analogically expresses a synaptic weight by analogically updating the channel conductance (Column 1, Lines 38-42).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ion controllable transistor-based neuromorphic synaptic device analogically expresses a synaptic weight by analogically updating the channel conductance because neuromorphic computers can theoretically overcome efficiency bottlenecks that are inherent to digital computers by using analog memory to both process and store weights in a neural network (Fuller Column 1, Lines 38-42).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0028278) hereinafter “Lee” in view of Tang et al. (US 2020/0327941) hereinafter “Tang”, Gao et al. (US 2020/0350440) hereinafter “Gao”, Nowak (US 2008/0122519) hereinafter “Nowak”, Hsu (US 2020/0343299) hereinafter “Hsu” and Fuller et al. (US 10497866) hereinafter “Fuller” and in further view of Bragaglia et al. (US 2021/0125043) hereinafter “Bragaglia”.
Regarding claim 15, the combination of Lee, Tang, Gao, Nowak, Hsu and Fuller teaches all of the elements of the claimed invention as stated above.
While Lee teach an array comprising a plurality of ion controllable transistor based neuromorphic synaptic devices, Lee does not explicitly teach where the synaptic array is configured to support a parallel operation of updating synaptic weight through a terminal of the gate area and reading the updated synaptic weight through a terminal of the drain area in each of the plurality of ion controllable transistor-based neuromorphic synaptic devices.
Bragaglia teaches where a synaptic array is configured to support a parallel operation of updating synaptic weight through a terminal of the gate area and reading the updated synaptic weight through a terminal of the drain area in each of the plurality of ion controllable transistor-based neuromorphic synaptic devices (Paragraph 0057).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the synaptic array taught by the combination of Lee and Tang be configured to support a parallel operation of updating synaptic weight through a terminal of the gate area and reading the updated synaptic weight through a terminal of the drain area in each of the plurality of ion controllable transistor-based neuromorphic synaptic devices because this can be used to increase the tunability of synaptic weights when the device is used in a neuromorphic apparatus (Bragaglia Paragraph 0057).
Response to Arguments
Applicant’s arguments, see Applicant’s REMARKS, filed 05/22/2025, with respect to the rejection(s) of claim(s) 1 and 14 under 35 USC 103(a) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee, Tang, Gao, Nowak, Hsu and Fuller.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached on 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891