Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Appeal Brief filed on 03/05/2026. Claim(s) 1-6, 8, 10, and 14-16 are cancelled. Claim(s) 7, 9 and 11-13 are pending in this case. Claim(s) 7 and 9 are independent claims.
In view of the Appeal Brief filed on 03/05/2026, PROSECUTION IS HEREBY REOPENED. Set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over “Supporting Very Large Models using Automatic Dataflow Graph Partitioning”, https://arxiv.org/pdf/1807.08887, Minjie et al, 02/20/2019, hereinafter referred to as Minjie in view of JP4756675B2 and further in view of Isard et al. (US Patent No. 20080098375 A1), hereinafter referred to as Isard.
With respect to claim 7, Minjie disclose:
An electronic device comprising a plurality of processing circuits, comprising: a circuitry, configured to perform the steps of: receiving a model and input data for execution ((Under the broadest reasonable interpretation consistent with the specification, the term "circuitry" can comprise a CPU, GPU, VPU, etc. found in paragraph [0013] of the specification.) On page 2, paragraph 3, Minjie discloses using large DNN models including Wide ResNet [1] and Multi-layer RecurrentNeural Networks [20], across multiple GPU devices and evaluates the system using large CNN and RUN models.)
analyzing the model at runtime to obtain a graph partition size of the model (On page 3 (3.2 How to optimize partitioning for a graph?), Minjie discloses partitioning each tensor in the dataflow graph, each of which has different execution time and per-GPU memory consumption. In Fig. 10 and Page 12, paragraph 2, Tofu shows the execution time of training one batch on 8 GPUs for RNN. Observing the impact of communication on the execution time.)
partitioning the model into a plurality of graphs based on the graph partition size, wherein each of the graphs comprises a portion of operations of the model (In Fig. 5 and 9, pages 5 -6 (Partitioning the dataflow graph), paragraph 4, Minjie discloses that a model represented as a dataflow graph is partitioned into multiple graph portions through partitioning of the graph's operators and tensors. Partitioning of a DNA dataflow graph across multiple devices therefore teaches partitioning the model into a plurality of graphs.)
deploying the plurality of graphs to at least two of the processing circuits, respectively (On page 12 (Parallel DNN training), Minjie discloses parallel execution across multiple GPUs. On page 13, paragraph 4, Minjie discloses partition and-reduce parallel patterns of operators using TDL description and optimizes partitioning for the entire dataflow graph. )
Generating output data according to results of the at least two of the processing circuits executing the plurality of graphs (On page 12 (7.4 Partition Results), Minjie discloses the partition found by Tofu for WResNet 152-10. ResNet-152 contains 4 groups of residual blocks. In Fig. 11, Minjie discloses the partition found by Tofu for WResNet-152-10 on 8 GPUs.)
With respect to claim 7, Minjie does not explicitly disclose:
wherein step of analyzing the model at runtime to obtain the graph partition size of the model comprises: generating a prediction error of the model according to a difference between a previous estimated performance and a previous actual performance of the model when the model is executed previously, wherein the previous estimated performance and the previous actual performance of the model are a previous memory usage and a previous actual memory usage of the model, respectively
updating a previous graph partition size to generate the graph partition size according to the prediction error every time the model is executed
However, it is known by JP4756675B2 to disclose:
Wherein step of analyzing the model at runtime to obtain the graph partition size of the model comprises: generating a prediction error of the model according to a difference between a previous estimated performance and a previous actual performance of the model when the model is executed previously, wherein the previous estimated performance and the previous actual performance of the model are a previous memory usage and a previous actual memory usage of the model, respectively (On pages 6–7, paragraphs 11–1, disclose comparing predicted processing amounts with actual processing amounts and determining an error associated with each prediction. Also, select the model having the smallest error.)
Minje and JP4756675B2 are analogous pieces of art because both references concern
analyzing computer resource capacity. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Minjie with a system that partitions very large DNN models across multiple GPU devices as taught by Minjie, while predicting future trends by analyzing computer resource capacity transitions in order to update the system configuration and settings as taught by JP4756675B2. The motivation for doing so would have been to optimize partitions for the dataflow graph and to generate the partitioned graph (See (Page 5 (4.2 Analyzing TDL Descriptions) of Minjie).
With respect to claim 7, Minje and JP4756675B2 does not explicitly disclose:
updating a previous graph partition size to generate the graph partition size according to the prediction error every time the model is executed
However, it is known by Isard to disclose:
Updating a previous graph partition size to generate the graph partition size according to the prediction error every time the model is executed (In paragraph [0042], Isard discloses automatically modifying a graph during runtime, the job manager (or other entity) can automatically modify the graph to improve efficiency. The modifications are based on runtime information, topology of the distributed execution engine, and/or the distributed application represented by the graph.)
Minje in view of JP4756675B2 and Isard are analogous pieces of art because both references concern analyzing computer resource capacity. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Isard with runtime information, topology of the distributed execution engine, and/or the distributed application represented by the graph as taught by Isard. The motivation for doing so would have been to automatically modify the graph to improve efficiency (See [0004] of Isard).
With respect to claim 9, Minjie disclose:
A non-transitory machine-readable storage medium comprising program codes, wherein when the program codes are executed by a processor, the processor performs the steps of: receiving a model and input data for execution ((Under the broadest reasonable interpretation consistent with the specification, the term "circuitry" can comprise a CPU, GPU, VPU, etc. found in paragraph [0013] of the specification.) On page 2, paragraph 3, Minjie discloses using large DNN models including Wide ResNet [1] and Multi-layer RecurrentNeural Networks [20], across multiple GPU devices and evaluates the system using large CNN and RUN models.)
analyzing the model at runtime to obtain a graph partition size of the model (On page 3 (3.2 How to optimize partitioning for a graph?), Minjie discloses partitioning each tensor in the dataflow graph, each of which has different execution time and per-GPU memory consumption. In Fig. 10 and Page 12, paragraph 2, Tofu shows the execution time of training one batch on 8 GPUs for RNN. Observing the impact of communication on the execution time.)
partitioning the model into a plurality of graphs based on the graph partition size, wherein each of the graphs comprises a portion of operations of the model (In Fig. 5 and 9, pages 5 -6 (Partitioning the dataflow graph), paragraph 4, Minjie discloses that a model represented as a dataflow graph is partitioned into multiple graph portions through partitioning of the graph's operators and tensors. Partitioning of a DNA dataflow graph across multiple devices therefore teaches partitioning the model into a plurality of graphs.)
deploying the plurality of graphs to at least two of the processing circuits, respectively (On page 12 (Parallel DNN training), Minjie discloses parallel execution across multiple GPUs. On page 13, paragraph 4, Minjie discloses partition and-reduce parallel patterns of operators using TDL description and optimizes partitioning for the entire dataflow graph. )
Generating output data according to results of the at least two of the processing circuits executing the plurality of graphs (On page 12 (7.4 Partition Results), Minjie discloses the partition found by Tofu for WResNet 152-10. ResNet-152 contains 4 groups of residual blocks. In Fig. 11, Minjie discloses the partition found by Tofu for WResNet-152-10 on 8 GPUs.)
With respect to claim 7, Minjie does not explicitly disclose:
wherein step of analyzing the model at runtime to obtain the graph partition size of the model comprises: generating a prediction error of the model according to a difference between a previous estimated performance and a previous actual performance of the model when the model is executed previously, wherein the previous estimated performance and the previous actual performance of the model are a previous memory usage and a previous actual memory usage of the model, respectively
updating a previous graph partition size to generate the graph partition size according to the prediction error every time the model is executed
However, it is known by JP4756675B2 to disclose:
Wherein step of analyzing the model at runtime to obtain the graph partition size of the model comprises: generating a prediction error of the model according to a difference between a previous estimated performance and a previous actual performance of the model when the model is executed previously, wherein the previous estimated performance and the previous actual performance of the model are a previous memory usage and a previous actual memory usage of the model, respectively (On pages 6–7, paragraphs 11–1, disclose comparing predicted processing amounts with actual processing amounts and determining an error associated with each prediction. Also, select the model having the smallest error.)
Minje and JP4756675B2 are analogous pieces of art because both references concern
analyzing computer resource capacity. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Minjie with a system that partitions very large DNN models across multiple GPU devices as taught by Minjie, while predicting future trends by analyzing computer resource capacity transitions in order to update the system configuration and settings as taught by JP4756675B2. The motivation for doing so would have been to optimize partitions for the dataflow graph and to generate the partitioned graph (See (Page 5 (4.2 Analyzing TDL Descriptions) of Minjie).
With respect to claim 9, Minje and JP4756675B2 does not explicitly disclose:
updating a previous graph partition size to generate the graph partition size according to the prediction error every time the model is executed
However, it is known by Isard to disclose:
Updating a previous graph partition size to generate the graph partition size according to the prediction error every time the model is executed (In paragraph [0042], Isard discloses automatically modifying a graph during runtime, the job manager (or other entity) can automatically modify the graph to improve efficiency. The modifications are based on runtime information, topology of the distributed execution engine, and/or the distributed application represented by the graph.)
Minje in view of JP4756675B2 and Isard are analogous pieces of art because both references concern analyzing computer resource capacity. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Isard with runtime information, topology of the distributed execution engine, and/or the distributed application represented by the graph as taught by Isard. The motivation for doing so would have been to automatically modify the graph to improve efficiency (See [0004] of Isard).
Regarding claim 11, Minjie in view of JP4756675B2 and Isard disclose the elements of claim 9. In addition, Minjie disclose:
The non-transitory machine-readable storage medium of claim 9, wherein the model is an artificial neural network model (On page 1, paragraph 3, Minjie discloses a DNN mode consisting of many layers, each parameterized by its own weights.)
Regarding claim 12, Minjie in view of JP4756675B2 and Isard disclose the elements of claim 9. In addition, Minjie disclose:
The non-transitory machine-readable storage medium of claim 9, wherein the plurality of processing circuits comprise at least two of a central processing unit (CPU), a graphics processing unit (GPU), a vision processing unit (VPU) and a deep learning accelerator (DLA) (On page 2 (2 Background), paragraph 5, Minjie discloses training very large DN models using CPU and GPU.)
Regarding claim 13, Minjie in view of JP4756675B2 and Isard disclose the elements of claim 9. In addition, Minjie disclose:
The non-transitory machine-readable storage medium of claim 9, wherein step of analyzing the model at runtime to obtain the graph partition size of the model comprises: using a gradient boosting model to estimate the model to obtain the graph partition size of the model (On page 6 (Group forward and backward operations, paragraph 5), Tofu discloses that the DN models are trained using a gradient-based optimization method.)
Pertaining to Rejection under 101
Claims 7, 9 and 11-13 are withdrawn under 35 USC § 101.
Pertaining to Rejection under 103
Applicant’s arguments in regard to the examiner’s rejections under 35 USC 103 are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVEL HONORE whose telephone number is (703)756-1179. The examiner can normally be reached Monday-Friday 8 a.m. -5:30 p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mariela D Reyes can be reached at (571) 270-1006. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
EVEL HONORE
Examiner
Art Unit 2142
/Mariela Reyes/Supervisory Patent Examiner, Art Unit 2142
Prosecution Insights