DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-27 and 31-33 are pending in this application. Claims 1, 15, 27 and 33 are currently amended; claims 3-14, 16-18, 20-26 and 31-32 are previously presented; claims 2 and 19 are original; claims 28-30 are cancelled.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Objections
Claims 1-27 and 31-32 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 1 lines 13-14, “grouped adder trees units” should read “grouped adder tree units” instead for better clarity. Claim 15 recites a similar limitation in line 14 and is objected to for the same reason. Claims 2-14 and 31-32 inherit the same deficiency as claim 1 by reason of dependence. Claims 16-27 inherit the same deficiency as claim 15 by reason of dependence.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B. See MPEP 3111.04 for more information.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 33 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 33 recites “wherein the provision of the data parallelism comprises providing a non-split identical weight, from one weight buffer, to the adder tree unit and another adder tree unit that comprises another multiplier and another adder tree of the operator, wherein the adder tree unit and the another adder tree unit each independently generate a respective output value for a respective different channel of an output feature map using the non-split identical weight”. This limitation lacks written description support because the specification fails to disclose generating a respective output value for a respective different channel of an output feature map using the same weight. As shown in Fig. 1B each channel of an output feature map 210 is generated from a corresponding filter 110 (i.e., filter 110-1 is used for generating the first channel of the output feature map 210 and filter 110-n is used for generating the Nth channel of the output feature map 210). There is no disclosure that weight values of filter 110-1 is used generate an output value of any other channels 2-N of the output feature map 210. Furthermore, Applicant has not cited any portion of the specification to support the claim amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-27 are rejected under 35 U.S.C. 103 as being unpatentable over Gibson et al. (US 11,625,581 B2), hereinafter Gibson, in view of Lee et al. (US 20190171930 A1), hereinafter Lee.
Regarding claim 15, Gibson teaches a neural network operation method, comprising:
storing an input feature map and a weight (Gibson Fig. 2 and col 6 lines 14-20; input feature map - input data; weight – weights);
mapping the input feature map to an operator and mapping the weight to the operator, (Gibson Fig. 2 and col 6 lines 29-34; operator - convolution engines 240, accumulator 245, and accumulation buffer 250; plurality of adder tree units - convolution engines 240 and accumulator 245);
using the operator, performing an operation between the mapped input feature map and the mapped weight (Gibson Figs. 2-3 and col 6 lines 34-40; operation - convolution operation);
wherein the operator comprises an adder tree unit, comprising a multiplier and an adder tree, configured to perform the operation (Gibson Fig. 3 and col 6 lines 40-43; multiplier – at least one of the plurality of elements of multiply logic 310; adder tree - plurality of elements of addition logic 320);
wherein, response to a bit length of the input feature map being greater than the reference bit length:
dynamically group two or more of a plurality of adder tree units into a single processing entity to perform a multiply-and-accumulate operation between the input feature map and the weight over a plurality of cycles; and mapping the input feature map and the weight to the grouped adder trees unit such that, for a same number of the adder tree units performing the operation, a number of channels of an output feature map is reduced proportionally to the bit length of the input feature map, and wherein the single processing entity is configured to sum respective outputs of the two or more adder tree units to generate a single output value for the reduced number of channels, to provide the mixed precision operation (Gibson Figs. 2-3 and col 6 lines 34-40; this is a contingent limitation that is not required to be performed if the bit length of the input feature map is equal to the reference bit length).
Gibson does not explicitly teach mapping the input feature map to an operator and mapping the weight to the operator, to provide one or both of a mixed precision operation and data parallelism; and wherein the operator comprises an adder tree unit, comprising a multiplier and an adder tree, configured to perform the operation by a unit of a reference bit length.
However, on the same field of endeavor, Lee discloses mapping an input feature map and a weight to an operator, to provide one or both of a mixed precision operation and data parallelism, and performing an operation by a unit of a reference bit length using the operator (Lee Figs. 5A-5B, 8A and 9C and paragraphs [0120-0122 and 0132-0133]; unit of a reference bit length – 8-bit (i.e., the precision of the sub-multipliers).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson using Lee and map the input feature map and the weight to the operator, to provide one or both of a mixed precision operation and data parallelism; and configure the operator to perform the operation by the reference bit length in order to increase the utilization of the operator when the inputs to the convolution operation is smaller than the operator precision by providing operands that can be performed in parallel to each of the sub-multipliers for the convolution operation (Lee paragraphs [0107-0108, 0122 and 0132-0133]).
Therefore, the combination of Gibson as modified in view of Lee teaches mapping the input feature map to an operator and mapping the weight to the operator, to provide one or both of a mixed precision operation and data parallelism; and wherein the operator comprises an adder tree unit, comprising a multiplier and an adder tree, configured to perform the operation by a unit of a reference bit length.
Regarding claim 16, Gibson as modified in view of Lee teaches all the limitations of claim 15 as stated above. Further, Gibson as modified in view of Lee teaches wherein the mapping of the input feature map comprises: in response to a bit length of the input feature map being half the reference bit length, increasing a number of channels of the input feature map to be mapped to the operator by a factor of two, to provide the mixed precision operation (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 17, Gibson as modified in view of Lee teaches all the limitations of claim 15 as stated above. Further, Gibson as modified in view of Lee teaches wherein the mapping of the weight comprises: in response to a bit length of the weight being half the reference bit length, mapping the weight to the adder tree unit by a unit of a group of two weights, including the weight, that each have half the reference bit length (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length), and
wherein the mapping of the input feature map comprises: in response to a bit length of the input feature map being half the reference bit length, mapping the input feature map to the adder tree unit by a unit of a group of two input feature maps, including the input feature map, that each have half the reference bit length (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 18, Gibson as modified in view of Lee teaches all the limitations of claim 17 as stated above. Further, Gibson as modified in view of Lee teaches wherein the performing the operation comprises:
respectively transforming the two input feature maps into first transformed data and second transformed data that each have the reference bit length (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length);
performing a first multiply operation between the first transformed data and a first weight comprised in the group of the two weights, using a first multiplier (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length);
performing a second multiply operation between the second transformed data and a second weight comprised in the group of the two weights, using a second multiplier, where one of the first multiplier and the second multiplier is the multiplier (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length); and
adding an output of the first multiplier, resulting from the performing of the first multiply operation, to an output of the second multiplier, resulting from the performing of the second multiply operation (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 19, Gibson as modified in view of Lee teaches all the limitations of claim 18 as stated above. Further, Gibson as modified in view of Lee teaches wherein the performing the operation further comprises: shifting the output of the first multiplier (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 20, Gibson as modified in view of Lee teaches all the limitations of claim 15 as stated above. Further, Gibson as modified in view of Lee teaches wherein the mapping of the input feature map comprises: in response to the bit length of the input feature map being double the reference bit length, mapping the input feature map and the weight to the operator such that the number of channels of the output feature map is halved, to provide the mixed precision operation (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 21, Gibson as modified in view of Lee teaches all the limitations of claim 15 as stated above. Further, Gibson as modified in view of Lee teaches wherein the mapping of the weight comprises: in response to a bit length of the weight being double the reference bit length, grouping two adder tree units together into one group of adder tree units and mapping the weight to the one group of the adder tree units, where one of the two adder tree units is the adder tree unit and another of the two adder tree units is another adder tree unit of the operator (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length).
Regarding claim 22, Gibson as modified in view of Lee teaches all the limitations of claim 21 as stated above. Further, Gibson as modified in view of Lee teaches wherein the mapping of the weight comprises:
mapping a first portion of the weight to the adder tree unit (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length); and
mapping a second portion of the weight to the other adder tree unit of the operator (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length).
Regarding claim 23, Gibson as modified in view of Lee teaches all the limitations of claim 15 as stated above. Further, Gibson as modified in view of Lee teaches wherein the mapping of the input feature map comprises: in response to the bit length of the input feature map being double the reference bit length, grouping two adder tree units together into one group of adder tree units and mapping the input feature map to the one group of the adder tree units, where one of the two adder tree units is the adder tree unit and another of the two adder tree units is another adder tree unit of the operator (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 24, Gibson as modified in view of Lee teaches all the limitations of claim 23 as stated above. Further, Gibson as modified in view of Lee teaches wherein the mapping of the input feature map comprises: mapping a first portion of the input feature map to the one group of the adder tree units in a first cycle; and mapping a second portion of the input feature map to the one group of the adder tree units in a second cycle (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 25, Gibson as modified in view of Lee teaches all the limitations of claim 15 as stated above. Further, Gibson as modified in view of Lee teaches wherein the performing the operation comprises:
performing a first operation between a first portion of the input feature map and a first portion of the weight in a first cycle, and performing a second operation between a second portion of the input feature map and the first portion of the weight in a second cycle (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the input feature map is equal to the reference bit length); and
performing a third operation between the first portion of the input feature map and a second portion of the weight in the first cycle, and performing a fourth operation between the second portion of the input feature map and the second portion of the weight in the second cycle (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 26, Gibson as modified in view of Lee teaches all the limitations of claim 15 as stated above. Further, Gibson as modified in view of Lee teaches
wherein the operator further comprises one or more another adder tree unit, that each comprise a corresponding other multiplier and a corresponding other adder tree (Gibson Fig. 2; one or more other adder tree units – at least one of the other 240 and 245 pairs of the n pairs; col 6 lines 26-43; each convolution engine includes a corresponding multiplier and a corresponding adder tree to perform their respective convolution operation), and
wherein the mapping of the weight comprises:
grouping the adder tree unit and the one or more other adder tree units together into one group of adder tree units by a unit of a weight parallelism size and mapping a same weight to the one group of the adder tree units, to provide the data parallelism (Lee Figs. 8A and 9C and paragraphs [0121-0123 and 0132-0133]). The motivation to combine is the same as claim 15.
Regarding claim 27, Gibson as modified in view of Lee teaches all the limitations of claim 15 as stated above. Further, Gibson as modified in view of Lee teaches wherein the operator further comprises one or more other adder tree units, each other adder tree of the one or more other adder tree units comprising a corresponding other multiplier and a corresponding other adder tree (Gibson Fig. 2; one or more other adder tree units – at least one of the other 240 and 245 pairs of the n pairs; col 6 lines 26-43; each convolution engine includes a corresponding multiplier and a corresponding adder tree to perform their respective convolution operation), and
wherein the mapping of the weight comprises: mapping the weight to the operator based on the reference bit length such that a product of a weight parallelism size and a total number of adder tree units, including the adder tree unit and the one or more other adder tree units, is constant, to provide the data parallelism (Lee Fig. 9C and paragraphs [0132-0133]). The motivation to combine is the same as claim 15.
Claims 1-4, 7-27 and 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Gibson in view of Makino et al. (US 20210011686 A1), hereinafter Makino and Lee.
Regarding claim 1, Gibson teaches a neural network operation device, comprising:
an input feature map buffer configured to store an input feature map (Gibson Fig. 2 and col 6 lines 14-20; input feature map buffer - input buffer 235; input feature map - input data);
a weight buffer configured to store a weight (Gibson Fig. 2 and col 6 lines 14-20; weight buffer - coefficient buffer 230; weight – weights);
an operator comprising a plurality of adder tree units configured to perform an operation between the input feature map and the weight (Gibson Figs. 2-3 and col 6 lines 32-57; operator – convolution engines 240, accumulator 245, and accumulation buffer 250; plurality of adder tree units - convolution engines 240 and accumulator 245; operation - convolution operation); and
a controller (Gibson Fig. 2 and col 5 lines 64-67; controller – command decoder 220, coefficient control buffer controller 225, input buffer controller 215),
wherein each of the adder tree units comprises a multiplier and an adder tree (Gibson Fig. 3 and col 6 lines 40-43; multiplier – at least one of the plurality of elements of multiply logic 310; adder tree - plurality of elements of addition logic 320).
Gibson does not explicitly teach an operator comprising a plurality of adder tree units configured to perform an operation between the input feature map and the weight by a unit of a reference bit length; and a controller configured to map the input feature map and the weight to the operator to provide one or both of a mixed precision operation and data parallelism, wherein the controller is configured to: in response to a bit length of the input feature map being greater than the reference bit length, dynamically group two or more of the plurality of adder tree units into a single processing entity to perform a multiply-and-accumulate operations between the input feature maps and the weight over a plurality of cycles, and map the input feature map and the weight to the grouped adder tree units such that, for a same number of the adder tree units performing the operation, a number of channels of an output feature map is reduced proportionally to the bit length of the input feature map, and wherein the single processing entity is configured to sum respective outputs of the two or more adder tree units to generate a single output value for the reduced number of channels, to provide the mixed precision operation.
However, on the same field of endeavor, Makino discloses a multiplication unit configured to perform an operation between a multiplicand and a multiplier by a unit of a reference bit length; and a controller configured to map the multiplicand and the multiplier to the multiplication unit to provide one or both of a mixed precision operation and data parallelism (Makino Fig. 1 and paragraphs [0066 and 0074-0078]; unit of a reference bit length – half-precision mode/bit length; controller – mode selection section; the mode selection section controls how the multiplicand and the multiplier are mapped and input to the multiplying units; paragraph [0286]). Furthermore, Makino discloses in response to a bit length of an operand (i.e. the multiplicand and/or the multiplier) being greater than the reference bit length, dynamically grouping two multiplying units together into one group (i.e., as a single processing entity) and mapping the multiplicand to the one group of the two multiplying units by providing the higher-order bit portion B10 to the one group in a first clock cycle and the lower-order bit portion B11 to the one group in a second clock cycle, and mapping the operands (the multiplicand and the multiplier) to the one group of two multiplying units to provide the mixed precision operation such that for a same number of the multiplying units performing the operation, a number of output is reduced proportionally to the bit length of the operands (Makino Figs. 11-12, 16 and paragraphs [0073, 0077-0078, 0139, 0148, 0153, 0157]; bit length being greater than the reference bit length – single-precision and/or double precision; multiplicand – input B). Further, Makino discloses the group is configured to sum respective outputs of the two or more multiplying units to generate a single output value to provide the mixed precision operation (Makino Figs. 11-12, 16 and paragraphs [0153 and 0186]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino and configure the CNN hardware system of Gibson to include a mode selection section for mapping the input feature map and the weight to the operator based on a bit length of the input feature map and the weight and configure the convolution engines 240 and accumulator 245 to perform the convolution operation between the input feature map and the weight by a unit of a reference bit length such that in response to a bit length of the input feature map being double the reference bit length, group two convolution engines and accumulator together into a single processing entity and map the input feature to the group of the two convolution engines and accumulator by providing the higher-order bit portion of the input feature map to the group in a first clock cycle and the lower-order bit portion of the input feature map to the one group in a second first clock cycle and adding the outputs of the group to generate a single convolution output value in order to provide a variable precision CNN hardware system that can efficiently perform convolution operation with high-precision input feature map using lower precision circuitry (Makino paragraph [0010, 0066, 0077-0078]).
Therefore, the combination of Gibson as modified in view of Makino teaches an operator comprising a plurality of adder tree units configured to perform an operation between the input feature map and the weight by a unit of a reference bit length; and a controller configured to map the input feature map and the weight to the operator to provide one or both of a mixed precision operation and data parallelism, wherein the controller is configured to: in response to a bit length of the input feature map being greater than the reference bit length, dynamically group two or more of the plurality of adder tree units into a single processing entity to perform a multiply-and-accumulate operations between the input feature maps and the weight over a plurality of cycles, and map the input feature map and the weight to the grouped adder tree units such that, for a same number of the adder tree units performing the operation, a number of output feature map is reduced proportionally to the bit length of the input feature map, wherein the single processing entity is configured to sum respective outputs of the two or more adder tree units to generate a single output value, to provide the mixed precision operation.
Gibson as currently modified in view of Makino does not explicitly teach wherein the controller is configured to: in response to a bit length of the input feature map being greater than the reference bit length, dynamically group two or more of the plurality of adder tree units into a single processing entity to perform a multiply-and-accumulate operations between the input feature maps and the weight over a plurality of cycles, and map the input feature map and the weight to the grouped adder trees unit such that, for a same number of the adder tree units performing the operation, a number of channels of an output feature map is reduced proportionally to the bit length of the input feature map, wherein the single processing entity is configured to sum respective outputs of the two or more adder tree units to generate a single output value for the reduced number of channels, to provide the mixed precision operation.
However, on the same field of endeavor, Lee discloses a number of channels of an output feature map is reduced proportionally to a bit length of the input feature map. For example, the number of channels of the output feature map is halved when the bit length of the input feature map and a
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino using Lee and generalize the teaching of Lee by mapping the input feature map and the weight to the grouped adder trees unit such that a number of channels of an output feature map is reduced proportionally to the bit length of the input feature map (i.e., halved in response to the bit length of the input feature map being double than the reference bit length) so that the convolution operation can still be performed on higher precision input feature maps using lower-precision circuitry (Makino paragraph [0010, 0066]).
Therefore, the combination of Gibson as modified in view of Makino and Lee teaches wherein the controller is configured to: in response to a bit length of the input feature map being greater than the reference bit length, dynamically group two or more of the plurality of adder tree units into a single processing entity to perform a multiply-and-accumulate operation between the input feature map and the weight over a plurality of cycles, and map the input feature map and the weight to the grouped adder trees units such that, for a same number of the adder tree units performing the operation, a number of channels of an output feature map is reduced proportionally to the bit length of the input feature map, and wherein the single processing entity is configured to sum respective outputs of the two or more adder tree units to generate a single output value for the reduced number of channels, to provide the mixed precision operation.
Regarding claim 2, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above.
Gibson as currently modified in view of Makino and Lee does not explicitly teach wherein the controller is configured to: in response to a bit length of the input feature map being half the reference bit length, increase a number of channels of the input feature map to be mapped to the operator by a factor of two, to provide the mixed precision operation.
However, on the same field of endeavor, Lee discloses increasing a number of channels of an input feature map to be mapped to an operator by a factor of two, to provide a mixed precision operation in response to a bit length of the input feature map being half a reference bit length (Lee Fig. 5B and paragraph [0108]; pixel value
F
1
and
F
0
are from different channels; bit length of the input feature map – 8-bit; reference bit length – 16-bit).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino and Lee using Lee and configure the controller to increase the number of channels of the input feature map to be mapped to the convolution engines and accumulator by a factor of two, to provide a mixed precision operation in response to a bit length of the input feature map being half a reference bit length in order to optimize the utilization and/or double the throughput of the convolution engines (Lee Fig. 5B and paragraph [0103, 0109]).
Therefore, the combination of Gibson as modified in view of Makino and Lee teaches wherein the controller is configured to: in response to a bit length of the input feature map being half the reference bit length, increase a number of channels of the input feature map to be mapped to the operator by a factor of two, to provide the mixed precision operation.
Regarding claim 3, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above.
Gibson as currently modified in view of Makino and Lee does not explicitly teach wherein the controller is configured to: in response to a bit length of the weight being half the reference bit length, map the weight to an adder tree unit by a unit of a group of two weights, including the weight, that each have half the reference bit length; and in response to a bit length of the input feature map being half the reference bit length, map the input feature map to the adder tree unit by a unit of a group of two input feature maps, including the input feature map, that each have half the reference bit length.
However, on the same field of endeavor, Lee discloses in response to a bit length of a weight being half a reference bit length, map the weight to a multiplier unit by a unit of a group of two weights each having half the reference bit length; and in response to a bit length of an input feature map being half the reference bit length, map an input feature map to the multiplier unit by a unit of a group of two input feature maps each having half the reference bit length (Lee Figs. 5a-5b and paragraphs [0107-0109]; group of two group of two weights –
W
00
(
0,0
)
and
W
01
(
0,0
)
; group of two input feature maps –
F
1
(
0,0
)
and
F
0
(0,0); reference bit length – 16-bit; half the reference bit length – 8-bit).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino and Lee using Lee and configure the controller to group the weights and input feature maps in a group of two in response to the bit length of the weights and the input feature maps being half the reference bit length and input the group to the convolution engines in order to optimize the utilization and/or double the throughput of the convolution engines (Lee Fig. 5B and paragraph [0103, 0109]).
Therefore, the combination of Gibson as modified in view of Makino and Lee teaches wherein the controller is configured to: in response to a bit length of the weight being half the reference bit length, map the weight to an adder tree unit by a unit of a group of two weights, including the weight, that each have half the reference bit length; and in response to a bit length of the input feature map being half the reference bit length, map the input feature map to the adder tree unit by a unit of a group of two input feature maps, including the input feature map, that each have half the reference bit length.
Regarding claim 4, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 3 as stated above. Further, Gibson as modified in view of Makino and Lee teaches wherein the adder tree unit comprises:
a multiplier portion, comprising the multiplier configured to perform a multiply operation between the input feature map and the weight (Gibson Fig. 3 and col 6 lines 40-43; multiplier portion comprising the multiplier - plurality of elements of multiply logic 310);
the adder tree that is configured to add outputs of the multiplier portion (Gibson Fig. 3 and col 6 lines 40-43; adder tree - plurality of elements of addition logic 320; claim 14); and
an accumulator configured to accumulate and sum outputs of the adder tree (Gibson Fig. 2 and col 15 lines 34-35; accumulator - accumulators 245; claim 10).
Regarding claim 7, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above. Further, Gibson as modified in view of Makino teaches wherein the controller is configured to: in response to the bit length of the input feature map being double the reference bit length, map the input feature map and the weight to the operator such that the number of channels of the output feature map is halved, to provide the mixed precision operation (Lee Figs. 4a and 5B; 4a only generates a single output while 5B produces two outputs each in different channel; see also claim 1 analysis. The motivation to combine is the same as claim 1).
Regarding claim 8, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above.
Gibson as currently modified in view of Makino and Lee does not explicitly teach wherein the controller is configured to: in response to a bit length of the weight being double the reference bit length, group two adder tree units together into one group of adder tree units and map the weight to the one group of the adder tree units, where one of the two adder tree units is an adder tree unit and another of the two adder tree units is another adder tree unit of the operator.
However, on the same field of endeavor, Makino discloses the controller is configured to: in response to a bit length of the multiplier being double the reference bit length, group two multiplying units together into one group and mapping the multiplier to the one group of the two multiplying units by providing the higher-order bit portion A10 to a first multiplying unit and the lower-order bit portion A11 to a second multiplying unit of the group of two multiplying units (Makino Figs. 11-12 and paragraphs [0077-0078, 0139]; double the reference bit length - single-precision; multiplier – input A).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino and Lee and configure the controller to group two convolution engines and accumulators together into one group and map the weight to the group of the two convolution engines and accumulator by providing the higher-order bit portion of the weight to a first convolution engine and accumulator and the lower-order bit portion of the weight to a second two convolution engine and accumulator in order to provide a variable precision CNN hardware system that can efficiently perform convolution operation with high-precision weights using lower precision circuitry (Makino paragraph [0010, 0066, 0077-0078]).
Therefore, the combination of Gibson as modified in view of Makino and Lee teaches wherein the controller is configured to: in response to a bit length of the weight being double the reference bit length, group two adder tree units together into one group of adder tree units and map the weight to the one group of the adder tree units, where one of the two adder tree units is an adder tree unit and another of the two adder tree units is another adder tree unit of the operator.
Regarding claim 9, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 8 as stated above. Further, Gibson as modified in view of Makino and Lee teaches wherein the controller is configured to: map a first portion of the weight to the adder tree unit, and map a second portion of the weight to the other adder tree unit of the operator (Makino Fig. 12 and paragraph [0139]; see also claim 8 analysis). The motivation to combine is the same as claim 8.
Regarding claim 10, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above. Further, Gibson as modified in view of Makino and Lee does teaches wherein the controller is configured to: in response to the bit length of the input feature map being double the reference bit length, group two adder tree units together into one group of adder tree units and map the input feature map to the one group of the adder tree units where one of the two adder tree units is an adder tree unit and another of the two adder tree units is another adder tree unit of the operator (Makino Figs. 11-12 and paragraphs [0077-0078, 0139, 0148]; double the reference bit length - single-precision; multiplicand – input B). The motivation to combine is the same as claim 1.
Regarding claim 11, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 10 as stated above. Further, Gibson as modified in view of Makino and Lee wherein the controller is configured to: map a first portion of the input feature map to the one group of the adder tree units in a first cycle (Makino Fig. 12 and paragraphs [0138-0139]), and map a second portion of the input feature map to the one group of the adder tree units in a second cycle (Makino Fig. 12 and paragraph [0148]). The motivation to combine is the same as claim 1.
Regarding claim 12, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above. Further, Gibson as modified in view of Makino and Lee teaches wherein the operator further comprises another adder tree unit (Gibson Fig. 2; other adder tree unit – at least one other convolution engine and accumulator pair of the n pairs, for example, 240b and 245b).
Gibson as currently modified in view of Makino does not explicitly teach wherein an adder tree unit is configured to: perform a first operation between a first portion of the input feature map and a first portion of the weight in a first cycle, and perform a second operation between a second portion of the input feature map and the first portion of the weight in a second cycle, and wherein the other adder tree unit is configured to: perform a third operation between the first portion of the input feature map and a second portion of the weight in the first cycle, and perform a fourth operation between the second portion of the input feature map and the second portion of the weight in the second cycle.
However, on the same field of endeavor, Makino discloses a first multiplying unit configured to: perform an operation between a first portion of a multiplicand and a first portion of a multiplier in a first cycle, and perform an operation between a second portion of the multiplicand and the first portion of the multiplier in a second cycle (Makino Fig. 12 and paragraphs [0139,0148]; operation – multiplication; multiplicand – B1; first portion of the multiplicand – B10; multiplier – A1; first portion of the multiplier A10; second portion of the multiplicand – B11; first multiplying unit – 2a). Furthermore, Makino discloses a second multiplying unit configured to: perform an operation between the first portion of the multiplicand and a second portion of multiplier in the first cycle, and perform an operation between the second portion of the multiplicand and the second portion of the multiplier in the second cycle (Makino Fig. 12 and paragraphs [0139, 0148]; operation – multiplication; second portion of the multiplier – A11; second multiplying unit – 2b).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino and Lee and configure 240a and 245a to process a first portion of the input feature map and a first portion of the weight in a first cycle, and process a second portion of the input feature map and the first portion of the weight in a second cycle, and configure 240b and 245b to process the first portion of the input feature map and a second portion of the weight in the first cycle, and process the second portion of the input feature map and the second portion of the weight in the second cycle in order to provide a variable precision CNN hardware system that can efficiently perform convolution operation with high-precision input feature map and/or weight using lower precision circuitry (Makino paragraph [0010, 0066, 0077-0078]).
Therefore, the combination of Gibson as modified in view of Makino teaches wherein an adder tree unit is configured to: perform a first operation between a first portion of the input feature map and a first portion of the weight in a first cycle, and perform a second operation between a second portion of the input feature map and the first portion of the weight in a second cycle, and wherein the other adder tree unit is configured to: perform a third operation between the first portion of the input feature map and a second portion of the weight in the first cycle, and perform a fourth operation between the second portion of the input feature map and the second portion of the weight in the second cycle.
Regarding claim 13, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above. Further, Gibson as modified in view of Makino teaches wherein the operator further comprises one or more other adder tree units, including another adder tree unit, that each comprise a corresponding other multiplier and a corresponding other adder tree (Gibson Fig. 2; one or more other adder tree units – at least one of the other 240 and 245 pairs of the n pairs; col 6 lines 26-43; each convolution engine includes a corresponding multiplier and a corresponding adder tree to perform their respective convolution operation), and
(Gibson Fig. 2; the weight is passed to 240a-240n; Fig. 7b and col 17 lines 42-45 “the weight data is received at step 710 and passed to the convolution engines 240a to 240n”; weight parallelism size - n).
Gibson does not explicitly teach wherein the controller is configured to: group an adder tree unit and the one or more other adder tree units together into one group of adder tree units by a unit of a weight parallelism size and map a same weight to the one group of the adder tree units, to provide the data parallelism.
However, on the same field of endeavor, Makino discloses the controller is configured to group the multiplying units together into one group and mapping the same multiplicand portion to the one group of the adder tree units (Makino Fig. 16 and paragraph [0158]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino and Lee and generalize the teaching of Makino by grouping the convolution engines 240 and accumulators 240 into one group such that the same weight is mapped to the one group efficiently perform the convolution operation by making full use of the parallelism of a convolution operation in a neural network (Lee Fig. 9C and paragraph [0126 and 0133-0134]). Furthermore, combining multiple elements as one group is obvious to one of ordinary skill in the art (Gibson col 4 lines 8-16). Furthermore, by grouping the convolution engines 240 and accumulators 240 into one group, the CNN hardware may be reduced by using a single coefficient buffer that provides the same weight to the whole group (Gibson Fig. 1).
Therefore, the combination of Gibson as modified in view of Makino and Lee teaches wherein the controller is configured to: group an adder tree unit and the one or more other adder tree units together into one group of adder tree units by a unit of a weight parallelism size and map a same weight to the one group of the adder tree units, to provide the data parallelism.
Regarding claim 14, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above. Further, Gibson as modified in view of Makino and Lee teaches wherein the operator further comprises one or more other adder tree units, including another adder tree unit, that each comprise a corresponding other multiplier and a corresponding other adder tree (Gibson Fig. 2; one or more other adder tree units – at least one of the other 240 and 245 pairs of the n pairs; col 6 lines 26-43; each convolution engine includes a corresponding multiplier and a corresponding adder tree to perform their respective convolution operation), and
wherein the controller is configured to:
map the weight to the operator by matching the weight to the reference bit length such that a product of a weight parallelism size and a total number of the adder tree units including an adder tree unit and the one or more other adder tree units is constant, to provide the data parallelism (Makino Fig. 9 and paragraph [0076]; weight parallelism size – 4; the product of 4xn is a constant value 4n). The motivation to combine is the same as claim 1.
Regarding claim 31, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above. Further, Gibson as modified in view of Makino and Lee teaches wherein each of the plurality of adder tree units further comprises an accumulator configured to accumulate and sum outputs of the adder tree (Gibson Fig. 2 and col 15 lines 34-35; accumulator – at least one of the accumulators 245; claim 10).
Regarding claim 32, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 1 as stated above. Further, Gibson as modified in view of Makino and Lee teaches wherein the controller is configured to map the input feature map and the weight to the operator to provide both the mixed precision operation and the data parallelism (Makino Figs. 9, 12 and 16 and paragraphs [0076-0078, 0286]). The motivation to combine is the same as claim 1.
Regarding claims 15-17 and 20-271, they are directed to a method that is practiced by the device of claims 1-3 and 7-14 respectively. All steps performed by the method of claims 15-17 and 20-27 would be practiced by the device of claims 1-3 and 7-14 respectively. Claims 1-3 and 7-14 analysis applies equally to claims 15-17 and 20-27 respectively.
Regarding claim 18, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 17 as stated above. Further, Gibson as modified in view of Makino and Lee teaches wherein the performing the operation comprises:
respectively transforming the two input feature maps into first transformed data and second transformed data that each have the reference bit length (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length);
performing a first multiply operation between the first transformed data and a first weight comprised in the group of the two weights, using a first multiplier (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length);
performing a second multiply operation between the second transformed data and a second weight comprised in the group of the two weights, using a second multiplier, where one of the first multiplier and the second multiplier is the multiplier (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length); and
adding an output of the first multiplier, resulting from the performing of the first multiply operation, to an output of the second multiplier, resulting from the performing of the second multiply operation (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length).
Regarding claim 19, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 18 as stated above. Further, Gibson as modified in view of Makino and Lee teaches wherein the performing the operation further comprises: shifting the output of the first multiplier (Gibson Fig. 2 and col 6 lines 29-40; this is a contingent limitation that is not required to be performed if the bit length of the weight is equal to the reference bit length and if the bit length of the input feature map is equal to the reference bit length).
Claims 5-6 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gibson in view of Makino and Lee as applied to claim 4 above, and further in view of Makineni et al. (US 5880985 A), hereinafter Makineni.
Regarding claim 5, Gibson as modified in view of Makino and Lee teaches all the limitations of claim 4 as stated above. Further, Gibson as modified in view of Makino and Lee teaches
wherein the multiplier portion comprises:
a first multiplier configured to perform a first multiply operation between a first (Gibson Fig. 3 and col 6 lines 34-43; first multiplier – one of the multiply logic 310); and
a second multiplier configured to perform a second multiply operation between a second (Gibson Fig. 3 and col 6 lines 34-43; second multiplier – one of the multiply logic 310 different from the first multiplier).
Gibson does not explicitly teach a first transformed data; and second transformed data; wherein the first transformed data and the second transformed data are the two input feature maps that have been respectively transformed to each have the reference bit length.
However, on the same field of endeavor, Makineni discloses a first multiplexer configured to multiplex respective inputs comprised in a group of two inputs into a first transformed data and a second transformed data that each have bit length being twice the bit length of the original inputs; and a first multiplier configured to perform a multiply operation between the first transformed data and a first second operand comprised in a group of two second operands; and a second multiplier configured to perform a multiply operation between the second transformed data and a second second operand comprised in the group of the two second operands (Makineni Figs. 2-3, col 3 lines 46-57 and col 4 lines 12-30; first transformed data – A’; second transformed data - A’’).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino and Lee using Makineni and configure the multiplexers to multiplex respective input feature maps comprised in the group of the two input feature maps into first transformed data and second transformed data that each have the reference bit length in order to extend the bit length of the input feature maps such that the input feature maps matches the precision of the multipliers (Makineni Figs. 2-3 and col 4 lines 12-30; claim 5), then perform the multiplication operations using the first transformed data and second transformed data.
Therefore, the combination of Gibson as modified in view of Makino, Lee and Makineni teaches a first transformed data; and second transformed data; wherein the first transformed data and the second transformed data are the two input feature maps that have been respectively transformed to each have the reference bit length.
Regarding claim 6, Gibson as modified in view of Makino, Lee and Makineni teaches all the limitations of claim 5 as stated above. Further, Gibson as modified in view of Makino, Lee and Makineni teaches wherein the adder tree unit further comprises: an adder configured to add an output of the first multiplier to an output of the second multiplier resulting from the performed second multiply operation (Gibson Fig. 3; adder - addition logic 320).
Gibson does not explicitly teach a shifter configured to shift an output of the first multiplier, resulting from the performed first multiply operation; and an adder configured to add an output of the shifter to an output of the second multiplier.
However, on the same field of endeavor, Makino discloses a shifter configured to shift an output of a multiplier; and an adder configured to add an output of the shifter (Makino Fig. 12 and paragraphs [0141, 0143]; shifter - shifter).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gibson in view of Makino, Lee and Makineni and generalize the teaching of Makino by including a shifter to shift an output of the first multiplier and configure the adder to add an output of the shifter to the output of the second multiplier in order to properly align the outputs of the multipliers before being added so that the convolution operation can be calculated correctly. As discussed in col 5 lines 19-23 and col 5 lines 38-42 of Makineni, the outputs of multipliers 51 and 53 are located in different portions of the 24-bit result, therefore in order to correctly add the outputs of the multipliers when performing the convolution operation, the result needs to be aligned correctly before being added to each other.
Therefore, the combination of Gibson as modified in view of Makino, Lee and Makineni teaches wherein the adder tree unit further comprises: a shifter configured to shift an output of the first multiplier, resulting from the performed first multiply operation; and an adder configured to add an output of the shifter to an output of the second multiplier, resulting from the performed second multiply operation.
Regarding claims 18-19, they are directed to a method that is practiced by the device of claim 6. All steps performed by the method of claims 18-19 would be practiced by the device of claim 6. Claim 6 analysis applies equally to claims 18-19.
Allowable Subject Matter
Claim 33 would be allowable if rewritten to overcome the 35 U.S.C. 112(a) rejection discussed above.
None of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims, providing a non-split identical weight, from one weight buffer, to the adder tree unit and another adder tree unit, wherein the adder tree unit and the another adder tree unit each independently generate a respective output value for a respective different channel of an output feature map using the non-split identical weight as recited in claim 33.
Response to Arguments
Applicant’s arguments, see remarks page 11-24, filed 07/07/2026, with respect to the rejection(s) of claim(s) 1-27 and 31-32 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Applicant argues the following:
1.) Makino fails to teach summing respective outputs for the reduced number of channels. Further, Lee does not describe reducing "a number of channels of an output feature map". Instead, Lee finds a number of channels in an output feature map based on a number of kernels applied during convolution and on the actual architecture of the neural network.
Response: Examiner respectfully disagrees. Makino discloses “sum respective outputs of the two or more adder tree units to generate a single output value to provide the mixed precision operation” in at least Fig. 12 and corresponding paragraphs [0137-0153]. Furthermore, the features of “a number of channels of an output feature map is reduced proportionally to the bit length of the input feature map” is disclosed in Lee Figs. 4a and 5B.
2.) Fig. 4A of Lee merely describes multiplier utilization using 16-bit operands while Fig. 5B merely describes using four 8-bit operands for parallel processing to provide two independent outputs. Furthermore, Lee discloses that Fig. 5B is inefficient. Therefore, Lee fails to teach “a number of channels of an output feature map is reduced/halved when a bit length of an input feature map and a weight is doubled”.
Response: Examiner respectfully disagrees. Applicant admits that Fig. 5B of Lee discloses using four 8-bit operands for parallel processing to provide two independent outputs in two different output channels. Further, Fig. 4A of Lee discloses using 16-bit inputs (i.e., a bit length being greater/double than the reference bit length) and providing a single output (i.e., a number of channels is reduced proportionally to the bit length). Therefore, Lee teaches “a number of channels of an output feature map is reduced/halved when a bit length of an input feature map and a weight is doubled”.
3.) Modifying Gibson using Lee would destroy Gibson’s operation and one of ordinary skill in the art would not modify Gibson simply to use Lee's multiplier array as Gibson's convolution engines are configured to handle the subsets of data.
Response: Examiner respectfully disagrees. Applicant appears to be confusing the splitting of data in Gibson into different subsets as shown in Fig. 8A. in which the data are divided into groups in the channel direction compared to being divided based on precision. Therefore, one of ordinary skill in the art would have a motivation to combine Gibson and Lee to perform the convolution operation of higher precision input feature maps using lower-precision circuitry.
4.) Makino is not in the same field of endeavor because the claimed invention is related to multiply-accumulate operation while Makino is related to performing multiplication operation.
Response: Examiner respectfully disagrees. Makino is on the same field of endeavor because multiplication operation is a part of a multiply-accumulate operation and therefore are related. Furthermore, both Makino and the claimed invention are related to multi-precision operations.
5.) Lee Figs. 4A and 5B do not compare the same hardware operating at different precision levels. Instead, Fig. 4A processes one pair of 16-bit inputs using one multiplier. Fig. 5B processes two pairs of 8-bit inputs using the same multiplier. The output count changes from one to two not because the bit length changed, but because the number of input pairs doubled. These are two different processing scenarios, not the same scenario at different bit lengths.
Response: Examiner respectfully disagrees. Applicant is arguing unclaimed features. The claim does not recite a same scenario of processing different bit lengths resulting in different number of channels of the output feature map. In contrast, the claim itself requires a different scenario (i.e., in response to a bit length of the input feature map being greater than the reference bit length).
6.) Lee does not show the same hardware producing fewer output channels in response to an increase in bit length while processing the same number of input pairs.
Response: Examiner respectfully disagrees. Applicant is arguing unclaimed features. The claim does not require producing fewer output channels while processing the same number of input pairs. The claim only requires producing fewer output channels in response to an increase in bit length.
7.) Lee itself characterizes the Fig. 5B scenario as inefficient. Therefore, it is inappropriate to cite Lee as teaching the proportional channel reduction recited in the amended claim.
Response: Examiner respectfully disagrees. See MPEP 2143.01 subsection I: “The disclosure of desirable alternatives does not necessarily negate a suggestion for modifying the prior art to arrive at the claimed invention.”
8.) Lee does not describe reducing "map the input feature map and the weight to the grouped adder trees units such that, for a same number of the adder tree units performing the operation, a number of channels of an output feature map is reduced proportionally to the bit length of the input feature map," as recited for example, in claim 15.
Response: Examiner respectfully disagrees. Examiner would like to point out that claim 15 is a method claim and Applicant is arguing contingent limitations that are not required by the claim if the bit length of the input feature map is equal to the reference bit length. See MPEP 3111.04 for more information.
Applicant’s arguments, see remarks page 24-25, filed 07/07/2026, with respect to the rejection(s) of claim(s) 33 under 35 U.S.C. 103 have been fully considered and they are not persuasive. The 35 U.S.C. 103 of claim 33 has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2182 (571)272-5767
1 Examiner notes that although the method claims are rejected using the same analysis and the device claims, the method claims includes contingent limitations that are not required by the claims if the precedent condition(s) are not met.
Prosecution Insights