DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 08, 2025 has been entered.
Response to Amendment
This action is responsive to the amendment and remarks received May 08, 2025. Claims 1, 11, and 15 are amended. Claim 26 is newly added. Claims 5-7, and 12-14 are canceled. Claims 1-4, 8-11, and 15-26 are currently pending in the application.
Claim Rejections - 35 USC § 102
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11, 21 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimura et al. (US Patent Application Publication 2002/0039464, hereinafter Yoshimura).
Regarding claims 11, 14, and 21-22; Yoshimura discloses a hybrid integrated circuit (IC) assembly (see Fig. 140, 143) comprising:
a first plurality of interconnected electronic logic devices (MCM - left side, Fig. 143; Par. 142) in a first region of a first layer (top layer, see Fig. 143) of the hybrid IC assembly (Fig. 143);
a second plurality of interconnected electronic logic devices (MCM -— right side, Fig. 143; Par. 142) in a second region of the first laver (top layer) of the hybrid IC assembly (Fig. 143); and
an optical waveguide (multiple optical waveguides depicted, see Fig. 143) coupled between the first plurality of interconnected electronic logic devices (MCM - left side) and the second plurality of interconnected electronic logic devices (MCM – right side) (multiple waveguides depicted coupling both pluralities of interconnected logic devices, see Fig. 148);
wherein the optical waveguide is in a second layer (middle layer, see Fig. 143) of the hybrid IC assembly (optical waveguide is depicted in the middle layer of the IC assembly);
further comprising a bonding layer between the first layer (top layer) and the second layer (middle layer) (bonding layer including bonding pads depicted between the first and second layers), see Fig. 143), wherein the optical waveguide extends through the bonding layer (optical waveguide depicted extending through the bonding layer, see Fig. 140);
wherein the optical waveguide is configured to transmit data signals from the first plurality of interconnected electronic logic devices to the second plurality of interconnected electronic logic devices (Par. 312);
wherein the first layer (top layer) comprising the first plurality of interconnected electronic logic devices (MCM -— left side) and the second plurality of interconnected electronic logic devices (MCM — right side) is stacked over the second layer (middle layer) (First layer depicted stacked over the second layer, see Fig. 143).
Claim(s) 18-19, 23 and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 2021/0166991 A1 hereinafter Liu).
Regarding claims 18, 19 and 23; Liu discloses a hybrid integrated circuit (IC) assembly (see annotated Fig. 6, included in the Final Rejection dated March 13, 2025) comprising:
a first hybrid layer (1St HL, see annotated Fig. 6) comprising a first electronic circuit element (1St HL can be capable of communicating electronic signals, see Par. 35) and a first waveguide (photonic interconnect, see annotated Fig. 6; Par. 35), the first hybrid layer (18 HL) having a front face (1§' HL is depicted having a front face facing the back face of the 2"? HL, see annotated Fig. 6);
a second hybrid layer (2.7 HL see annotated Fig. 6) comprising a second electronic circuit element (Par. 35) and a second waveguide (TWI, see annotated Fig. 6; Par. 35), the second waveguide (TWI) formed of a substantially monocrystalline material (Par. 36), the-second hybrid layer (2" HL) having a back face (2"¢ HL is depicted having a back face facing the front face of the 1st HL, see annotated Fig. 6); and
a bonding layer (Bonding Layer, see annotated Fig. 6) between the front face of the first hybrid layer and the back face of the second hybrid layer;
the bonding layer comprising a bonding material having a lower crystallinity than the second waveguide (Par. 36);
wherein the first electronic circuit element and the first waveguide are near the front face of the first hybrid layer, and the second electronic circuit element and the second waveguide are near a front face of the second hybrid layer (the depicted layers are thin and all elements of each layer are near the faces of each layer, see annotated Fig. 6);
wherein the first electronic circuit element is a first active element, and the second electronic circuit element is a second active element (the elements are both interpreted as active elements).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2021/0166991 A1 hereinafter Liu) in view of lida et al. (US 10,656,442 B2 hereinafter lida).
Regarding claims 1-4 and 8-10; Liu discloses a hybrid integrated circuit (IC) assembly (see annotated Fig. 5, included in the Final Rejection dated March 13, 2025) comprising:
a first IC structure (photonic die n, see annotated Fig. 5) comprising a waveguide (1St Waveguide, see annotated Fig. 5) formed of a substantially monocrystalline material (Par. 36), the first IC structure having a front face (Front Face, see annotated Fig. 5);
a second IC structure (electronic die n, see annotated Fig. 5) comprising an electronic circuit (Par. 35) comprising a conductive structure (conductive structures are an inherent feature of an electronic circuit),
wherein the second IC structure has a back face (Back Face, see annotated Fig. 5); and
a bonding layer (Bonding Layer, see annotated Fig. 5) between the front face (Front Face) of the first IC structure (photonic die n) and the back face (Back Face) of the second IC structure (electronic die n), the bonding layer (Bonding Layer) comprising a bonding material having a lower crystallinity than the waveguide (Par. 36);
wherein the first IC structure (photonic die n) further comprises at least one electronic circuit element (TSV, see annotated Fig. 5; Par. 42);
wherein the second IC structure (electronic die n) further comprises a second waveguide (2" Waveguide, see annotated Fig. 5);
the second waveguide (2nd Waveguide) couples a first portion (photonic die n) of the hybrid IC assembly to a second portion (electronic die n) of the hybrid IC assembly;
wherein the first portion (photonic die n) of the hybrid IC assembly is the first IC structure (photonic die n), the second portion (electronic die n) of the hybrid IC assembly is the second IC structure (electronic die n), and the second waveguide (2"¢ Waveguide) comprises an optical via that couples the first IC structure (photonic die n) and the second IC structure (electronic die n) through the bonding layer (Par. 35);
wherein the first portion (photonic die n) of the hybrid IC assembly is a first electronics portion (photonic die n comprises electronic elements such as the electrode connected TSV, see annotated Fig. 5; Par. 42) of the first IC structure (photonic die n), and the second portion (electronics die n) of the hybrid IC assembly is a second electronics portion of the first IC structure (electronic die n; electronic die contains electronic elements and is an electronics portion, see Par. 35);
the conductive structure is in contact with the bonding layer (see figure 5, all the elements of the device are thermally contacting every other element in the device).
Liu fails to disclose that the electronic circuit is along the back face of the second IC structure, wherein the conductive structure in the second IC structure is directly over the waveguide in the first IC structure, or that the conductive structure is a heating element to modulate a wavelength of light in the waveguide.
lida teaches a hybrid IC assembly (Fig. 3) wherein an electronic circuit with conductive structure (MH1, Fig. 3) is along a back face of a second IC structure (IL2, Fig. 3; the electronic elements are depicted along the back surface of IL2, see Fig. 3), wherein the conductive structure (MH1) is directly over a waveguide (CR1, Fig. 3) in a first IC structure (IL1), and that the conductive (MH1) structure is a heating element to modulate a wavelength in the waveguide (CR1) (Col. 3, Ln. 37-42). Using heat is a well- known method for modulating optical signals by harnessing the thermal dependence of a material's refractive index to control light modulation. Therefore, it would have been obvious, before the effective filing date of the claimed invention, to have incorporated the thermal optical modulation structure taught by lida within the hybrid IC assembly disclose by Liu in order to modulate optical signals in waveguides within photonic elements by changing the refractive index by thermal manipulation of the waveguide materials.
Liu also does not specifically disclose that the first IC structure in the embodiment depicted in Fig. 5 comprises a second waveguide. Liu does however teach connecting layers within an IC stack with vertical waveguides and includes embodiments with multiple photonic interconnects and through wafer vias which could be optical waveguides (see Fig. 6 and 7 and Par. 34-35). Furthermore, these methods are well established in the art for connecting optical components in stacked hybrid integrated circuits. Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have utilized multiple waveguides in a photonic layer, including waveguides connecting multiple layers in a hybrid IC stack as taught by Liu, within the hybrid IC assembly disclosed by Liu in figure 5 in order to send multiple optical signals between layers in the IC.
Upon making such a combination, the combination device discloses the bonding layer is between the waveguide and the conductive structure.
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimura et al. (US 2002/0039464 A1 hereinafter Yoshimura) in view of Liu et al. (US 2021/0166991 A1 hereinafter Liu).
Regarding claims 15-17; Yoshimura discloses the hybrid IC assembly according to claim 14;
further comprising a first conversion circuitry (Photodetector, Fig. 143) that couples the first plurality of interconnected electronic logic devices (MCM left-side) to the optical waveguide and a second conversion circuitry (VCSEL, Fig. 143) that couples the second plurality of interconnected electronic logic devices (MCM -— right side) to the optical waveguide (coupling to waveguide layer depicted, see Fig. 143);
further comprising a second optical waveguide coupled between the first plurality of interconnected logic devices (MCM - left side) and an optical port (multiple waveguides are depicted coupling the MCM and an optical port, see Fig. 143).
Yoshimura fails to disclose that the bonding layer comprises a bonding material having a lower crystallinity than the optical waveguide.
Liu teaches a hybrid IC assembly (see annotated Fig. 5) having a bonding layer (Bonding Layer, see annotated Fig. 5) wherein the bonding layer comprises a bonding material having a lower crystallinity than the optical waveguide (Par. 36). Waveguides comprised of crystalline materials such as waveguides taught by Liu (see Par. 36) are well known in the art, and both Liu and Yoshimura teach surface low-crystallinity bonding methods such as flip chip bonding, solder bonding, and adhesive bonding (see Liu, Par. 8 and Yoshimura, Par. 186) that are well known in the art. Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have utilized established low-crystallinity layer bonding techniques such as those taught by Lue and Yoshimura, and crystalline waveguides such as those taught by Liu, within the hybrid IC assembly disclosed by Yoshimura in order to meet manufacturing or performance constraints.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2021/0166991 A12 hereinafter Liu) in view of Fathpour et al. (US 10,718,904 B2 hereinafter Fathpour).
Regarding claim 20; Liu discloses the hybrid IC assembly of claim 18, the first hybrid layer (1S HL, see annotated Fig. 6) comprising an optical region (photonic die m, see annotated Fig. 6), the optical region comprising a waveguide layer (photonic die m comprises multiple waveguides, see annotated Fig. 6).
Liu fails to teach an isolation layer.
Fathpour teaches the optical layer (Fig. 1E) comprising an isolation layer (116, Fig. 1E). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to incorporated the isolation layer as taught by Fathpour within the hybrid IC assembly with waveguide layer disclosed by Liu in order to isolate distinct optical signals within the optical layer to limit interference.
Claim(s) 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2021/0166991 A1 hereinafter Liu) in view of Yoshimura et al. (US 2002/0039464 A1 hereinafter Yoshimura).
Regarding claims 24 and 25; Liu discloses the hybrid IC assembly of claim 18.
Liu fails to disclose that the hybrid IC assembly further comprises an optical via coupling the first waveguide and the second waveguide, the optical via extending through the bonding layer or conversion circuitry between the first waveguide and the first electronic circuit element.
Yoshimura teaches a hybrid IC assembly (Fig. 143) comprising an optical via coupling a first waveguide and a second waveguide (an optical via is depicted coupling multiple depicted waveguides, see Fig. 143 and Par. 317), the optical via extending through the bonding layer (the optical via is depicted extending through a bonding layer see Fig. 143) as well as conversion circuitry (photodetector, Fig. 143) between the first waveguide and the first electronic circuit element (MCM, Fig. 143; the photodetector is depicted between a waveguide and an MCM, see Fig. 143). Optical vias coupling waveguides are well known in the art as methods to couple light between different paths, optical vias extending through bonding layers are taught by both Liu and Yoshimura and are well known in the art for coupling light between layers in IC assemblies, utilizing conversion circuitry such as the photodetector taught by Yoshimura is well known in the art for converting optical signals to electrical signals or versa. Therefore, would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the light guiding and signal conversion techniques as taught by Yoshimura within the hybrid IC assembly disclosed by Liu in order to couple light signals between layers in the device as well as between optical and electronic components within the device.
Response to Arguments
Applicant's arguments filed May 08, 2025 have been fully considered but they are not persuasive. The examiner has reviewed Applicant’s arguments but believes the cited references meet the limitations.
Applicant first argues, see the bottom half of page 6, that the combination of Liu and Iida fails to disclose the limitations of claim because Iida does not disclose the newly added limitations and because the process for forming the device of Iida is entirely different from that of Liu and one would not mix and match to arrive at the claimed subject matter. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant’s assertion that one would not mix and match elements to arrive at the claimed subject matter, the examiner notes that this is simply a conclusion given by applicant and applicant does not offer any explanation of why such a combination would be obvious. As such, this argument is not persuasive.
Next, see the top of page 7, applicant argues that Yoshimura fails to anticipate claim 11, which has incorporated the subject matter of previous claim 14, and argues that Yoshimura does not anticipate claim 14 because fig. 143 does not depict a bonding layer at all.
The examiner respectfully disagrees. Looking at Yoshimura the various layers and hybrid IC assemblies are connected or bonded to one another. The claim does not require specific materials or physical characteristics for the bonding layer. The prior art reference does not have to use Applicant’s claim language as long as the skilled artisan would understand that the elements disclosed in the prior art meets the claim terms. Further one skilled in the art would understand the features from both figs. 140 and 143 which meet the claimed first and second layer, hybrid IC assemblies, bonding layer and waveguides.
Lastly, see pages 7 and 8, applicant argues that nothing in Liu indicates that the layers identified as the first hybrid layer are capable of communicating electronic signals.
The examiner respectfully disagrees. Paragraph [ 0035] of Liu clearly explains that fabricating the PICs includes forming “metallized contacts” for electrical communication. Applicant further argues that the disclosed TWIls do not meet the claimed waveguides because Liu teaches that the TWI can be photonic or electronic and there is no explanation of whether the TWI shown in fig. 6 is photonic or electronic. As Applicant acknowledges, Liu teaches alternate arrangements for the TWIs and when one of the disclosed alternate arrangements meets the claim limitation, the claim is anticipated. The reference does not have to limit the disclosure to only one alternative for the claim to be anticipated. For these reason Applicant’s arguments are not found persuasive.
Conclusion
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/John Bedtelyon/Primary Examiner, Art Unit 2874