Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed on 04/28/2026
Claims 1-3, 5-8, 10-13, 15-18, 20 and 22-25 are pending in the case. Claims 1, 11 and 24 are independent claims. Claims 4, 9, 14, 19, 21 have been canceled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-8, 11, 15-18, 22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US Pub No.: 20200371835 A1), hereinafter referred to as Chuang, in view of Coon et al. (US Patent No. 8,108,625 B1), hereinafter referred to as Coon.
With respect to claim 1, Coon disclose:
At least one same stored data (In Col. 11, lines 47–60, Coon teaches multithreaded processor systems and, in particular to a memory that can be shared by concurrent threads, where multiple threads can access the shared memory in parallel.)
Verifying whether competition occurs between the first data traversal path and the second data traversal path, where a result of the verifying is that competition occurs based on a first operand data of the first data traversal path and a second operand data of the second data traversal path being the same stored data, and in response to the first processor and the second processor being determined to be approaching, according to the first and second data traversal paths, respective executions of the first and second operand data at a same point in time (In Fig. 7 and Col.16-17, lines 54–16, Coon teaches whether conflict occurs between concurrent processing operations by employing address conflict logic 310. Address conflict logic receives pending memory requests from multiple processing engines and a conflict detection unit compares the pending addresses to detect conflict, generating conflict signals when multiple request contend for the same memory resource.)
Executing a first neural network operation by the first processor using the first operand data in parallel with a second neural network operation by the second processor using the second operand data in response to the result of the verifying being that competition does not occur (In Col. 16-17, lines 66-17, Coon teaches executing operations in response to a determination that no conflict exists. Specifically, a go signal is asserted when there are no conflicts, thereby permitting the corresponding request to proceed. However, (In paragraph [0171], Chuang teaches the parallel execution of neural-network operations by first and second processors.))
Respectively executing the first neural network operation by the first processor and the second neural network operation by the second processor in non-parallel order in response to the result of the verifying being that competition does occur, where the non-parallel order is dependent on a determined priority between the first data traversal path and the second data traversal path (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle. However, (In paragraph [0171], Chuang teaches the parallel execution of neural-network operations by first and second processors.))
With respect to claim 1, Coon does not explicitly disclose:
A processor-implemented method, the method comprising: implementing a neural network by executing parallel neural network operations by first and second processors respectively based on a plurality of first data and a plurality of second data, where the plurality of first data is assigned to be utilized by the first processor in order according to a first data traversal path, the plurality of second data is assigned to be utilized by the second processor in order according to a second data traversal path, and the first data traversal path and the second data traversal path overlap with respect to
Wherein each of the plurality of first data and the plurality of second data are respectively parameters of the neural network or input data of the neural network
Wherein the input data of the neural network corresponds to either an input to the neural network or activations of the neural network
However, it is known by Chuang to disclose:
A processor-implemented method, the method comprising: implementing a neural network by executing parallel neural network operations by first and second processors respectively based on a plurality of first data and a plurality of second data, where the plurality of first data is assigned to be utilized by the first processor in order according to a first data traversal path, the plurality of second data is assigned to be utilized by the second processor in order according to a second data traversal path, and the first data traversal path and the second data traversal path overlap with respect to (In Figs. 7A-7B and paragraph [0098], Chuang teaches that the artificial neural network can be provided to multiple matrix processors such that data samples can be processed in parallel. In Figs. 17A-17B and paragraph [0171], Chuang teaches an artificial neural network using two separate processors. The reference assigns the first two layers of the ANN to a first matrix processor (server 0) and the remaining two layers to a second matrix processor (server 1), thereby distributing execution of the neural network across first and second processors. Each processor performs neural -network computations on the data associated with its assigned layers.)
Wherein each of the plurality of first data and the plurality of second data are respectively parameters of the neural network or input data of the neural network (In paragraph [0051], Chuang teaches that the data processed by the artificial neural network includes input data vectors supplied to the neural network and weighted matrices used to transform the input data through successive layers. The weighted matrices constitute neural-network parameters, while the input vectors comprise neural-network input data.)
Wherein the input data of the neural network corresponds to either an input to the neural network or activations of the neural network (In paragraph [0054], Chuang teaches to process input data through a first weighted matrix to generate intermediate output data. The neural-network input data includes both original input data supplied to the artificial neural network and intermediate output data generated by earlier neural-network layers and provided as input to subsequent layers.)
Coon in view of Chuang are analogous pieces of art because both references concern ensuring the correctness or reliability of data before it used in subsequent processing. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Coon, with parallel processing engines executing the threads generate a group of parallel memory access requests as taught by Coon, with various parallel computer systems such as multicore processors and massive parallel processing (MPP) computer systems as taught by Chuang. The motivation for doing so would have been to determine an error and that error is used to adjust as set of weights within the artificial neural networks to improve performance (See [0050] of Chuang.)
Regarding claim 5, Coon in view of Chuang disclose elements of claim 1. In addition, Coon disclose:
The method of the neural network further comprises setting respective priorities for the first data traversal path and the second data traversal path, and wherein the determined priority between the first data traversal path and the second data traversal path is determine d dependent on the set respective priorities (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
Regarding claim 6, Coon in view of Chuang disclose elements of claim 5. In addition, Coon disclose:
The method of claim 5, wherein the setting of the respective priorities comprises: setting different first priorities for each of the plurality of first data on the first data traversal path; and setting different second priorities for each of the plurality of second data on the second data traversal path (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
Regarding claim 7, Coon in view of Chuang disclose elements of claim 5. In addition, Coon disclose:
The method of wherein the implementing of the neural network further comprises performing the determining of the priority by comparing a first priority, among the set respective priorities, set for the first data traversal path with a second priority, among the set respective priorities, set for the second data traversal path to determine a higher-priority traversal path among the first data traversal path and the second data traversal path, and wherein the respective executing of the first neural network operation by the first processor and the second neural network operation by the second processor in the non-parallel order comprises: in response to the determined higher-priority traversal path being the first data traversal path, executing the first neural network operation by the first processor before executing the second neural network operation by the second processor (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
In response to the determined higher-priority traversal path being the second data traversal path, executing the second neural network operation by the second processor before executing the first neural network operation by the first processor (In Col.15, lines 17-35, Coon disclose In the event that two (or more) processing engines 202 request access to target addresses in the same bank 302, the processing engine with the lower identifier i is given priority over the processing engine with the higher identifier i.)
Regarding claim 8, Coon in view of Chuang disclose elements of claim 6. In addition, Coon disclose:
The method of The method of wherein the implementing of the neural network further comprises performing the determining of the priority by comparing a corresponding first priority, among the set respective priorities, set for the first operand data with a second priority, among the set respective priorities, set for the second operand data, and wherein the respective executing of the first neural network operation by the first processor and the second neural network operation by the second processor in the non-parallel order comprises performing one, dependent on a result of the performing of the determining of the priority, of: executing the first neural network operation by the first processor before executing the second neural network operation by the second processor and executing, in parallel with the execution of the first neural network operation, another second operand data on the second data traversal path subsequent to the second operand data by the second processor (In Fig. 6 and Col. 15, lines 17-35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
Executing the second neural network operation by the second processor before executing the first neural network operation by the first processor and executing, in parallel with the execution of the second neural network operation, another first operand data on the first data traversal path subsequent to the first operand data by the first processor (In Col.15, lines 17-35, Coon discloses that In the event that two (or more) processing engines 202 request access to target addresses in the same bank 302, the processing engine with the lower identifier I is given priority over the processing engine with the higher identifier i.)
With respect to claim 11, Coon disclose:
At least one same stored data (In Col. 11, lines 47–60, Coon teaches multithreaded processor systems and, in particular to a memory that can be shared by concurrent threads, where multiple threads can access the shared memory in parallel.)
Verifying whether competition occurs between the first data traversal path and the second data traversal path, where a result of the verifying is that competition occurs based on a first operand data of the first data traversal path and a second operand data of the second data traversal path being the same stored data, and in response to the first processor and the second processor being determined to be approaching, according to the first and second data traversal paths, respective executions of the first and second operand data at a same point in time (In Fig. 7 and Col.16-17, lines 54–16, Coon teaches whether conflict occurs between concurrent processing operations by employing address conflict logic 310. Address conflict logic receives pending memory requests from multiple processing engines and a conflict detection unit compares the pending addresses to detect conflict, generating conflict signals when multiple request contend for the same memory resource.)
Executing a first neural network operation by the first processor using the first operand data in parallel with a second neural network operation by the second processor using the second operand data in response to the result of the verifying being that competition does not occur (In Col. 16-17, lines 66-17, Coon teaches executing operations in response to a determination that no conflict exists. Specifically, a go signal is asserted when there are no conflicts, thereby permitting the corresponding request to proceed. However, (In paragraph [0171], Chuang teaches the parallel execution of neural-network operations by first and second processors.))
Respectively executing the first neural network operation by the first processor and the second neural network operation by the second processor in non-parallel order in response to the result of the verifying being that competition does occur, where the non-parallel order is dependent on a determined priority between the first data traversal path and the second data traversal path (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle. However, (In paragraph [0171], Chuang teaches the parallel execution of neural-network operations by first and second processors.))
With respect to claim 11, Coon does not explicitly disclose:
A computing apparatus, the apparatus comprising: one or more processors configured to: implement a neural network through a control of an execution of parallel neural network operations by first and second processors respectively based on a plurality of first data and a plurality of second data, where the plurality of first data is assigned to be utilized by the first processor in order according to a first data traversal path, the plurality of second data is assigned to be utilized by the second processor in order according to a second data traversal path, and the first data traversal path and the second data traversal path overlap with respect to
Wherein each of the plurality of first data and the plurality of second data are respectively parameters of the neural network or input data of the neural network
Wherein the input data of the neural network corresponds to either an input to the neural network or activations of the neural network
However, it is known by Chuang to disclose:
A computing apparatus, the apparatus comprising: one or more processors configured to: implement a neural network through a control of an execution of parallel neural network operations by first and second processors respectively based on a plurality of first data and a plurality of second data, where the plurality of first data is assigned to be utilized by the first processor in order according to a first data traversal path, the plurality of second data is assigned to be utilized by the second processor in order according to a second data traversal path, and the first data traversal path and the second data traversal path overlap with respect to (In Figs. 7A-7B and paragraph [0098], Chuang teaches that the artificial neural network can be provided to multiple matrix processors such that data samples can be processed in parallel. In Figs. 17A-17B and paragraph [0171], Chuang teaches an artificial neural network using two separate processors. The reference assigns the first two layers of the ANN to a first matrix processor (server 0) and the remaining two layers to a second matrix processor (server 1), thereby distributing execution of the neural network across first and second processors. Each processor performs neural -network computations on the data associated with its assigned layers.)
Wherein each of the plurality of first data and the plurality of second data are respectively parameters of the neural network or input data of the neural network (In paragraph [0051], Chuang teaches that the data processed by the artificial neural network includes input data vectors supplied to the neural network and weighted matrices used to transform the input data through successive layers. The weighted matrices constitute neural-network parameters, while the input vectors comprise neural-network input data.)
Wherein the input data of the neural network corresponds to either an input to the neural network or activations of the neural network (In paragraph [0054], Chuang teaches to process input data through a first weighted matrix to generate intermediate output data. The neural-network input data includes both original input data supplied to the artificial neural network and intermediate output data generated by earlier neural-network layers and provided as input to subsequent layers.)
Coon in view of Chuang are analogous pieces of art because both references concern ensuring the correctness or reliability of data before it used in subsequent processing. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Coon, with parallel processing engines executing the threads generate a group of parallel memory access requests as taught by Coon, with various parallel computer systems such as multicore processors and massive parallel processing (MPP) computer systems as taught by Chuang. The motivation for doing so would have been to determine an error and that error is used to adjust as set of weights within the artificial neural networks to improve performance (See [0050] of Chuang.)
Regarding claim 15, Coon in view of Chuang disclose elements of claim 11. In addition, Coon disclose:
The apparatus of The apparatus of wherein the implementation of the neural network further comprises a setting of respective priorities for the first data traversal path and the second data traversal path, and wherein the determined priority between the first data traversal path and the second data traversal path is determined dependent on the set respective priorities (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
Regarding claim 16, Coon in view of Chuang disclose elements of claim 15. In addition, Coon disclose:
The apparatus of claim 15, wherein the setting of the respective priorities comprises: a setting of different first priorities for each of the plurality of first data on the first data traversal path; and a setting of different second priorities for each of the plurality of second data on the second data traversal path (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
Regarding claim 17, Coon in view of Chuang disclose elements of claim 15. In addition, Coon disclose:
The apparatus of The apparatus of wherein the implementation of the neural network further comprises a performing of the determining of the priority by a comparing of a first priority, among the set respective priorities, set for the first data traversal path with a second priority, among the set respective priorities, set for the second data traversal path to determine a higher-priority traversal path among the first data traversal path and the second data traversal path, and wherein the control of the respective execution of the first neural network operation by the first processor and the second neural network operation by the second processor in the non- parallel order comprises: in response to the determined higher-priority traversal path being the first data traversal path, a control of the execution of the first neural network operation by the first processor before the execution of the second neural network operation by the second processor (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
In response to the determined higher-priority traversal path being the second data traversal path, a control of the execution of the second neural network operation by the second processor before the execution of the first neural network operation by the first processor (In Col.15, lines 17-35, Coon disclose In the event that two (or more) processing engines 202 request access to target addresses in the same bank 302, the processing engine with the lower identifier i is given priority over the processing engine with the higher identifier i.)
Regarding claim 18, Coon in view of Chuang disclose elements of claim 17. In addition, Coon disclose:
The apparatus of The apparatus of wherein the implementation of the neural network further comprises a performing of the determining of the priority by a comparing of a corresponding first priority, among the set respective priorities, set for the first operand data with a second priority, among the set respective priorities, set for the second operand data, and wherein the control of the respective execution of the first neural network operation by the first processor and the second neural network operation by the second processor in the non- parallel order comprises a control of a performing of one, dependent on a result of the performing of the determining of the priority, of: the execution of the first neural network operation by the first processor before the execution of the second neural network operation by the second processor and an execution, in parallel with the execution of the first neural network operation, of another second operand data on the second data traversal path subsequent to the second operand data by the second processor (In Fig. 6 and Col. 15, lines 17-35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
Execution of the second neural network operation by the second processor before the execution of the first neural network operation by the first processor and an execution, in parallel with the execution of the second neural network operation, of another first operand data on the first data traversal path subsequent to the first operand data by the first processor (In Col.15, lines 17-35, Coon discloses that In the event that two (or more) processing engines 202 request access to target addresses in the same bank 302, the processing engine with the lower identifier I is given priority over the processing engine with the higher identifier i.)
Regarding claim 22, Coon in view of Chuang disclose elements of claim 7. In addition, Coon disclose:
The method of claim 7, wherein the respective executing of the first neural network operation by the first processor and the second neural network operation by the second processor in the non-parallel order further comprises: in response to the determined higher-priority traversal path being the first data traversal path, executing the first neural network operation by the first processor in parallel with an executing by the second processor of another second operand data on the second data traversal path subsequent to the second operand data (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
In response to the determined higher-priority traversal path being the second data traversal path, executing the second neural network operation in parallel with an executing by the first processor of another first operand data on the first data traversal path subsequent to the first operand data (In Col.15, lines 17-35, Coon discloses that in the event that two (or more) processing engines 202 request access to target addresses in the same bank 302, the processing engine with the lower identifier I is given priority over the processing engine with the higher identifier.)
Regarding claim 23, Coon in view of Chuang disclose elements of claim 11. In addition, Chuang disclose:
The apparatus of claim 11, wherein the one or more processors comprise the first and second processors (In paragraph [0154], Chuang disclose a first matrix processor labelled “server 0” 1431 and the second two layers will be handled by a second matrix processor labelled “server 1”)
With respect to claim 24, Coon disclose:
At least one same stored data (In Col. 11, lines 47–60, Coon teaches multithreaded processor systems and, in particular to a memory that can be shared by concurrent threads, where multiple threads can access the shared memory in parallel.)
Verifying whether competition occurs between the first data traversal path and the second data traversal path, where a result of the verifying is that competition occurs based on a first operand data of the first data traversal path and a second operand data of the second data traversal path being the same stored data, and in response to the first processor and the second processor being determined to be approaching, according to the first and second data traversal paths, respective executions of the first and second operand data at a same point in time (In Fig. 7 and Col.16-17, lines 54–16, Coon teaches whether conflict occurs between concurrent processing operations by employing address conflict logic 310. Address conflict logic receives pending memory requests from multiple processing engines and a conflict detection unit compares the pending addresses to detect conflict, generating conflict signals when multiple request contend for the same memory resource.)
Executing a first neural network operation by the first processor using the first operand data in parallel with a second neural network operation by the second processor using the second operand data in response to the result of the verifying being that competition does not occur (In Col. 16-17, lines 66-17, Coon teaches executing operations in response to a determination that no conflict exists. Specifically, a go signal is asserted when there are no conflicts, thereby permitting the corresponding request to proceed. However, (In paragraph [0171], Chuang teaches the parallel execution of neural-network operations by first and second processors.))
Respectively executing the first neural network operation by the first processor and the second neural network operation by the second processor in non-parallel order in response to the result of the verifying being that competition does occur, where the non-parallel order is dependent on a determined priority between the first data traversal path and the second data traversal path (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle. However, (In paragraph [0171], Chuang teaches the parallel execution of neural-network operations by first and second processors.))
With respect to claim 24, Coon does not explicitly disclose:
A processor-implemented method, the method comprising: implementing a neural network by executing parallel neural network operations by first and second processors respectively based on a plurality of first data and a plurality of second data, where the plurality of first data is assigned to be utilized by the first processor in order according to a first data traversal path, the plurality of second data is assigned to be utilized by the second processor in order according to a second data traversal path, and the first data traversal path and the second data traversal path overlap with respect to
Wherein each of the plurality of first data and the plurality of second data are respectively parameters of the neural network or input data of the neural network
Wherein the input data of the neural network corresponds to either an input to the neural network or activations of the neural network
However, it is known by Chuang to disclose:
A processor-implemented method, the method comprising: implementing a neural network by executing parallel neural network operations by first and second processors respectively based on a plurality of first data and a plurality of second data, where the plurality of first data is assigned to be utilized by the first processor in order according to a first data traversal path, the plurality of second data is assigned to be utilized by the second processor in order according to a second data traversal path, and the first data traversal path and the second data traversal path overlap with respect to to a second matrix processor (server 1), thereby distributing execution of the neural network across first and second processors. Each processor performs neural -network computations on the data associated with its assigned layers.)
Wherein each of the plurality of first data and the plurality of second data are respectively parameters of the neural network or input data of the neural network (In paragraph [0051], Chuang teaches that the data processed by the artificial neural network includes input data vectors supplied to the neural network and weighted matrices used to transform the input data through successive layers. The weighted matrices constitute neural-network parameters, while the input vectors comprise neural-network input data.)
Wherein the input data of the neural network corresponds to either an input to the neural network or activations of the neural network (In paragraph [0054], Chuang teaches to process input data through a first weighted matrix to generate intermediate output data. The neural-network input data includes both original input data supplied to the artificial neural network and intermediate output data generated by earlier neural-network layers and provided as input to subsequent layers.)
Coon in view of Chuang are analogous pieces of art because both references concern ensuring the correctness or reliability of data before it used in subsequent processing. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Coon, with parallel processing engines executing the threads generate a group of parallel memory access requests as taught by Coon, with various parallel computer systems such as multicore processors and massive parallel processing (MPP) computer systems as taught by Chuang. The motivation for doing so would have been to determine an error and that error is used to adjust as set of weights within the artificial neural networks to improve performance (See [0050] of Chuang.)
Regarding claim 25, Coon in view of Chuang disclose elements of claim 24. In addition, Chuang disclose:
The method of claim 24, further comprising: in response to the result of the verifying being that competition does occur: in response to the selected one being the first neural network operation by the first processor, executing in parallel with the selected one another second neural network operation by the second processor using another second operand data on the second data traversal path subsequent to the second operand data (In Fig. 6 and Col. 15, lines 17–35, Coon teaches resolving detected execution conflicts by changing from parallel execution to priority-based sequential execution. When competing processing engines request access to the same memory resource, the system allows the higher priority request to proceed while deferring the lower-priority request to a later cycle.)
In response to the selected one being the second neural network operation by the second processor, executing in parallel with the selected one another first neural network operation by the first processor using another first operand data on the first data traversal path subsequent to the first operand data (In Col.15, lines 17-35, Coon discloses that In the event that two (or more) processing engines 202 request access to target addresses in the same bank 302, the processing engine with the lower identifier I is given priority over the processing engine with the higher identifier i.)
Claim(s) 2-3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang, in view of Coon and further in view of Xu et al. (US Pub No.: 20200371835 A1), hereinafter referred to as Xu.
Regarding claim 2, Chuang in view of Coon disclose elements of claim 1. Chuang in view of Coon does not disclose:
The method of claim 1, wherein the implementing of the neural network further comprises selectively skipping a neural network operation of the first processor for a data on the first data traversal path, and/or another neural network operation of the second processor for the data or another data on the second data traversal path
However, Xu disclose the limitation (The examiner selects the first portion of claim 2:In paragraph [0050], Xu teaches the determination of which of the 784 convolution operations can be skipped by the convolutional layer.)
Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, having the teaching of Chuang in view of Coon to include Xu, with a subset of a plurality of deterministic computations is selectively performed on new input data to the neural network as taught by Xu. The motivation for doing so would have been to improve, resulting neural network saves power and runs more quickly, without significant compromise to its accuracy (See [0060] of Xu.)
Regarding claim 3, Chuang in view of Coon disclose elements of claim 1. Chuang in view of Coon does not disclose:
The method of claim 1, wherein the selectively skipping further comprises: skipping the first neural network operation in response to the first operand data having a value of "0"; or skipping the first neural network operation in response to the first operand data having a value within a predetermined range
However, Xu disclose the limitation (The examiner selects the first portion of claim 2:In paragraph [0050], Xu teaches the determination of which of the 784 convolution operations can be skipped by the convolutional layer.)
Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, having the teaching of Chuang in view of Coon to include Xu, with a subset of a plurality of deterministic computations is selectively performed on new input data to the neural network as taught by Xu. The motivation for doing so would have been to improve, resulting neural network saves power and runs more quickly, without significant compromise to its accuracy (See [0060] of Xu.)
Regarding claim 12, Chuang in view of Coon disclose elements of claim 11. Chuang in view of Coon does not disclose:
The apparatus of claim 11, wherein the implementation of the neural network further comprises a selective skipping of a neural network operation of the first processor for a data on the first data traversal path, and/or another neural network operation of the second processor for the data or another data on the second data traversal path
However, Xu disclose the limitation (The examiner selects the first portion of claim 2:In paragraph [0050], Xu teaches the determination of which of the 784 convolution operations can be skipped by the convolutional layer.)
Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, having the teaching of Chuang in view of Coon to include Xu, with a subset of a plurality of deterministic computations is selectively performed on new input data to the neural network as taught by Xu. The motivation for doing so would have been to improve, resulting neural network saves power and runs more quickly, without significant compromise to its accuracy (See [0060] of Xu.)
Regarding claim 13, Chuang in view of Coon disclose elements of claim 11. Chuang in view of Coon does not disclose:
The apparatus of claim 11, wherein the selective skipping further comprises: a skipping of the first neural network operation in response to the first operand data having a value of "0"; or the skipping of the first neural operation in response to the first operand data having a value within a predetermined range.
However, Xu disclose the limitation (The examiner selects the first portion of claim 2:In paragraph [0050], Xu teaches the determination of which of the 784 convolution operations can be skipped by the convolutional layer.)
Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, having the teaching of Chuang in view of Coon to include Xu, with a subset of a plurality of deterministic computations is selectively performed on new input data to the neural network as taught by Xu. The motivation for doing so would have been to improve, resulting neural network saves power and runs more quickly, without significant compromise to its accuracy (See [0060] of Xu.)
Claim(s) 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang ,in view of Coon and further in view of Demaj et al. (US Pub No.: 20180293441 A1), hereinafter referred to as Demaj.
Regarding claim 10, Chuang in view of Coon disclose the elements of claim 1 Chuang in view of Coon do not explicitly disclose:
The method of claim 1, wherein the first data traversal path and the second data traversal path each have a corresponding predetermined traversal range corresponding to a respective predetermined number of parameters of the neural network or input data of the neural network, and wherein the implementing of the neural network further comprises respectively updating, with another respective predetermined number of the parameters of the neural network or the input data of the neural network, each of the first data traversal path and the second data traversal path, in response to respective completions of traversals of the first data traversal path by the first processor and the second data traversal path by the second processor
However, Demaj disclose the limitation (In paragraph [0132-0134], Demaj discloses that the first and second processing module's corresponding attribute has the current value. The first and second processing module determines an initial confidence index from all the first and second probabilities taken into account along the traversed path. Each first distribution of probabilities and the second distribution of probabilities result in a value.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chuang in view of Coon before them, to include Demaj, with acquiring current values of the attributes so as to traverse a path within the decision tree and obtain at the output of the path. The motivation for doing so would have been to improve the reliability of the classification obtained at the output of a decision tree (See[0013] of Demaj.)
Regarding claim 20, Chuang in view of Coon disclose the elements of claim 11. Chuang in view of Coon do not explicitly disclose:
The apparatus of The apparatus of wherein the first data traversal path and the second data traversal path each have a corresponding predetermined traversal range corresponding to a respective predetermined number of parameters of the neural network or input data of the neural network, and wherein the implementation of the neural network further comprises a respective updating, with another respective predetermined number of the parameters of the neural network or the input data of the neural network, of each of the first data traversal path and the second data traversal path, in response to respective completions of traversals of the first data traversal path by the first processor and the second data traversal path by the second processor
However, Demaj disclose the limitation (In paragraph [0132-0134], Demaj discloses that the first and second processing module's corresponding attribute has the current value. The first and second processing module determines an initial confidence index from all the first and second probabilities taken into account along the traversed path. Each first distribution of probabilities and the second distribution of probabilities result in a value.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chuang in view of Coon before them, to include Demaj, with acquiring current values of the attributes so as to traverse a path within the decision tree and obtain at the output of the path. The motivation for doing so would have been to improve the reliability of the classification obtained at the output of a decision tree (See[0013] of Demaj.)
Response to Arguments
Applicant's arguments filed on 04/28/2026 have been fully considered, and in part are persuasive
Pertaining to Rejection under 101
Applicant’s argument in regard to 101 is persuasive and rejection is withdrawn
Pertaining to Rejection under 103
Applicant’s arguments in regard to the examiner’s rejections under 35 USC 103 are moot in view of the new grounds of rejection
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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EVEL HONORE
Examiner
Art Unit 2142
/HAIMEI JIANG/Primary Examiner, Art Unit 2142
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