DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RCE filed 3/4/2025 is acknowledged.
Claims 21, 30, and 39 have been amended.
Claims 1-20, 22, 24, 25, 29, 31, 33, 34, 38, and 40 are previously cancelled.
Claims 21, 23, 26-28, 30, 32, 35-37, 39, and 41-43 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 44-48, 51-55, and 58 are rejected under 35 U.S.C. 103 as being unpatentable over Khoryaev et al. (US20220140967A1), hereafter Khoryaev, in view of Osawa et al. (US20210321384A1), hereafter Osawa.
Regarding claims 44, 51, and 58,
Khoryaev discloses a first terminal apparatus (Fig. 4, UE 401) comprising one or more processors; and a memory/computer-readable storage medium that stores instructions/computer programs, and when executing the instructions/programs stored in the memory/non-transitory computer-readable storage medium by a computer apparatus (Fig. 7-9, 13; paragraphs 261-265) enabling to performing a method (Fig. 3) comprising obtaining synchronization resource configuration information (paragraph 99-101; sync source/hop/SSB index), wherein the synchronization resource configuration information is used to configure a first synchronization resource (SPSS) and a second synchronization resource (SSSS) of a sidelink (Fig. 2-3; paragraph 3-5).
Khoryaev shows synchronization signal blocks comprises at least one P symbol carrying a primary sidelink synchronization signal (Fig. 2, 202), at least one S symbol carrying a secondary sidelink synchronization signal (Fig. 2, 204), and at least two B symbols carrying a physical sidelink broadcast channel (Fig. 2, 206; PSBCH/DMRS), and have at least one of the following four features: 1) a quantity of B symbols in a time domain resource occupied by the first synchronization signal block is different from a quantity of B symbols in a time domain resource occupied by the second synchronization signal block; 2) a spacing between the at least one P symbol and the at least one S symbol in the time domain resource occupied by the first synchronization signal block is different from a spacing between the at least one P symbol and the at least one S symbol in the time domain resource occupied by the second synchronization signal block (Fig. 1, right side; paragraphs 65-66; number of PSSS/S-PSS symbols allocated in SSB includes different lengths of symbols at different 15/30/60 kHz spacings); 3) a sequence used by the at least one P symbol in the time domain resource occupied by the first synchronization signal block is different from a sequence used by the at least one P symbol in the time domain resource occupied by the second synchronization signal block; or 4) the sequence used by the at least one S symbol in the time domain resource occupied by the first synchronization signal block is different from the sequence used by the at least one S symbol in the time domain resource occupied by the second synchronization signal block (paragraphs 44-53; describes S-PSS design based on PSS design to reduce UE complexity and use of different cyclic shift and/or time reversal mapping to legacy PSS sequences for use in S-PSS, thereby resulting different sequences used for both P and S symbols).
Khoryaev discloses (Fig. 1, right side and paragraph 42-53; frequency for PSS/first sync block and S-PSS/second sync block are the same; paragraph 83, 94; relative locations of SSSS and PSSS within a slot; paragraph 125, 836 and Fig. 2 illustrate TDM within the slot) but does not expressly disclose sending/receiving a first synchronization signal block on the first synchronization resource, and receiving/sending a second synchronization signal block on the second synchronization resource which occupy a portion of symbols in the same synchronization slot, and are time division multiplexed in the synchronization slot.
Osawa discloses analogous art (Fig. 6-15; Background/Summary; paragraph 58) including sending/receiving a first synchronization signal block on the first synchronization resource (Fig. 6, SLSS/PSBCH) and receiving/sending a second synchronization signal block on the second synchronization resource (Fig. 6, PSCCH/PSSCH/PDSCH) which occupy a portion of symbols in the same synchronization slot (Abstract; paragraph 9, 53, 72), and are time division multiplexed in the synchronization slot (Fig. 9, 10, 12, 13 shows various TDM resources in the same slot – compared to Fig 6 of the instant disclosure; paragraph 51, 58-72, 104-105; see also Fig. 15 shows multiple SSBs per synchronization slot - compared to Fig. 7 of the instant disclosure).
It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Khoryaev by sending/receiving a first synchronization signal block on the first synchronization resource, and receiving/sending a second synchronization signal block on the second synchronization resource which occupy a portion of symbols in the same synchronization slot, and are time division multiplexed in the synchronization slot, as shown by Osawa, thereby enabling various use cases for sending and/or receiving synchronization signal blocks within a same slot for V2X service applications.
Regarding claims 45 and 52,
The combination of Khoryaev and Osawa discloses synchronization resource configuration information includes at least one of the following: a periodicity of the first/second synchronization signal (Khoryaev: paragraph 66; 1ms; paragraph 153-154; periodic update timer; Fig. 1; Table 1; paragraph 30, 66, 86; periodicity of the synchronization signal); a time domain offset of the first/second synchronization signal (Osawa: Fig. 9, 10, 12, 13 shows various TDM resources in the same slot) or a frequency domain position of the first/second synchronization signal (Khoryaev: paragraph 105, 304). See motivation above.
Regarding claims 46 and 53,
The combination of Khoryaev and Osawa discloses a subcarrier spacing of a synchronization signal is 15 kHz, and both the first synchronization resource and the second synchronization resource carry one secondary synchronization signal block; or a subcarrier spacing of a frequency domain resource occupied by the synchronization signal is 30 kHz, and both the first synchronization resource and the second synchronization resource carry two secondary synchronization signal blocks; or the subcarrier spacing of the frequency domain resource occupied by the synchronization signal is 60 kHz, and both the first synchronization resource and the second synchronization resource carry four secondary synchronization signal blocks (Fig. 1; Table 1; paragraph 30, 66, 86; describes and illustrates the effect of SCS on the periodicity of the synchronization signal); the subcarrier spacing of the frequency domain resource occupied by the synchronization signal is 120 kHz, and both the first synchronization resource and the second synchronization resource carry eight secondary synchronization signal blocks (Khoryaev does not expressly disclose 120 kHz; claim is presented in alternative language so disclosure of 15/30/60 kHz meets the claim, 120 kHz limitation would be found obvious by one of ordinary skill in the art before the time of effective filing if required - rather than alternative - by the claim construction).
Regarding claims 47 and 54,
The combination of Khoryaev and Osawa discloses a sequence length of the primary sidelink synchronization signal in a symbol, and a sequence length of the secondary sidelink synchronization signal in a symbol, are both 127 (Khoryaev: paragraph 33; Osawa: Fig. 15 shows multiple equal-length SSBs in the same synchronization slot). See motivation above.
Regarding claims 48 and 55,
The combination of Khoryaev and Osawa discloses a quantity of frequency domain resource blocks occupied by a P symbol, an S symbol, or a B symbol is 11 (Khoryaev: Abstract; para 3-4, 30-31, 111; max of 11 PRBs based on SCS).
Claims 49, 50, 56, and 57 are rejected under 35 U.S.C. 103 as being unpatentable over Khoryaev and Osawa as applied to claims 44 and 51 above, and further in view of Kwon et al. (US20180054788A1), hereafter Kwon.
Regarding claims 49, 50, 56, and 57,
The combination of Khoryaev and Osawa discloses various arrangement sequence of the symbols in the time domain resource (Khoryaev: Fig. 2; Osawa: Fig. 9, 10, 12, 13) including P (Fig. 2, 202), S (Fig. 2, 204), B (Fig. 2, 206), and G/gap (Fig. 2, guard period GP 208) symbols adjacent in time domain but fails to expressly show a 1st symbol is a B symbol such that the synchronization signal blocks are one of the following arrangement sequences: {B-P-B-B-B-S-B}, {B-P-B-B-B-S-G}, {B-P-B-B-B-S}, {B-P-B-B-S-B}, or {B-P-B-B-S-G}.
Kwon discloses providing universal synchronization signals for new radio (Title) analogous to Khoryaev (i.e. Fig. 11) including synchronization signal having SPSS/SSSS/PSBCH as in Khoryaev, in which the 1st symbol occupied by the synchronization signal block in a slot is a B symbol (Fig. 5 shows at least 6 B symbols including a B symbol in a 1st symbol prior to PSSS/SSSS) in an arrangement sequence of the symbols in a slot occupied by the synchronization signal block (Fig. 5; paragraph 53-56; initial PSBCH followed by the PSSS/SSSS/remaining PSBCH/DMRS) such that the synchronization blocks are one of the following arrangement sequences: {B-P-B-B-B-S-B}, {B-P-B-B-B-S-G}, {B-P-B-B-B-S}, {B-P-B-B-S-B}, or {B-P-B-B-S-G}.
It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Khoryaev by providing the 1st symbol occupied by the synchronization signal block in a slot is a B symbol, as shown by Kwon, thereby accommodating variations of synchronization signal structure for various D2D communication.
Response to Arguments
Applicant’s arguments filed 9/19/2025 on pg. 11-14 have been considered but are moot because the new ground of rejection relies on newly-cited Osawa reference for any teaching or matter specifically challenged in the argument with respect to transmitting/receiving two synchronization signals within the same sync slot.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GREGORY B SEFCHECK/Primary Examiner, Art Unit 2477
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