DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed December 10, 2025 have been fully considered but are not persuasive. Applicant argues that the claims are allowable because:
“the cited references, either alone or in hypothetical combination, do not appear to teach or suggest at least a soft microprocessor, as recited by the claims. Specifically, the "microprocessor 402" of Karoubalis relies on fixed hardware rather than a soft microprocessor synthesized within programmable logic circuitry and, thus, cannot read on the "soft microprocessor" of claims 2, 11, and 17. See Karoubalis, 11 [0039]-[0045].” (Applicant’s Remarks, Pg. 8).
Examiner respectfully disagrees. The claimed “soft microprocessor” corresponds to the first and second synthesized processors which correspond to first and second accelerators. Examiner has mapped the claimed “soft microprocessor to the combination of Karoubalis- Kruglick. Kruglick teaches reconfigurable soft microprocessor (i.e. FPGA logic circuit) that is programmed with accelerator functions. ([0005], at least one programmable logic circuits is programmed with the selected accelerator program to execute at least some of the instructions of the application; and [0020], a programmable logic circuit in a computing device can be configured with a desired application-specific architecture, or hardware image, via an accelerator program associated with a particular application).
“Neither reference teaches or suggests application-based accelerator selection. Any hypothetical combination of the references would require significant reconstruction of the physical architecture of each reference, leaving a person of ordinary skill in the art with no motivation to combine.” (Applicant’s Remarks, Pg. 9).
Examiner respectfully disagrees. Karoubalis teaches user applications that can dynamically select/ reconfigure accelerators. ([0002], with an FPGA, a design engineer is able to program electrical connections on-site for a specific application; [0010], different user functions can be implemented on demand through dynamic reconfiguration. A software tool provides the means to place and route dynamically reconfigurable designs in the FPGA and also generate appropriate bitstream files; and [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404).
“even in hypothetical combination, the references fail to teach or suggest application specific swapping of soft microprocessor accelerators in independent dynamic regions while a static region remains active, which would require hindsight beyond anything taught in the references themselves.” (Applicant’s Remarks Pg. 9).
Examiner respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “swapping of soft microprocessor accelerators in independent dynamic regions”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, Karoubalis teaches an FGPA that has a dynamic part and an active static part. ([0008], The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA), and dynamic part including a first dynamic macro and a second dynamic macro. The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured; and [0010], An FPGA is provided that implements a supporting infrastructure in the static part that substantially operates in all configurations of the FPGA; and [0029], static part 102 corresponds to logic within FPGA 100 that must always be present and running within FPGA 100).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3, 5-6, 11, and 16-21, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Karoubalis et al. (US 20070283311) in view of Kruglick et al. (US 20140380025).
As per claim 2, Karoubalis teaches the invention substantially as claimed including a device ([0040], A combination of a microprocessor and an FPGA supporting dynamic reconfiguration on a SoC platform (such as SoC platform 400) can be used to implement a general-purpose microprocessor system with a hardware accelerator), comprising:
a first dynamic region of programmable logic circuitry ([0006], The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured) configurable to receive one or more accelerators [from a database communicatively coupled to the first dynamic region] ([0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros)) and configurable to include a first accelerator [from the database] ([0008], The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured. The first dynamic macro is operable to execute a first operation associated with a user program; and [0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros)), the first accelerator configured to be matched, via a dispatcher, to a first application to be accelerated based on a first acceleration request of the first application ([0002], with an FPGA, a design engineer is able to program electrical connections on-site for a specific application; [0008], The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured. The first dynamic macro is operable to execute a first operation associated with a user program; and [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404), the first accelerator comprising a first synthesized processor ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured; [0045], According to the implementation shown in FIG. 5, microprocessor 402 is operable to be reconfigured based on dynamic macros within FPGA 404. In one implementation, a library of pre-compiled IP cores are associated with a virtual socket of FPGA 404. The library of pre-compiled IP cores can be stored in the external memory shown in FIG. 4. The reconfiguration controller manages the reconfiguration of FPGA 404. Based on inputs to a software tool, the reconfiguration controller signals when to reconfigure the virtual socket and which IP core to load; and [0056], the use of dynamic reconfiguration requires additional constraints on the synthesis of user (dynamic) macros. The designs are usually synthesized as several independent user designs that are packed together during placement and routing--i.e., when all valid FPGA configurations must be assembled to produce valid configuration bitstreams) formed using programmable logic circuitry in the first dynamic region of the programmable logic circuitry,
a second dynamic region of the programmable logic circuitry ([0006], The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured) configurable to receive one or more accelerators [from the database communicatively coupled to the second dynamic region] ([0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros)) and configurable to include a second accelerator [from the database] ([0008], The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured. The first dynamic macro is operable to execute a first operation associated with a user program; and [0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros)), the second accelerator configured to be matched, via the dispatcher, to a second application to be accelerated based on a second acceleration request of the second application ([0009], the second operation is operable to execute a second operation associated with the task using the second dynamic macro; [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404; and [0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros)), the second accelerator comprising a second synthesized processor ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured; [0045], According to the implementation shown in FIG. 5, microprocessor 402 is operable to be reconfigured based on dynamic macros within FPGA 404. In one implementation, a library of pre-compiled IP cores are associated with a virtual socket of FPGA 404. The library of pre-compiled IP cores can be stored in the external memory shown in FIG. 4. The reconfiguration controller manages the reconfiguration of FPGA 404. Based on inputs to a software tool, the reconfiguration controller signals when to reconfigure the virtual socket and which IP core to load; and [0056], the use of dynamic reconfiguration requires additional constraints on the synthesis of user (dynamic) macros. The designs are usually synthesized as several independent user designs that are packed together during placement and routing--i.e., when all valid FPGA configurations must be assembled to produce valid configuration bitstreams) formed using programmable logic circuitry in the second dynamic region of the programmable logic circuitry ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured); and
a static region comprising circuitry to support the first dynamic region and the second dynamic region ([0010], An FPGA is provided that implements a supporting infrastructure in the static part that substantially operates in all configurations of the FPGA), wherein the static region comprises programmable logic circuitry and is not to be reconfigured during the configuration of the first dynamic region and the second dynamic region ([0009], The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA); [0029], static part 102 corresponds to logic within FPGA 100 that must always be present and running within FPGA 100, and dynamic part 104 corresponds to logic that can be loaded or unloaded from FPGA 100 as needed. In one implementation, only static part 102 is connected to one or more input pin (PI) and one or more output pins (PO) of FPGA 100).
Karoubalis fails to specifically teach, a first dynamic region of programmable logic circuitry configurable to receive one or more accelerators from a database communicatively coupled to the first dynamic region and configurable to include a first accelerator from the database... wherein the first synthesized processor comprises a first soft microprocessor; and a second dynamic region of the programmable logic circuitry configurable to receive one or more accelerators from the database communicatively coupled to the second dynamic region and configurable to include a second accelerator from the database... wherein the second synthesized processor comprises a second soft microprocessor.
However, Kruglick teaches, a first dynamic region of programmable logic circuitry configurable to receive one or more accelerators from a database communicatively coupled to the first dynamic region ([0025], field-programmable logic circuits 121-124 may be programmed with any combination of hardware accelerators available from accelerator programs 151-158 stored in library 150; and [0026] The received accelerator program may be saved in library 150 and may also be used to program field-programmable logic circuit 122 with a particular hardware accelerator image) and configurable to include a first accelerator from the database ([0025], field-programmable logic circuits 121-124 may be programmed with any combination of hardware accelerators available from accelerator programs 151-158 stored in library 150; and [0029], Library 150 stores accelerator programs 151-158 that are each associated with either software applications installed on the host computing device that includes processor chip 100 or web applications that are not installed on processor chip 100 but are run on processor chip 100. Specifically, accelerator programs 151-158 are configured to program a suitable field-programmable logic circuit in processor chip 100 with hardware accelerators 151A-158A, respectively) ... wherein the first synthesized processor comprises a first soft microprocessor ([0005], at least one programmable logic circuits is programmed with the selected accelerator program to execute at least some of the instructions of the application; and [0020], a programmable logic circuit in a computing device can be configured with a desired application-specific architecture, or hardware image, via an accelerator program associated with a particular application); and
a second dynamic region of the programmable logic circuitry configurable to receive one or more accelerators from the database communicatively coupled to the second dynamic region ([0025], field-programmable logic circuits 121-124 may be programmed with any combination of hardware accelerators available from accelerator programs 151-158 stored in library 150) and configurable to include a second accelerator from the database ([0025], field-programmable logic circuits 121-124 may be programmed with any combination of hardware accelerators available from accelerator programs 151-158 stored in library 150; and [0029], Library 150 stores accelerator programs 151-158 that are each associated with either software applications installed on the host computing device that includes processor chip 100 or web applications that are not installed on processor chip 100 but are run on processor chip 100. Specifically, accelerator programs 151-158 are configured to program a suitable field-programmable logic circuit in processor chip 100 with hardware accelerators 151A-158A, respectively)...wherein the second synthesized processor comprises a second soft microprocessor ([0005], at least one programmable logic circuits is programmed with the selected accelerator program to execute at least some of the instructions of the application; [0006], the programmable logic circuit in the processor chip is programmed with the second accelerator program; and [0020], a programmable logic circuit in a computing device can be configured with a desired application-specific architecture, or hardware image, via an accelerator program associated with a particular application).
Kruglick also teaches, the first accelerator configured to be matched, via a dispatcher, to a first application to be accelerated based on a first acceleration request of the first application ([0024], each of field-programmable logic circuits 121-124 can be reprogrammed as desired during operation with a hardware accelerator image and function as a hardware accelerator for a specific application; [0029], Library 150 stores accelerator programs 151-158 that are each associated with either software applications installed on the host computing device that includes processor chip 100 or web applications that are not installed on processor chip 100 but are run on processor chip 100; [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404; and [0044], In block 202, hardware strategy module 170 selects an appropriate accelerator program from library 150 based on the information collected in block 201), the first accelerator comprising a first synthesized processor formed using programmable logic circuitry in the first dynamic region of the programmable logic circuitry ([0039], processor chip 100 receives one or more accelerator programs, such as accelerator programs 151-158, which are programmed into available field-programmable logic circuits 121-124 and are also stored in library 150. Each of the one or more accelerator programs may be received in conjunction with an associated application being loaded onto the host computing device that includes processor chip 100… Accelerator reconfigure module 180 then fetches the desired accelerator programs and facilitates the programming thereof into the desired field-programmable logic circuits 121-124; and [0045], accelerator reconfigure module 180 fetches one or more of accelerator programs 151-158 that correspond to the accelerator programs selected in block 202. In some embodiments, accelerator reconfigure module 180 may also facilitate the programming of one or more of field-programmable logic circuits 121-124 with the accelerator programs selected in block 202. In some embodiments, one or more field-programmable logic circuits 121-124 are reprogrammed in block 203 from a preexisting architecture to a new architecture using the fetched accelerator program), the first accelerator comprising a first synthesized processor formed using programmable logic circuitry in the first dynamic region of the programmable logic circuitry ([0024], each of field-programmable logic circuits 121-124 can be reprogrammed as desired during operation with a hardware accelerator image and function as a hardware accelerator for a specific application…each of field-programmable logic circuits 121-124 can be reprogrammed as desired during operation with a hardware accelerator image and function as a hardware accelerator for a specific application. To that end, one or more of field-programmable logic circuits 121-124 may include programmable logic components referred to as "logic blocks" and a hierarchy of reconfigurable interconnects that allow the logical blocks to be inter-wired in different configurations); and
the second accelerator configured to be matched, via the dispatcher, to based on a second application to be accelerated based on a second acceleration request of the second application ([0024], each of field-programmable logic circuits 121-124 can be reprogrammed as desired during operation with a hardware accelerator image and function as a hardware accelerator for a specific application; [0029], Library 150 stores accelerator programs 151-158 that are each associated with either software applications installed on the host computing device that includes processor chip 100 or web applications that are not installed on processor chip 100 but are run on processor chip 100; [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404; and [0044], In block 202, hardware strategy module 170 selects an appropriate accelerator program from library 150 based on the information collected in block 201), the second accelerator comprising a second synthesized processor formed using programmable logic circuitry in the second dynamic region of the programmable logic circuitry ([0024], each of field-programmable logic circuits 121-124 can be reprogrammed as desired during operation with a hardware accelerator image and function as a hardware accelerator for a specific application…each of field-programmable logic circuits 121-124 can be reprogrammed as desired during operation with a hardware accelerator image and function as a hardware accelerator for a specific application. To that end, one or more of field-programmable logic circuits 121-124 may include programmable logic components referred to as "logic blocks" and a hierarchy of reconfigurable interconnects that allow the logical blocks to be inter-wired in different configurations).
Karoubalis and Kruglick are analogous because they are each related to providing reconfigurable accelerators. Karoubalis teaches a method for selecting logic for reconfiguring a FPGA comprising a static part and a dynamic part. ([0016], The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured. The method further includes executing a first operation associated with the user application using the first dynamic macro; reconfiguring the second macro to execute a second operation associated with the user application prior to completion of the first operation; and upon completion of the first operation, executing the second operation using the second dynamic macro; and [0010], different user functions can be implemented on demand through dynamic reconfiguration. A software tool provides the means to place and route dynamically reconfigurable designs in the FPGA and also generate appropriate bitstream files. The described methods provide the following features: a way to define an organization and design description on the reconfigurable logic; a way to describe spatial and temporal FPGA contexts; a way to reduce placement complexity and guide the independent placements and routings of the independent contexts of the reconfigurable parts of the FPGA; a way to organize reconfiguration data into bitstreams in an efficient manner; and a way to implement reconfigurable accelerators attached to a microprocessor). Kruglick teaches a method for accelerator reconfiguration using accelerator images received from a database. ([0021], the management of hardware accelerators may be optimized by selecting which hardware accelerator images are implemented in the one or more programmable logic circuits. The hardware accelerator images may be chosen from a library of accelerator programs downloaded to a device associated with the processor chip). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that based on the combination, the teachings of Karoubalis would be modified with the database of available accelerators as taught by Kruglick resulting in a system that accelerates tasks using accelerators selected from a database. Therefore, it would have been obvious to combine the teachings of Karoubalis and Kruglick.
As per claim 3, Karoubalis teaches, wherein the first dynamic region, the second dynamic region, the static region, or any combination thereof, comprise field programmable gate array (FPGA) programmable logic ([0008], this specification describes a field programmable gate array (FPGA). The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA), and dynamic part including a first dynamic macro and a second dynamic macro. The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured).
As per claim 5, Karoubalis teaches, wherein dynamically configuring comprises adding, removing, or a combination thereof, the first accelerator, the second accelerator, or both based at least in part on accelerators used to accelerate the first application or the second application ([0009], The first dynamic macro is operable to execute a first operation associated with the task. The second macro is operable to be reconfigured while the first dynamic macro is executing the first operation. Upon completion of the first operation, the second operation is operable to execute a second operation associated with the task using the second dynamic macro).
As per claim 6, Karoubalis teaches, wherein the first dynamic region and the second dynamic region are to be partially reconfigured ([0009], The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured; [0054], partial bitstreams for dynamic macros are created by comparing two bitstream files--one held by a design context having a specific dynamic macro present, and the other held by the same design context without the dynamic macro present. The differences between the two bitstream files hold only the elementary changes on the FPGA regarding the existence or the removal of a specific dynamic macro are, therefore, optimized in size) while the static region is not partially reconfigured ([0009], The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA); [0029], static part 102 corresponds to logic within FPGA 100 that must always be present and running within FPGA 100, and dynamic part 104 corresponds to logic that can be loaded or unloaded from FPGA 100 as needed. In one implementation, only static part 102 is connected to one or more input pin (PI) and one or more output pins (PO) of FPGA 100).
As per claim 11, Karoubalis teaches the invention as claimed including a system, comprising:
a plurality of regions ([0006], The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured) configurable to dynamically add one or more accelerators [from a database of accelerators] ([0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros)) to accelerate a first task based on a first acceleration request from a first application ([0002], with an FPGA, a design engineer is able to program electrical connections on-site for a specific application; [0008], The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured. The first dynamic macro is operable to execute a first operation associated with a user program; and [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404) and to accelerate a second task based on a second acceleration request from a second application ([0009], the second operation is operable to execute a second operation associated with the task using the second dynamic macro; [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404; and [0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros)), wherein the one or more accelerators comprise one or more synthesized processors ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured; [0045], According to the implementation shown in FIG. 5, microprocessor 402 is operable to be reconfigured based on dynamic macros within FPGA 404. In one implementation, a library of pre-compiled IP cores are associated with a virtual socket of FPGA 404. The library of pre-compiled IP cores can be stored in the external memory shown in FIG. 4. The reconfiguration controller manages the reconfiguration of FPGA 404. Based on inputs to a software tool, the reconfiguration controller signals when to reconfigure the virtual socket and which IP core to load; and [0056], the use of dynamic reconfiguration requires additional constraints on the synthesis of user (dynamic) macros. The designs are usually synthesized as several independent user designs that are packed together during placement and routing--i.e., when all valid FPGA configurations must be assembled to produce valid configuration bitstreams) formed using programmable logic circuitry in a region of the plurality of regions ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured); and
a static region not to be reconfigured ([0009], The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA); [0029], static part 102 corresponds to logic within FPGA 100 that must always be present and running within FPGA 100, and dynamic part 104 corresponds to logic that can be loaded or unloaded from FPGA 100 as needed. In one implementation, only static part 102 is connected to one or more input pin (PI) and one or more output pins (PO) of FPGA 100), the static region comprising circuitry to support the plurality of regions ([0010], An FPGA is provided that implements a supporting infrastructure in the static part that substantially operates in all configurations of the FPGA).
Karoubalis fails to specifically teach, a plurality of regions configurable to dynamically add one or more accelerators from a database of accelerators.
However, Kruglick a plurality of regions configurable to dynamically add one or more accelerators from a database of accelerators ([0025], field-programmable logic circuits 121-124 may be programmed with any combination of hardware accelerators available from accelerator programs 151-158 stored in library 150; and [0026] The received accelerator program may be saved in library 150 and may also be used to program field-programmable logic circuit 122 with a particular hardware accelerator image).
The same motivation used in the rejection of claim 2 is applicable to the instant clam.
As per claim 16, Karoubalis teaches, wherein at least one of the plurality regions is reconfigurable to add, remove, or a combination thereof, an accelerator to accelerate a different task ([0009], The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured; and [0030], A dynamic macro represents a portion of (user) logic that can be removed in certain configurations of FPGA 100).
As per claim 17, Karoubalis teaches the invention as claimed including a device, comprising:
a memory ([0039], system-on-chip (SoC) platform 400 including … a memory (SRAM) 406); and
processing circuitry coupled to the memory ([0039], system-on-chip (SoC) platform 400 including a microprocessor 402, [and] an FPGA 404), the processing circuitry comprising:
a first dynamic region ([0006], The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured) configurable to comprise one or more accelerators [of a database of accelerators] ([0040], A combination of a microprocessor and an FPGA supporting dynamic reconfiguration on a SoC platform (such as SoC platform 400) can be used to implement a general-purpose microprocessor system with a hardware accelerator; and [0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros); and [0055], Reconfiguration in FPGAs is implemented as a data transfer operation between bitstream storage (e.g., the external memory of FIG. 4) and special locations inside of the FPGA (e.g., FPGA 404)) and configurable to dynamically include a first accelerator of the one or more accelerators based on a first acceleration request from a first application to be accelerated ([0008], The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured. The first dynamic macro is operable to execute a first operation associated with a user program; [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404; and [0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros)), the first accelerator comprising a first synthesized processor ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured; [0045], According to the implementation shown in FIG. 5, microprocessor 402 is operable to be reconfigured based on dynamic macros within FPGA 404. In one implementation, a library of pre-compiled IP cores are associated with a virtual socket of FPGA 404. The library of pre-compiled IP cores can be stored in the external memory shown in FIG. 4. The reconfiguration controller manages the reconfiguration of FPGA 404. Based on inputs to a software tool, the reconfiguration controller signals when to reconfigure the virtual socket and which IP core to load; and [0056], the use of dynamic reconfiguration requires additional constraints on the synthesis of user (dynamic) macros. The designs are usually synthesized as several independent user designs that are packed together during placement and routing--i.e., when all valid FPGA configurations must be assembled to produce valid configuration bitstreams) formed using field programmable gate array circuitry in the first dynamic region ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured); and
a second dynamic region ([0006], The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured) configurable to comprise one or more accelerators [of the database of accelerators] ([0040], A combination of a microprocessor and an FPGA supporting dynamic reconfiguration on a SoC platform (such as SoC platform 400) can be used to implement a general-purpose microprocessor system with a hardware accelerator) of the database of accelerators ([0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros); and [0055], Reconfiguration in FPGAs is implemented as a data transfer operation between bitstream storage (e.g., the external memory of FIG. 4) and special locations inside of the FPGA (e.g., FPGA 404)) and configurable to dynamically include a second accelerator of the one or more accelerators based on a second acceleration request from a second application to be accelerated ([0009], the second operation is operable to execute a second operation associated with the task using the second dynamic macro; and [0044], the external memory stores the information and context (or bitstreams) needed to reconfigure the hardware accelerator. An FPGA register (CONTEXT in RCFG CTRL) can be used for context (bitstream) selection and as a data path between the external memory, the reconfiguration controller, and the FPGA configuration logic (e.g., dynamic macros); and [0041], when the low-level OS (operating system) of microprocessor 402 detects a request for an operation different than the current function implemented within FPGA 404, the low-level OS calls a function that reconfigures FPGA 404), the second accelerator comprising a second synthesized processor ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured; [0045], According to the implementation shown in FIG. 5, microprocessor 402 is operable to be reconfigured based on dynamic macros within FPGA 404. In one implementation, a library of pre-compiled IP cores are associated with a virtual socket of FPGA 404. The library of pre-compiled IP cores can be stored in the external memory shown in FIG. 4. The reconfiguration controller manages the reconfiguration of FPGA 404. Based on inputs to a software tool, the reconfiguration controller signals when to reconfigure the virtual socket and which IP core to load; and [0056], the use of dynamic reconfiguration requires additional constraints on the synthesis of user (dynamic) macros. The designs are usually synthesized as several independent user designs that are packed together during placement and routing--i.e., when all valid FPGA configurations must be assembled to produce valid configuration bitstreams) formed using field programmable gate array circuitry in the second dynamic region ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured),
Karoubalis fails to specifically teach, a first dynamic region configurable to comprise one or more accelerators of a database of accelerators.. wherein the first synthesized processor comprises a first soft microprocessor;; and a second dynamic region configurable to comprise one or more accelerators of the database of accelerators.. wherein the second synthesized processor comprises a second soft microprocessor;.
However, Kruglick teaches, a first dynamic region configurable to comprise one or more accelerators of a database of accelerators ([0025], field-programmable logic circuits 121-124 may be programmed with any combination of hardware accelerators available from accelerator programs 151-158 stored in library 150; and [0026] The received accelerator program may be saved in library 150 and may also be used to program field-programmable logic circuit 122 with a particular hardware accelerator image) .. wherein the first synthesized processor comprises a first soft microprocessor ([0005], at least one programmable logic circuits is programmed with the selected accelerator program to execute at least some of the instructions of the application; and [0020], a programmable logic circuit in a computing device can be configured with a desired application-specific architecture, or hardware image, via an accelerator program associated with a particular application); and
a second dynamic region configurable to comprise one or more accelerators of the database of accelerators ([0025], field-programmable logic circuits 121-124 may be programmed with any combination of hardware accelerators available from accelerator programs 151-158 stored in library 150; and [0026] The received accelerator program may be saved in library 150 and may also be used to program field-programmable logic circuit 122 with a particular hardware accelerator image)... wherein the second synthesized processor comprises a second soft microprocessor([0005], at least one programmable logic circuits is programmed with the selected accelerator program to execute at least some of the instructions of the application; [0006], the programmable logic circuit in the processor chip is programmed with the second accelerator program; and [0020], a programmable logic circuit in a computing device can be configured with a desired application-specific architecture, or hardware image, via an accelerator program associated with a particular application).
The same motivation used in the rejection of claim 2 is applicable to the instant claim.
As per claim 18, Karoubalis teaches, wherein a field programmable gate array (FPGA) comprises the first dynamic region and the second dynamic region ([0009], The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA), and dynamic part including a first dynamic macro and a second dynamic macro. The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured).
As per claim 19, Karoubalis teaches, comprising:
a static region configurable to support the first dynamic region and the second dynamic region ([0008], this specification describes a field programmable gate array (FPGA). The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA), and dynamic part including a first dynamic macro and a second dynamic macro), wherein the static region comprises programmable logic circuitry and is not to be reconfigured during a configuration of the first dynamic region or the second dynamic region ([0009], The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA); [0029], static part 102 corresponds to logic within FPGA 100 that must always be present and running within FPGA 100, and dynamic part 104 corresponds to logic that can be loaded or unloaded from FPGA 100 as needed. In one implementation, only static part 102 is connected to one or more input pin (PI) and one or more output pins (PO) of FPGA 100).
As per claim 20, Karoubalis teaches, wherein the first dynamic region and the second dynamic region are to be partially reconfigured while the static region is not partially reconfigured ([0009], The field programmable gate array (FPGA) includes a static part that corresponds to logic within the field programmable gate array (FPGA) that is present in substantially all configurations of the field programmable gate array (FPGA), and dynamic part including a first dynamic macro and a second dynamic macro. The first dynamic macro and the second dynamic macro each represent logic within the field programmable gate array (FPGA) that can be reconfigured; [0029], static part 102 corresponds to logic within FPGA 100 that must always be present and running within FPGA 100, and dynamic part 104 corresponds to logic that can be loaded or unloaded from FPGA 100 as needed. In one implementation, only static part 102 is connected to one or more input pin (PI) and one or more output pins (PO) of FPGA 100).
As per claim 21, Karoubalis teaches, wherein the first dynamic region and the second dynamic region are to be partially reconfigured by adding, removing, or a combination thereof, at least one accelerator ([0006], The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured. The method further includes executing a first operation associated with the user program using the first dynamic macro; reconfiguring the second macro to execute a second operation associated with the user program prior to completion of the first operation; and upon completion of the first operation, executing the second operation using the second dynamic macro; and [0030], Dynamic part 104 includes dynamic macros 106, 108 and a supermacro 110. Though dynamic part 104 is shown as including (2) dynamic macros and (1) supermacro, in general, dynamic part 104 contains at least two dynamic macros, or one dynamic macro and one supermacro, or one supermacro. A dynamic macro represents a portion of (user) logic that can be removed in certain configurations of FPGA 100).
As per claim 23, Karoubalis teaches, wherein the first accelerator comprising the first synthesized processor ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured; [0045], According to the implementation shown in FIG. 5, microprocessor 402 is operable to be reconfigured based on dynamic macros within FPGA 404. In one implementation, a library of pre-compiled IP cores are associated with a virtual socket of FPGA 404. The library of pre-compiled IP cores can be stored in the external memory shown in FIG. 4. The reconfiguration controller manages the reconfiguration of FPGA 404. Based on inputs to a software tool, the reconfiguration controller signals when to reconfigure the virtual socket and which IP core to load; and [0056], the use of dynamic reconfiguration requires additional constraints on the synthesis of user (dynamic) macros. The designs are usually synthesized as several independent user designs that are packed together during placement and routing--i.e., when all valid FPGA configurations must be assembled to produce valid configuration bitstreams), the second accelerator comprising the second synthesized processor ([0006], The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured; [0045], According to the implementation shown in FIG. 5, microprocessor 402 is operable to be reconfigured based on dynamic macros within FPGA 404. In one implementation, a library of pre-compiled IP cores are associated with a virtual socket of FPGA 404. The library of pre-compiled IP cores can be stored in the external memory shown in FIG. 4. The reconfiguration controller manages the reconfiguration of FPGA 404. Based on inputs to a software tool, the reconfiguration controller signals when to reconfigure the virtual socket and which IP core to load; and [0056], the use of dynamic reconfiguration requires additional constraints on the synthesis of user (dynamic) macros. The designs are usually synthesized as several independent user designs that are packed together during placement and routing--i.e., when all valid FPGA configurations must be assembled to produce valid configuration bitstreams), or both are responsive to a control register ([0044], the reconfiguration controller fetches FPGA configuration information from the bitstream memory and writes the configuration information to FPGA configuration memory).
As per claim 24, Karoubalis teaches, wherein the first accelerator and the second accelerator comprise a general-purpose processor ([0006], a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured; and [0043], FPGA floating-point coprocessor), a specialized embedded processor ([0041], FPGA coprocessor (IP core) is implemented as a special low-level function), an OpenCL processor, an application-specific-set (ASIP) processor, a fixed function (FF) processor, or a digital signal processor (DSP), or any combination thereof.
Claims 7-9, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Karoubalis- Kruglick as applied to independent claims 2, 11, and 17 and in further view of Chiou et al. (US 20160378460).
As per claim 7, the combination of Karoubalis- Kruglick fails to specifically teach, wherein the static region is configurable to communicate data over a peripheral component interconnect express (PCIe) interface.
However, Chiou teaches, wherein the static region is configurable to communicate data over a peripheral component interconnect express (PCIe) interface ([0056], host component 108 is coupled to acceleration component 110 through a local link 112 (e.g., a Peripheral Component Interconnect Express (PCIe) link). Thus, host component 108 is a local host component form the perspective of acceleration component 110 and acceleration component 110 is a local acceleration component from the perspective of host component 108).
The combination of Karoubalis- Kruglick and Chiou are analogous because they are each related to reconfigurable accelerators. Karoubalis teaches a method for reconfiguring a FPGA comprising a static part and a dynamic part. Kruglick teaches a method for accelerator reconfiguration using accelerator images received from a database. Chiou teaches a method for accelerator reconfiguration including partial reconfiguration for various types of tasks. (Abstract, partially reconfiguring acceleration components. Partial reconfiguration can be implemented for any of a variety of reasons, including to address an error in functionality at the acceleration component or to update functionality at the acceleration component. During partial reconfiguration, connectivity can be maintained for any other functionality at the acceleration component untouched by the partial reconfiguration. Partial reconfiguration is more efficient to deploy than full reconfiguration of an acceleration component; and [0079], The application domain hosts application logic 706 that performs service specific tasks (such as a portion of functionality for … facilitating computer vision, facilitating speech translation, etc.)). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that based on the combination, the teachings of Karoubalis would be modified with the networking and media task processing mechanisms taught by Chiou resulting in a system that accelerates a variety of tasks. Therefore, it would have been obvious to combine the teachings of Karoubalis and Chiou.
As per claim 8, Karoubalis fails to specifically teach, wherein the first accelerator, the second accelerator, or both is configurable to accelerate a task associated with media processing.
However, Chiou teaches wherein the first accelerator, the second accelerator, or both is configurable to accelerate a task associated with media processing ([0079], The application domain hosts application logic 706 that performs service specific tasks (such as a portion of functionality for … facilitating computer vision, facilitating speech translation, etc.)).
The same motivation used in the rejection of claim 7 is applicable to the instant claim.
As per claim 9, Karoubalis fails to specifically teach, wherein the first accelerator, the second accelerator, or both is configurable to accelerate a task associated with a real-time application.
However, Chiou teaches, wherein the first accelerator, the second accelerator, or both is configurable to accelerate a task associated with a real-time application ([0079], The application domain hosts application logic 706 that performs service specific tasks (such as a portion of functionality for ranking documents, encrypting data, compressing data, facilitating computer vision, facilitating speech translation, etc.)).
The same motivation used in the rejection of claim 7 is applicable to the instant claim.
As per claim 10, Karoubalis fails to specifically teach, wherein the first accelerator, the second accelerator, or both is configurable to accelerate a task associated with media encoding.
However, Chiou teaches, wherein the first accelerator, the second accelerator, or both is configurable to accelerate a task associated with media encoding ([0079], The application domain hosts application logic 706 that performs service specific tasks (such as a portion of functionality for … facilitating computer vision, facilitating speech translation, etc.)).
The same motivation used in the rejection of claim 7 is applicable to the instant claim.
As per claim 12, the combination of Karoubalis- Kruglick fails to specifically teach, wherein the static region is configurable to communicate data over a peripheral component interconnect express (PCIe) interface.
However, Chiou teaches, wherein the static region is configurable to communicate data over a peripheral component interconnect express (PCIe) interface ([0056], host component 108 is coupled to acceleration component 110 through a local link 112 (e.g., a Peripheral Component Interconnect Express (PCIe) link). Thus, host component 108 is a local host component form the perspective of acceleration component 110 and acceleration component 110 is a local acceleration component from the perspective of host component 108).
The same motivation used in the rejection of claim 7 is applicable to the instant claim.
As per claim 13, the combination of Karoubalis- Kruglick fails to specifically teach, comprising: a network interface configurable to enable communication with the one or more accelerators of the database of accelerators over a network.
However, Chiou teaches, comprising:
a network interface configurable to enable communication with the one or more accelerators of the database of accelerators over a network ([0081], shell resources include bridge 708 for coupling acceleration component 702 to the network interface controller (via a NIC interface 710) and a local top-of-rack switch (via a TOR interface 712). Bridge 708 also includes a data path that allows traffic from the NIC or TOR to flow into acceleration component 702, and traffic from the acceleration component 702 to flow out to the NIC or TOR).
The same motivation used in the rejection of claim 7 is applicable to the instant claim.
As per claim 14, the combination of Karoubalis- Kruglick fails to specifically teach, wherein at least one accelerator of the one or more accelerators is to accelerate a task associated with media processing.
However, Chiou teaches, wherein at least one accelerator of the one or more accelerators is to accelerate a task associated with media processing ([0079], The application domain hosts application logic 706 that performs service specific tasks (such as a portion of functionality for … facilitating computer vision, facilitating speech translation, etc.)).
The same motivation used in the rejection of claim 7 is applicable to the instant claim.
As per claim 15, the combination of Karoubalis- Kruglick fails to specifically teach, wherein at least one accelerator of the one or more accelerators is to accelerate a task associated with encryption.
However, Chiou teaches, wherein at least one accelerator of the one or more accelerators is to accelerate a task associated with encryption ([0079], The application domain hosts application logic 706 that performs service specific tasks (such as a portion of functionality for … encrypting data)).
The same motivation used in the rejection of claim 7 is applicable to the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is as follows:
Newell et al. (us 20150242620): Teaches implementing dynamic macros as soft microprocessors within an FPGA: ([0018], IP enforcer block 22 may include a ...microprocessor. These may be implemented as ... a soft macro that is programmed into the FPGA fabric 12 using its configuration memory 14).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MELISSA A. HEADLY/
Examiner Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197