Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4-21 are presented for examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/31/25 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, and similarly claims 8, 9, 10, 15, 16, 17, 21, recites the limitation "the BCNT instruction". The antecedent basis for this limitation is unclear. There are multiple previous BCNT instruction limitations (“a plurality of branch-on-count (BCNT) instructions”, “a targeted number of BCNT instructions”, “a number of fetched BCNT instructions”, “a final BCNT instruction”), and it is unclear to which instruction this limitation refers. For the purposes of examination, “the BCNT instruction” will be interpreted as “the final BCNT instruction.”
Claim 9, and similarly claim 16, recites the limitation "the final BCNT instruction". The antecedent basis for this limitation is unclear. There are multiple previous “final BCNT instruction” limitations, and it is unclear to which instruction this limitation refers.
Claims 12, 13, 19, 20 recite the limitation "the given BCNT instruction". There is insufficient antecedent basis for this limitation.
Claim 21 recites the limitation "the BCNT". There is insufficient antecedent basis for this limitation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-21 are rejected under 35 U.S.C. 103 as being unpatentable over Chavan et al., US Patent 11,132,200 (hereinafter Chavan) in view of Gonion, US Patent Application Publication 2012/0166765 (hereinafter Gonion).
Regarding claim 1, Chavan teaches:
A computer processor comprising: an instruction pipeline configured to dispatch a plurality of branch-on-count (BCNT) instructions (see e.g. fig. 2, col. 1 line 41 – col. 2 line 37, loop end instructions); and an instruction fetch unit (IFU) configured to execute an instruction loop for fetching a targeted number of BCNT instructions from the instruction pipeline (see e.g. fig. 2, col. 1 lines 39-49, fetch circuitry), and to monitor a loop counter that counts a number of fetched BCNT instructions that are actually fetched from the instruction pipeline in response to executing the instruction loop (see e.g. fig. 1, col. 1 line 39 – col. 2 line 37, col. 7 lines 1-14, the loop end instructions are counted down by decrementing the loop counter by one for each loop end instruction), wherein when the loop counter reaches zero (see e.g. fig. 5, loop counter is decremented and reaches zero at step 162), the IFU resolves a final BCNT instruction early in the pipeline without waiting for the BCNT instruction to execute (see e.g. fig. 5 steps 160 and 164, col. 7 line 1 – col. 8 line 28, fig. 8, if the loop counter is 0, the loop end instruction is resolved to be not taken without waiting for the instruction to execute).
Chavan fails to explicitly recite resolving so as to perform early flushing and re-direct of a mispredicted branch path.
Gonion teaches that while fetching, upon determining a count reaches a threshold value for a branch instruction, performing early flushing and a re-direct of a mispredicted branch path without waiting for the branch instruction to execute (see e.g. para. [0011], [0015-16], [0122]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Chavan and Gonion to resolve a final BCNT instruction early so as to perform early flushing and re-direct of a mispredicted branch path. This would have provided an advantage of rectifying a misprediction earlier so that instructions could be fetched from the correct location in program code more quickly (see Gonion para. [0122]).
Regarding claim 4, Chavan in view of Gonion teaches or suggests:
The computer processor of claim 1, wherein the IFU comprises: a latch stage configured to monitor the instruction pipeline and identify a plurality of move-to-count register (MTCTR) instructions (see e.g. Gonion para. [0013-14], SegCount instruction); and a BCNT prediction stage configured to monitor the instruction pipeline and associates a fetched BCNT instruction with a given MTCTR register instruction fetched from the pipeline, wherein the MTCTR instructions are utilized to track the fetched BCNT instruction (see e.g. Gonion para. [0013-14]).
Regarding claim 5, Chavan in view of Gonion teaches or suggests:
The computer processor of claim 4, wherein the BCNT prediction stage adjusts the loop counter in response to detecting the given BCNT instruction fetched from the pipeline (see e.g. Chavan col. 1 line 39 – col. 2 line 37, col. 7 line 1 – col. 8 line 28).
Regarding claim 6, Chavan in view of Gonion teaches or suggests:
The computer processor of claim 5, wherein the BCNT prediction stage comprises: the loop counter configured to increment a loop count value in response to detection of the given BCNT instruction fetched from the pipeline (see e.g. Chavan col. 1 line 39 – col. 2 line 37, col. 7 line 1 – col. 8 line 28, a loop counter is incremented to be set; Gonion para. [0014]); and a shadow register configured to receive MTCTR write back data in response to the given MTCTR register instruction executed from the pipeline (see e.g. Chavan col. 7 line 1 – col. 8 line 28; Gonion para. [0014], [0049]).
Regarding claim 7, Chavan in view of Gonion teaches or suggests:
The computer processor of claim 6, wherein the BCNT prediction stage decrements the loop count value in response to storing the MTCTR write back data, and predicts the final BCNT instruction included in the instruction pipeline in response to the loop count value reaching a target loop count value (see e.g. Chavan col. 1 line 39 – col. 2 line 37, col. 7 line 1 – col. 8 line 28, it resolves a final loop end instruction when the count value reaches zero; Gonion para. [0011], [0015-16], [0122]).
Regarding claim 21, Chavan in view of Gonion teaches or suggests:
The computer processor of claim 1, wherein resolving the BCNT without waiting for the BCNT instruction to execute includes causing a branch re-direct without waiting for the BCNT instruction to execute (see e.g. Chavan fig. 5, col. 7 line 1 – col. 8 line 28, if the loop counter is 0, the branch is re-directed to be not taken without waiting for the instruction to execute; Gonion para. [0011], [0015-16], [0122]).
Claims 8-14 are rejected for reasons corresponding to those given above for claims 1, 4-7.
Claims 15-20 are rejected for reasons corresponding to those given above for claims 1, 4-7, 21.
Response to Arguments
Applicant’s amendment has resolved the previous rejections under 35 USC 112(a) and 112(b) regarding a “confirmation” operation.
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183