Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the RCE filed 7/28/2026 in which Claims 1-3, 6-13, 16-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/28/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10, 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 1 objected to because of the following informalities: Line 5 should be “voltage and an output voltage of the electrical module are equal, the electrical module reduces”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 8, 10, 11, 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2022/0091625 to Luo et al (“Luo”).
As to Claim 1, Lee teaches a drive circuit comprising: an electrical module; and an electrical sub-module connected to the electrical module (comparator 210 [electrical sub-module] used in the output node 200 of the AB class buffer amplifier [electrical module] has an offset voltage, see ¶ 0012); wherein, in response to detecting that an input voltage and an output voltage of the electrical module are equal, the electrical module reduces an initial quiescent current of the electrical module to a first quiescent current (The level of the output voltage VOUT becomes equal to the level of the input voltage VIN if the AB class buffer amplifier 700 operates as a buffer. Here, the comparing unit 730 generates the first signal S1 at a level for saturating both the second and fifth transistors MP2 and MN5 in order to reduce the amount of the quiescent current IQ, see ¶ 0194),
Lee does not expressly disclose wherein, in response to detecting a difference between the input voltage and the output voltage of the electrical module, the electrical module increases the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reduces the initial quiescent current of the electrical module to the first quiescent current.
Luo teaches wherein, in response to detecting a difference between the input voltage and the output voltage of the electrical module, the electrical module increases the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reduces the initial quiescent current of the electrical module to the first quiescent current (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). The first maximum voltage 506 may correspond to the maximum voltage (e.g., Vmax of FIG. 3A) outputted by the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; At a first time 516, the second voltage 504 is greater than the first voltage 502, such that magnitudes of the first and second maximum voltages 506, 508 are each equal to the second magnitude 512. At a second time 518 the first voltage 502 is greater than the magnitude of the second voltage 504. In some instances, at a third time 520, the voltage selector circuit (e.g., 350 of FIG. 3A) determines that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the first maximum voltage 506 to the magnitude of the first voltage 502…the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049; the DC-to-DC converter (e.g., 100 of FIG. 1) that utilizes the voltage selector circuit (e.g., 302 of FIG. 3A) having the adaptive current bias generator (e.g., 304 of FIG. 3A or 3B)…In at least one example, between the second time 518 and the third time 520, the second current 526 increases from the first current magnitude 528 to a third current magnitude that is greater than the second current magnitude 530. In at least one example, the second current 526 maintains this higher current from the third time 520 until the fourth time 522, see ¶ 0050; Figure 5 (annotated below) illustrates an increase to a third quiescent current when there is a difference between voltages 502 and 504, the third quiescent current set for a preset period (i.e. second time 520 to fourth time 522) and thereafter, a reduction to a first quiescent current. Examiner construes the initial quiescent current as a value between the third quiescent current and the first quiescent current whether on the upward slope between second time 518 and 520 or on the downward slope at fourth time 522, as according to the Applicant’s disclosure, the third quiescent current is 110% to 150% of the initial quiescent current and the first quiescent current is 30% to 80% of the initial quiescent current. Therefore, it would be reasonable that Luo’s Figure 5 corresponds to the relationship between current values disclosed in the Applicant’s disclosure where third quiescent current is higher than the initial quiescent current which is higher than the first quiescent current).
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Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee with Luo to teach wherein, in response to detecting a difference between the input voltage and the output voltage of the electrical module, the electrical module increases the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reduces the initial quiescent current of the electrical module to the first quiescent current. The suggestion/motivation would have been in order for the adaptive current bias generator generates a bias current for the voltage comparator during a transition from a first state to a second state (see Abstract).
As to Claim 8, Lee and Luo depending from Claim 1, Luo teaches wherein the electrical sub-module comprises a comparator and a control unit, the comparator is configured to compare whether there is the difference between the output voltage and the input voltage of the electrical module or not (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049), the control unit is configured to reduce the initial quiescent current of the electrical module to the first quiescent current, when there is a difference between the input voltage and the output voltage of the electrical module (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; At a first time 516, the second voltage 504 is greater than the first voltage 502, such that magnitudes of the first and second maximum voltages 506, 508 are each equal to the second magnitude 512. At a second time 518 the first voltage 502 is greater than the magnitude of the second voltage 504. In some instances, at a third time 520, the voltage selector circuit (e.g., 350 of FIG. 3A) determines that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the first maximum voltage 506 to the magnitude of the first voltage 502…the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049; the DC-to-DC converter (e.g., 100 of FIG. 1) that utilizes the voltage selector circuit (e.g., 302 of FIG. 3A) having the adaptive current bias generator (e.g., 304 of FIG. 3A or 3B)…In at least one example, between the second time 518 and the third time 520, the second current 526 increases from the first current magnitude 528 to a third current magnitude that is greater than the second current magnitude 530. In at least one example, the second current 526 maintains this higher current from the third time 520 until the fourth time 522, see ¶ 0050; Figure 5 (annotated above) illustrates a reduction from initial quiescent current to a first quiescent current when there is a difference between voltages 502 and 504 (i.e. fourth time 522 onward). Examiner construes the initial quiescent current as a value between the third quiescent current and the first quiescent current on the downward slope at fourth time 522, as according to the Applicant’s disclosure, the third quiescent current is 110% to 150% of the initial quiescent current and the first quiescent current is 30% to 80% of the initial quiescent current. Therefore, it would be reasonable that Luo’s Figure 5 corresponds to the relationship between current values disclosed in the Applicant’s disclosure where third quiescent current is higher than the initial quiescent current which is higher than the first quiescent current).
Luo teaches the control unit is configured to control to increase the initial quiescent current of the electrical module to the third quiescent current for a preset time period and then reduce the initial quiescent current of the electrical module to the first quiescent current (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). The first maximum voltage 506 may correspond to the maximum voltage (e.g., Vmax of FIG. 3A) outputted by the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049; the DC-to-DC converter (e.g., 100 of FIG. 1) that utilizes the voltage selector circuit (e.g., 302 of FIG. 3A) having the adaptive current bias generator (e.g., 304 of FIG. 3A or 3B)…In at least one example, between the second time 518 and the third time 520, the second current 526 increases from the first current magnitude 528 to a third current magnitude that is greater than the second current magnitude 530. In at least one example, the second current 526 maintains this higher current from the third time 520 until the fourth time 522, see ¶ 0050; Figure 5 (annotated below) illustrates an increase to a third quiescent current when there is a difference between voltages 502 and 504, the third quiescent current set for a preset period (i.e. second time 520 to fourth time 522) and thereafter, a reduction to a first quiescent current. Examiner construes the initial quiescent current as a value between the third quiescent current and the first quiescent current whether on the upward slope between second time 518 and 520 or on the downward slope at fourth time 522, as according to the Applicant’s disclosure, the third quiescent current is 110% to 150% of the initial quiescent current and the first quiescent current is 30% to 80% of the initial quiescent current. Therefore, it would be reasonable that Luo’s Figure 5 corresponds to the relationship between current values disclosed in the Applicant’s disclosure where third quiescent current is higher than the initial quiescent current which is higher than the first quiescent current).
As to Claim 10, Lee teaches a data-driven method comprising: in response to detecting that the input voltage and the output voltage of the electrical module are equal, reducing an initial quiescent current of the electrical module to a first quiescent current (The level of the output voltage VOUT becomes equal to the level of the input voltage VIN if the AB class buffer amplifier 700 operates as a buffer. Here, the comparing unit 730 generates the first signal S1 at a level for saturating both the second and fifth transistors MP2 and MN5 in order to reduce the amount of the quiescent current IQ, see ¶ 0194),
Lee does not expressly disclose detecting whether there is the difference between the output voltage and the input voltage of the electrical module or not; in response to detecting a difference between the input voltage and the output voltage of the electrical module, increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reducing the initial quiescent current of the electrical module to the first quiescent current.
Luo teaches detecting whether there is the difference between the output voltage and the input voltage of the electrical module or not (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049);
in response to detecting a difference between the input voltage and the output voltage of the electrical module, increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reducing the initial quiescent current of the electrical module to the first quiescent current (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). The first maximum voltage 506 may correspond to the maximum voltage (e.g., Vmax of FIG. 3A) outputted by the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; At a first time 516, the second voltage 504 is greater than the first voltage 502, such that magnitudes of the first and second maximum voltages 506, 508 are each equal to the second magnitude 512. At a second time 518 the first voltage 502 is greater than the magnitude of the second voltage 504. In some instances, at a third time 520, the voltage selector circuit (e.g., 350 of FIG. 3A) determines that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the first maximum voltage 506 to the magnitude of the first voltage 502…the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049; the DC-to-DC converter (e.g., 100 of FIG. 1) that utilizes the voltage selector circuit (e.g., 302 of FIG. 3A) having the adaptive current bias generator (e.g., 304 of FIG. 3A or 3B)…In at least one example, between the second time 518 and the third time 520, the second current 526 increases from the first current magnitude 528 to a third current magnitude that is greater than the second current magnitude 530. In at least one example, the second current 526 maintains this higher current from the third time 520 until the fourth time 522, see ¶ 0050; Figure 5 (annotated below) illustrates an increase to a third quiescent current when there is a difference between voltages 502 and 504, the third quiescent current set for a preset period (i.e. second time 520 to fourth time 522) and thereafter, a reduction to a first quiescent current. Examiner construes the initial quiescent current as a value between the third quiescent current and the first quiescent current whether on the upward slope between second time 518 and 520 or on the downward slope at fourth time 522, as according to the Applicant’s disclosure, the third quiescent current is 110% to 150% of the initial quiescent current and the first quiescent current is 30% to 80% of the initial quiescent current. Therefore, it would be reasonable that Luo’s Figure 5 corresponds to the relationship between current values disclosed in the Applicant’s disclosure where third quiescent current is higher than the initial quiescent current which is higher than the first quiescent current).
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Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee with Luo to teach in response to detecting a difference between the input voltage and the output voltage of the electrical module, increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reducing the initial quiescent current of the electrical module to the first quiescent current. The suggestion/motivation would have been in order for the bias voltage to be based at least on a bias current (see ¶ 0055).
As to Claim 11, Lee teaches a display panel, comprising a pixel and a drive circuit to drive the pixel, the drive circuit comprising: an electrical module; and an electrical sub-module connected to the electrical module (comparator 210 [electrical sub-module] used in the output node 200 of the AB class buffer amplifier [electrical module] has an offset voltage, see ¶ 0012); wherein, in response to detecting that an input voltage and an output voltage of the electrical module are equal, the electrical module reduces an initial quiescent current of the electrical module to a first quiescent current (The level of the output voltage VOUT becomes equal to the level of the input voltage VIN if the AB class buffer amplifier 700 operates as a buffer. Here, the comparing unit 730 generates the first signal S1 at a level for saturating both the second and fifth transistors MP2 and MN5 in order to reduce the amount of the quiescent current IQ, see ¶ 0194),
Lee does not expressly disclose wherein, in response to detecting a difference between the input voltage and the output voltage of the electrical module, the electrical module increases the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reduces the initial quiescent current of the electrical module to the first quiescent current.
Luo teaches wherein, in response to detecting a difference between the input voltage and the output voltage of the electrical module, the electrical module increases the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reduces the initial quiescent current of the electrical module to the first quiescent current (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). The first maximum voltage 506 may correspond to the maximum voltage (e.g., Vmax of FIG. 3A) outputted by the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; At a first time 516, the second voltage 504 is greater than the first voltage 502, such that magnitudes of the first and second maximum voltages 506, 508 are each equal to the second magnitude 512. At a second time 518 the first voltage 502 is greater than the magnitude of the second voltage 504. In some instances, at a third time 520, the voltage selector circuit (e.g., 350 of FIG. 3A) determines that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the first maximum voltage 506 to the magnitude of the first voltage 502…the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049; the DC-to-DC converter (e.g., 100 of FIG. 1) that utilizes the voltage selector circuit (e.g., 302 of FIG. 3A) having the adaptive current bias generator (e.g., 304 of FIG. 3A or 3B)…In at least one example, between the second time 518 and the third time 520, the second current 526 increases from the first current magnitude 528 to a third current magnitude that is greater than the second current magnitude 530. In at least one example, the second current 526 maintains this higher current from the third time 520 until the fourth time 522, see ¶ 0050; Figure 5 (annotated below) illustrates an increase to a third quiescent current when there is a difference between voltages 502 and 504, the third quiescent current set for a preset period (i.e. second time 520 to fourth time 522) and thereafter, a reduction to a first quiescent current. Examiner construes the initial quiescent current as a value between the third quiescent current and the first quiescent current whether on the upward slope between second time 518 and 520 or on the downward slope at fourth time 522, as according to the Applicant’s disclosure, the third quiescent current is 110% to 150% of the initial quiescent current and the first quiescent current is 30% to 80% of the initial quiescent current. Therefore, it would be reasonable that Luo’s Figure 5 corresponds to the relationship between current values disclosed in the Applicant’s disclosure where third quiescent current is higher than the initial quiescent current which is higher than the first quiescent current).
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Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee with Luo to teach wherein, in response to detecting a difference between the input voltage and the output voltage of the electrical module, the electrical module increases the initial quiescent current of the electrical module to a third quiescent current for a preset time period and thereafter reduces the initial quiescent current of the electrical module to the first quiescent current. The suggestion/motivation would have been in order for the adaptive current bias generator generates a bias current for the voltage comparator during a transition from a first state to a second state (see Abstract).
As to Claim 19, Lee and Luo depending from Claim 11, Luo teaches wherein the electrical sub-module comprises a comparator and a control unit, the comparator is configured to compare whether there is the difference between the output voltage and the input voltage of the electrical module or not (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049), the control unit is configured to reduce the initial quiescent current of the electrical module to the first quiescent current, when there is a difference between the input voltage and the output voltage of the electrical module (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; At a first time 516, the second voltage 504 is greater than the first voltage 502, such that magnitudes of the first and second maximum voltages 506, 508 are each equal to the second magnitude 512. At a second time 518 the first voltage 502 is greater than the magnitude of the second voltage 504. In some instances, at a third time 520, the voltage selector circuit (e.g., 350 of FIG. 3A) determines that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the first maximum voltage 506 to the magnitude of the first voltage 502…the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049; the DC-to-DC converter (e.g., 100 of FIG. 1) that utilizes the voltage selector circuit (e.g., 302 of FIG. 3A) having the adaptive current bias generator (e.g., 304 of FIG. 3A or 3B)…In at least one example, between the second time 518 and the third time 520, the second current 526 increases from the first current magnitude 528 to a third current magnitude that is greater than the second current magnitude 530. In at least one example, the second current 526 maintains this higher current from the third time 520 until the fourth time 522, see ¶ 0050; Figure 5 (annotated above) illustrates a reduction from initial quiescent current to a first quiescent current when there is a difference between voltages 502 and 504 (i.e. fourth time 522 onward). Examiner construes the initial quiescent current as a value between the third quiescent current and the first quiescent current on the downward slope at fourth time 522, as according to the Applicant’s disclosure, the third quiescent current is 110% to 150% of the initial quiescent current and the first quiescent current is 30% to 80% of the initial quiescent current. Therefore, it would be reasonable that Luo’s Figure 5 corresponds to the relationship between current values disclosed in the Applicant’s disclosure where third quiescent current is higher than the initial quiescent current which is higher than the first quiescent current).
Luo teaches the control unit is configured to control to increase the initial quiescent current of the electrical module to the third quiescent current for a preset time period and then reduce the initial quiescent current of the electrical module to the first quiescent current (the first voltage 502 may correspond to the input voltage (e.g., V1 of FIG. 3A) of a DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). Further, the second voltage 504 may correspond to the output voltage (e.g., V2 of FIG. 3A) of the DC-to-DC converter (e.g., 100 of FIG. 1) and may be provided to an input of the voltage selector circuit (e.g., 350 of FIG. 3A). The first maximum voltage 506 may correspond to the maximum voltage (e.g., Vmax of FIG. 3A) outputted by the voltage selector circuit (e.g., 350 of FIG. 3A), see ¶ 0048; the another voltage selector circuit (not shown) that does not comprise an adaptive current bias generator may determine, at a fourth time 522, that the first voltage 502 is greater than the magnitude of the second voltage 504 and sets the second maximum voltage 508 to the magnitude of the first voltage 502, see ¶ 0049; the DC-to-DC converter (e.g., 100 of FIG. 1) that utilizes the voltage selector circuit (e.g., 302 of FIG. 3A) having the adaptive current bias generator (e.g., 304 of FIG. 3A or 3B)…In at least one example, between the second time 518 and the third time 520, the second current 526 increases from the first current magnitude 528 to a third current magnitude that is greater than the second current magnitude 530. In at least one example, the second current 526 maintains this higher current from the third time 520 until the fourth time 522, see ¶ 0050; Figure 5 (annotated below) illustrates an increase to a third quiescent current when there is a difference between voltages 502 and 504, the third quiescent current set for a preset period (i.e. second time 520 to fourth time 522) and thereafter, a reduction to a first quiescent current. Examiner construes the initial quiescent current as a value between the third quiescent current and the first quiescent current whether on the upward slope between second time 518 and 520 or on the downward slope at fourth time 522, as according to the Applicant’s disclosure, the third quiescent current is 110% to 150% of the initial quiescent current and the first quiescent current is 30% to 80% of the initial quiescent current. Therefore, it would be reasonable that Luo’s Figure 5 corresponds to the relationship between current values disclosed in the Applicant’s disclosure where third quiescent current is higher than the initial quiescent current which is higher than the first quiescent current).
Claim(s) 2, 3, 12, 13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2022/0091625 to Luo et al (“Luo”) in further view of Japanese Patent Publication JPH09219636 to Nakao et al (“Nakao”).
As to Claim 2, Lee and Luo depending from Claim 1, Lee and Luo do not expressly disclose the initial quiescent current of the electrical module is reduced to a first quiescent current, the first quiescent current is 30% to 80% of the initial quiescent current. Nakao teaches the first quiescent current is 30% to 80% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Luo with Nakao to teach the first quiescent current is 30% to 80% of the initial quiescent current. The suggestion/motivation would have been in order to realize output current control (see ¶ 0077).
As to Claim 3, Lee, Luo and Nakao depending from Claim 2, Nakao teaches wherein the first quiescent current is 50% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
As to Claim 12, Lee and Luo depending from Claim 11, Lee and Luo do not expressly disclose wherein when the input voltage and the output voltage of the electrical module are equal, the initial quiescent current of the electrical module is reduced to a first quiescent current, the first quiescent current is 30% to 80% of the initial quiescent current. Nakao teaches the first quiescent current is 30% to 80% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Luo with Nakao to teach the first quiescent current is 30% to 80% of the initial quiescent current. The suggestion/motivation would have been in order to realize output current control (see ¶ 0077).
As to Claim 13, Lee, Luo and Nakao depending from Claim 12, Nakao teaches wherein the first quiescent current is 50% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Claim(s) 6, 16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2022/0091625 to Luo et al (“Luo”) in further view of U.S. Patent Publication 2022/0335871 to Lee et al (“Lee 2”) and in further view of Japanese Patent Publication JPH09219636 to Nakao et al (“Nakao”).
As to Claim 6, Lee and Luo depending from Claim 1, Lee and Luo do not expressly disclose the third quiescent current is 110% to 150% of the initial quiescent current. Lee 2 teaches the third quiescent current is 110% to 150% of the initial quiescent current (The first current may quickly increase to the maximum current value IMAX in a very short first period between the first time point t1 and the second time point t2. The maximum current value IMAX may be again multiplied by K times and it may be provided to the output terminal OUT as the first auxiliary current Ix. Accordingly, the slew rate of the rising edge of the output signal VOUT may increase, see ¶ 0153; The third current I3 may rise to IMAX/b by the current mirror, see ¶ 0155).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Luo with Lee 2 to teach the initial quiescent current of the electrical module is reduced to the first quiescent current after the initial quiescent current of the electrical module is increased to a third quiescent current for the preset time period, the third quiescent current is 110% to 150% of the initial quiescent current.
Lee, Luo and Lee 2 do not expressly disclose wherein when there is the difference between the input voltage and the output voltage of the electrical module, the first quiescent current is 30% to 80% of the initial quiescent current.
Nakao teaches wherein the first quiescent current is 30% to 80% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Luo and Lee 2 with Nakao to teach wherein the first quiescent current is 30% to 80% of the initial quiescent current. The suggestion/motivation would have been in order to realize output current control (see ¶ 0077).
As to Claim 16, Lee and Luo depending from Claim 11, Lee and Luo do not expressly disclose the third quiescent current is 110% to 150% of the initial quiescent current. Lee 2 teaches the third quiescent current is 110% to 150% of the initial quiescent current (The first current may quickly increase to the maximum current value IMAX in a very short first period between the first time point t1 and the second time point t2. The maximum current value IMAX may be again multiplied by K times and it may be provided to the output terminal OUT as the first auxiliary current Ix. Accordingly, the slew rate of the rising edge of the output signal VOUT may increase, see ¶ 0153; The third current I3 may rise to IMAX/b by the current mirror, see ¶ 0155).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Luo with Lee 2 to teach the initial quiescent current of the electrical module is reduced to the first quiescent current after the initial quiescent current of the electrical module is increased to a third quiescent current for the preset time period, the third quiescent current is 110% to 150% of the initial quiescent current.
Lee, Luo and Lee 2 do not expressly disclose wherein when there is the difference between the input voltage and the output voltage of the electrical module, the first quiescent current is 30% to 80% of the initial quiescent current.
Nakao teaches wherein the first quiescent current is 30% to 80% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Luo and Lee 2 with Nakao to teach wherein the first quiescent current is 30% to 80% of the initial quiescent current. The suggestion/motivation would have been in order to realize output current control (see ¶ 0077).
Claim(s) 7, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2022/0091625 to Luo et al (“Luo”) in further view of U.S. Patent Publication 2006/0145749 to Bhattacharya et al (“Bhattacharya”).
As to Claim 7, Lee and Luo depending from Claim 1, Lee and Luo do not expressly disclose wherein the preset time period is from 0.5µs to 2µs. Bhattacharya teaches wherein the preset time period is from 0.5µs to 2µs (shunt circuit is configured to provide a source of current to assist in charging the output of the reference generator to a quiescent operating level during the second mode of operation. The shunt circuit, in response to a second control signal applied thereto, is operable for a selected period time after the reference generator transitions from the first mode of operation to the second mode of operation, see Abstract; the bias circuit includes a shunt circuit which is only operable for a brief period of time (e.g., less than about one microsecond), so as to assist in charging an output of the bias circuit to its steady state value during a normal operating mode, see ¶ 0007).
Before the effective filing date of the claimed invention, it would have been in order to modify Lee and Luo with Bhattacharya to teach wherein the preset time period is from 0.5µs to 2µs. The suggestion/motivation would have been in order to reduce current consumption in a bias circuit (see ¶ 0007).
As to Claim 17, Lee and Luo depending from Claim 11, Lee and Luo do not expressly disclose wherein the preset time period is from 0.5µs to 2µs. Bhattacharya teaches wherein the preset time period is from 0.5µs to 2µs (shunt circuit is configured to provide a source of current to assist in charging the output of the reference generator to a quiescent operating level during the second mode of operation. The shunt circuit, in response to a second control signal applied thereto, is operable for a selected period time after the reference generator transitions from the first mode of operation to the second mode of operation, see Abstract; the bias circuit includes a shunt circuit which is only operable for a brief period of time (e.g., less than about one microsecond), so as to assist in charging an output of the bias circuit to its steady state value during a normal operating mode, see ¶ 0007).
Before the effective filing date of the claimed invention, it would have been in order to modify Lee and Luo with Bhattacharya to teach wherein the preset time period is from 0.5µs to 2µs. The suggestion/motivation would have been in order to reduce current consumption in a bias circuit (see ¶ 0007).
As to Claim 18, Lee and Luo depending from Claim 11, Lee and Luo do not expressly disclose wherein the preset time period is from 1µs to 1.5µs. Bhattacharya teaches wherein the preset time period is from 1 s to 1.5 s (Figure 5 illustrates a t1 – t2 interval [preset time period] between 0 and 200 ns in the sixth chart that would fall between 1 and 1.5 microseconds).
Before the effective filing date of the claimed invention, it would have been in order to modify Lee and Luo with Bhattacharya to teach wherein the preset time period is from 1µs to 1.5µs. The suggestion/motivation would have been in order to reduce current consumption in a bias circuit (see ¶ 0007).
Claim(s) 9, 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2022/0091625 to Luo et al (“Luo”) in further view of U.S. Patent Publication 2012/0249245 to Chen et al (“Chen”) and in further view of U.S. Patent Publication 2021/0183320 to Lee et al (“Lee 3”).
As to Claim 9, Lee and Luo depends from Claim 1, Lee and Luo do not expressly disclose wherein the drive circuit comprises an interface receiving module, a data shift module, a data register module, a data latch module, a level conversion module and a digital/analog conversion module, output terminals of the interface receiving module and the data shift module are connected to an input terminal of the data register module, an output terminal of the data register module is connected to an input terminal of the data latch module, an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module, an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module, an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module. Chen teaches wherein the drive circuit comprises an interface receiving module (receiver 10, Fig. 1), a data shift module (shift register 14, Fig. 1), a data register module (data register 12, Fig. 1), a data latch module (line latch 16, Fig. 1), a level conversion module (level shifter 18, Fig. 1) and a digital/analog conversion module (digital-to-analog converter 20, Fig. 1), output terminals of the interface receiving module are connected to an input terminal of the data register module (receiver 10 is coupled to the data register 12, see ¶ 0019; Figure 1 illustrates outputs of the receiver 10 connected to the data register 12), an output terminal of the data register module is connected to an input terminal of the data latch module (the data register 12 is coupled to the line latch 16, see ¶ 0019, Fig. 1), an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module (the line latch 16 is coupled to the level shifter 18, see ¶ 0019, Fig. 1), an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module (the level shifter 18 is coupled to the digital-to-analog converter 20, see ¶ 0019, Fig. 1), an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module (the digital-to-analog converter 20 is coupled to the output buffer 22, see ¶ 0019, Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Luo with Chen to teach wherein the drive circuit comprises an interface receiving module, a data shift module, a data register module, a data latch module, a level conversion module and a digital/analog conversion module, output terminals of the interface receiving module and the data shift module are connected to an input terminal of the data register module, an output terminal of the data register module is connected to an input terminal of the data latch module, an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module, an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module, an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module. The suggestion/motivation would have been in order to enhance the slew rate of the output buffer (see Abstract).
Lee, Luo and Chen do not expressly disclose output terminals of the data shift module are connected to an input terminal of the data register module.
Lee 3 teaches output terminals of the interface receiving module and data shift module are connected to an input terminal of the data register module (the data controller 131 [interface receiving module] transmits the digital image data DATA stored in the lookup table to the first latch circuit 135A [data register module], see ¶ 0154; The shift register 134 [data shift module] generates a first latch enable signal 1st LEN for operating the first latch circuit 135A [data register module], see ¶ 0155).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Luo and Chen with Lee 3 to teach output terminals of the data shift module are connected to an input terminal of the data register module. The suggestion/motivation would have been in order for a first latch circuit that stores the digital image data and offset image data received from the data controller (see ¶ 0023).
As to Claim 20, Lee and Luo depends from Claim 11, Lee and Luo do not expressly disclose wherein the drive circuit comprises an interface receiving module, a data shift module, a data register module, a data latch module, a level conversion module and a digital/analog conversion module, output terminals of the interface receiving module and the data shift module are connected to an input terminal of the data register module, an output terminal of the data register module is connected to an input terminal of the data latch module, an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module, an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module, an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module. Chen teaches wherein the drive circuit comprises an interface receiving module (receiver 10, Fig. 1), a data shift module (shift register 14, Fig. 1), a data register module (data register 12, Fig. 1), a data latch module (line latch 16, Fig. 1), a level conversion module (level shifter 18, Fig. 1) and a digital/analog conversion module (digital-to-analog converter 20, Fig. 1), output terminals of the interface receiving module are connected to an input terminal of the data register module (receiver 10 is coupled to the data register 12, see ¶ 0019; Figure 1 illustrates outputs of the receiver 10 connected to the data register 12), an output terminal of the data register module is connected to an input terminal of the data latch module (the data register 12 is coupled to the line latch 16, see ¶ 0019, Fig. 1), an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module (the line latch 16 is coupled to the level shifter 18, see ¶ 0019, Fig. 1), an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module (the level shifter 18 is coupled to the digital-to-analog converter 20, see ¶ 0019, Fig. 1), an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module (the digital-to-analog converter 20 is coupled to the output buffer 22, see ¶ 0019, Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Luo with Chen to teach wherein the drive circuit comprises an interface receiving module, a data shift module, a data register module, a data latch module, a level conversion module and a digital/analog conversion module, output terminals of the interface receiving module and the data shift module are connected to an input terminal of the data register module, an output terminal of the data register module is connected to an input terminal of the data latch module, an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module, an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module, an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module. The suggestion/motivation would have been in order to enhance the slew rate of the output buffer (see Abstract).
Lee, Luo and Chen do not expressly disclose output terminals of the data shift module are connected to an input terminal of the data register module.
Lee 3 teaches output terminals of the interface receiving module and data shift module are connected to an input terminal of the data register module (the data controller 131 [interface receiving module] transmits the digital image data DATA stored in the lookup table to the first latch circuit 135A [data register module], see ¶ 0154; The shift register 134 [data shift module] generates a first latch enable signal 1st LEN for operating the first latch circuit 135A [data register module], see ¶ 0155).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Luo and Chen with Lee 3 to teach output terminals of the data shift module are connected to an input terminal of the data register module. The suggestion/motivation would have been in order for a first latch circuit that stores the digital image data and offset image data received from the data controller (see ¶ 0023).
Conclusion
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/EBONI N GILES/ Examiner, Art Unit 2622
/PATRICK N EDOUARD/ Supervisory Patent Examiner, Art Unit 2622
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