Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the amendment filed 12/24/2025 in which Claims 1-3, 6-13, 16-20 are pending and Claims 4-5, 14-15 are canceled.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10, 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2019/0172505 to Asaki et al (“Asaki”) in further view of U.S. Patent 8,970,199 to Scoones et al (“Scoones”).
As to Claim 1, Lee teaches a drive circuit comprising: an electrical module; and an electrical sub-module connected to the electrical module (comparator 210 [electrical sub-module] used in the output node 200 of the AB class buffer amplifier [electrical module] has an offset voltage, see ¶ 0012); wherein when the electrical sub-module detects that an input voltage and an output voltage of the electrical module are equal, an initial quiescent current of the electrical module is reduced to a first quiescent current (The level of the output voltage VOUT becomes equal to the level of the input voltage VIN if the AB class buffer amplifier 700 operates as a buffer. Here, the comparing unit 730 generates the first signal S1 at a level for saturating both the second and fifth transistors MP2 and MN5 in order to reduce the amount of the quiescent current IQ, see ¶ 0194),
Lee does not expressly disclose when there is a difference between the input voltage and the output voltage of the electrical module, the initial quiescent current of the electrical module is reduced to the first quiescent current after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period.
Asaki teaches when there is a difference between the input voltage and the output voltage of the electrical module, the initial quiescent current of the electrical module is reduced to the first quiescent current (an example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value, see Abstract; the bias circuit 410 provides a decreasing IBIAS current for an increasing supply voltage [difference between input voltage and output voltage, reduces the initial quiescent current to the first quiescent current], see ¶ 0045; Figures 5 & 6b illustrate the input voltage at node 26 is lower than the output voltage VDD2 when the IBIAS decreases).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee with Asaki to teach when there is a difference between the input voltage and the output voltage of the electrical module, the initial quiescent current of the electrical module is reduced. The suggestion/motivation would have been in order for the bias voltage to be based at least on a bias current (see ¶ 0055).
Lee and Asaki do not expressly disclose the initial quiescent current of the electrical module is reduced to the first quiescent current, after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period.
Scoones teaches the initial quiescent current of the electrical module is reduced to the first quiescent current, after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period (the bias current IBIAS starts at time TX with a maximum magnitude IMAX and falls gradually with a falling slope DNSL until the minimum bias current magnitude IMIN is reached, see Col. 6, lines 14-20; Figure 3 illustrates an IBIAS increasing to an IMAX value for a time period and after said time period, decreasing to an IMIN value).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Asaki with Scoones to teach the initial quiescent current of the electrical module is reduced to the first quiescent current, after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period. The suggestion/motivation would have been in order for the electronic device to provide a quick response for a change from low loads to high loads (see Col. 2, lines 16-18).
As to Claim 11, Lee teaches a display panel, comprising a pixel and a drive circuit to drive the pixel, the drive circuit comprising: an electrical module; and an electrical sub-module connected to the electrical module (comparator 210 [electrical sub-module] used in the output node 200 of the AB class buffer amplifier [electrical module] has an offset voltage, see ¶ 0012); wherein when the electrical sub-module detects that an input voltage and an output voltage of the electrical module are equal, an initial quiescent current of the electrical module is reduced (The level of the output voltage VOUT becomes equal to the level of the input voltage VIN if the AB class buffer amplifier 700 operates as a buffer. Here, the comparing unit 730 generates the first signal S1 at a level for saturating both the second and fifth transistors MP2 and MN5 in order to reduce the amount of the quiescent current IQ, see ¶ 0194),
Lee does not expressly disclose when there is a difference between the input voltage and the output voltage of the electrical module, the initial quiescent current of the electrical module is reduced to the first quiescent current after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period.
Asaki teaches when there is a difference between the input voltage and the output voltage of the electrical module, the initial quiescent current of the electrical module is reduced to the first quiescent current (an example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value, see Abstract; the bias circuit 410 provides a decreasing IBIAS current for an increasing supply voltage [difference between input voltage and output voltage, reduces the initial quiescent current to the first quiescent current], see ¶ 0045; Figures 5 & 6b illustrate the input voltage at node 26 is lower than the output voltage VDD2 when the IBIAS decreases).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee with Asaki to teach when there is a difference between the input voltage and the output voltage of the electrical module, the initial quiescent current of the electrical module is reduced. The suggestion/motivation would have been in order for the bias voltage to be based at least on a bias current (see ¶ 0055).
Lee and Asaki do not expressly disclose the initial quiescent current of the electrical module is reduced to the first quiescent current, after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period.
Scoones teaches the initial quiescent current of the electrical module is reduced to the first quiescent current, after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period (the bias current IBIAS starts at time TX with a maximum magnitude IMAX and falls gradually with a falling slope DNSL until the minimum bias current magnitude IMIN is reached, see Col. 6, lines 14-20; Figure 3 illustrates an IBIAS increasing to an IMAX value for a time period and after said time period, decreasing to an IMIN value).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Asaki with Scoones to teach the initial quiescent current of the electrical module is reduced to the first quiescent current, after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period. The suggestion/motivation would have been in order for the electronic device to provide a quick response for a change from low loads to high loads (see Col. 2, lines 16-18).
Claim(s) 2, 3, 12, 13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2019/0172505 to Asaki et al (“Asaki”) in further view of U.S. Patent 8,970,199 to Scoones et al (“Scoones”) and in further view of Japanese Patent Publication JPH09219636 to Nakao et al (“Nakao”).
As to Claim 2, Lee, Asaki and Scoones depending from Claim 1, Lee, Asaki and Scoones do not expressly disclose the initial quiescent current of the electrical module is reduced to a first quiescent current, the first quiescent current is 30% to 80% of the initial quiescent current. Nakao teaches the first quiescent current is 30% to 80% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Nakao to teach the first quiescent current is 30% to 80% of the initial quiescent current. The suggestion/motivation would have been in order to realize output current control (see ¶ 0077).
As to Claim 3, Lee, Asaki, Scoones and Nakao depending from Claim 2, Nakao teaches wherein the first quiescent current is 50% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
As to Claim 12, Lee, Asaki and Scoones depending from Claim 11, Lee, Asaki and Scoones do not expressly disclose wherein when the input voltage and the output voltage of the electrical module are equal, the initial quiescent current of the electrical module is reduced to a first quiescent current, the first quiescent current is 30% to 80% of the initial quiescent current. Nakao teaches the first quiescent current is 30% to 80% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Nakao to teach the first quiescent current is 30% to 80% of the initial quiescent current. The suggestion/motivation would have been in order to realize output current control (see ¶ 0077).
As to Claim 13, Lee, Asaki, Scoones and Nakao depending from Claim 12, Nakao teaches wherein the first quiescent current is 50% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Claim(s) 6, 16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2019/0172505 to Asaki et al (“Asaki”) in further view of U.S. Patent 8,970,199 to Scoones et al (“Scoones”) in further view of U.S. Patent Publication 2022/0335871 to Lee et al (“Lee 2”) and in further view of Japanese Patent Publication JPH09219636 to Nakao et al (“Nakao”).
As to Claim 6, Lee, Asaki and Scoones depending from Claim 1, Lee, Asaki and Scoones do not expressly disclose the third quiescent current is 110% to 150% of the initial quiescent current. Lee 2 teaches the third quiescent current is 110% to 150% of the initial quiescent current (The first current may quickly increase to the maximum current value IMAX in a very short first period between the first time point t1 and the second time point t2. The maximum current value IMAX may be again multiplied by K times and it may be provided to the output terminal OUT as the first auxiliary current Ix. Accordingly, the slew rate of the rising edge of the output signal VOUT may increase, see ¶ 0153; The third current I3 may rise to IMAX/b by the current mirror, see ¶ 0155).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Lee 2 to teach the initial quiescent current of the electrical module is reduced to the first quiescent current after the initial quiescent current of the electrical module is increased to a third quiescent current for the preset time period, the third quiescent current is 110% to 150% of the initial quiescent current.
Lee, Asaki, Scoones and Lee 2 do not expressly disclose wherein when there is the difference between the input voltage and the output voltage of the electrical module, the first quiescent current is 30% to 80% of the initial quiescent current.
Nakao teaches wherein the first quiescent current is 30% to 80% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki, Scoones and Lee 2 with Nakao to teach wherein the first quiescent current is 30% to 80% of the initial quiescent current. The suggestion/motivation would have been in order to realize output current control (see ¶ 0077).
As to Claim 16, Lee, Asaki and Scoones depending from Claim 11, Lee, Asaki and Scoones do not expressly disclose the third quiescent current is 110% to 150% of the initial quiescent current. Lee 2 teaches the third quiescent current is 110% to 150% of the initial quiescent current (The first current may quickly increase to the maximum current value IMAX in a very short first period between the first time point t1 and the second time point t2. The maximum current value IMAX may be again multiplied by K times and it may be provided to the output terminal OUT as the first auxiliary current Ix. Accordingly, the slew rate of the rising edge of the output signal VOUT may increase, see ¶ 0153; The third current I3 may rise to IMAX/b by the current mirror, see ¶ 0155).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Lee 2 to teach the initial quiescent current of the electrical module is reduced to the first quiescent current after the initial quiescent current of the electrical module is increased to a third quiescent current for the preset time period, the third quiescent current is 110% to 150% of the initial quiescent current.
Lee, Asaki, Scoones and Lee 2 do not expressly disclose wherein when there is the difference between the input voltage and the output voltage of the electrical module, the first quiescent current is 30% to 80% of the initial quiescent current.
Nakao teaches wherein the first quiescent current is 30% to 80% of the initial quiescent current (when the non-inverting input voltage VIA and the inverting input voltage VIB are in a substantially equal balanced state, the current flowing through the transistors N1 and N2 is I1=I1a because transistors P1 and P2 constitute a current mirror circuit, see ¶ 0079; since the current flowing through the differential amplifier circuit 52 is given as I3 = 2.5µA, the currents respectively supplied from transistors P1 and P2 at the time of equilibrium are I1a = I2A = I3/2 = 1.25 µA, see ¶ 0086. I1 is 50% of the initial quiescent current I3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki, Scoones and Lee 2 with Nakao to teach wherein the first quiescent current is 30% to 80% of the initial quiescent current. The suggestion/motivation would have been in order to realize output current control (see ¶ 0077).
Claim(s) 7, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2019/0172505 to Asaki et al (“Asaki”) in further view of U.S. Patent 8,970,199 to Scoones et al (“Scoones”) and in further view of U.S. Patent Publication 2006/0145749 to Bhattacharya et al (“Bhattacharya”).
As to Claim 7, Lee, Asaki and Scoones depending from Claim 1, Lee, Asaki and Scoones do not expressly disclose wherein the preset time period is from 0.5µs to 2µs. Bhattacharya teaches wherein the preset time period is from 0.5µs to 2µs (shunt circuit is configured to provide a source of current to assist in charging the output of the reference generator to a quiescent operating level during the second mode of operation. The shunt circuit, in response to a second control signal applied thereto, is operable for a selected period time after the reference generator transitions from the first mode of operation to the second mode of operation, see Abstract; the bias circuit includes a shunt circuit which is only operable for a brief period of time (e.g., less than about one microsecond), so as to assist in charging an output of the bias circuit to its steady state value during a normal operating mode, see ¶ 0007).
Before the effective filing date of the claimed invention, it would have been in order to modify Lee, Asaki and Scoones with Bhattacharya to teach wherein the preset time period is from 0.5µs to 2µs. The suggestion/motivation would have been in order to reduce current consumption in a bias circuit (see ¶ 0007).
As to Claim 17, Lee, Asaki and Scoones depending from Claim 11, Lee, Asaki and Scoones do not expressly disclose wherein the preset time period is from 0.5µs to 2µs. Bhattacharya teaches wherein the preset time period is from 0.5µs to 2µs (shunt circuit is configured to provide a source of current to assist in charging the output of the reference generator to a quiescent operating level during the second mode of operation. The shunt circuit, in response to a second control signal applied thereto, is operable for a selected period time after the reference generator transitions from the first mode of operation to the second mode of operation, see Abstract; the bias circuit includes a shunt circuit which is only operable for a brief period of time (e.g., less than about one microsecond), so as to assist in charging an output of the bias circuit to its steady state value during a normal operating mode, see ¶ 0007).
Before the effective filing date of the claimed invention, it would have been in order to modify Lee, Asaki and Scoones with Bhattacharya to teach wherein the preset time period is from 0.5µs to 2µs. The suggestion/motivation would have been in order to reduce current consumption in a bias circuit (see ¶ 0007).
As to Claim 18, Lee, Asaki and Scoones depending from Claim 11, Lee and Annes do not expressly disclose wherein the preset time period is from 1µs to 1.5µs. Bhattacharya teaches wherein the preset time period is from 1 s to 1.5 s (Figure 5 illustrates a t1 – t2 interval [preset time period] between 0 and 200 ns in the sixth chart that would fall between 1 and 1.5 microseconds).
Before the effective filing date of the claimed invention, it would have been in order to modify Lee, Asaki and Scoones with Bhattacharya to teach wherein the preset time period is from 1µs to 1.5µs. The suggestion/motivation would have been in order to reduce current consumption in a bias circuit (see ¶ 0007).
Claim(s) 8, 10, 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2019/0172505 to Asaki et al (“Asaki”) in further view of U.S. Patent 8,970,199 to Scoones et al (“Scoones”) and in further view of U.S. Patent Publication 2015/0084694 to Lee et al (“Lee 3”).
As to Claim 8, Lee, Asaki and Scoones depending from Claim 1, Asaki teaches the control unit is configured to reduce the initial quiescent current of the electrical module to the first quiescent current, when there is a difference between the input voltage and the output voltage of the electrical module (an example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value, see Abstract; the bias circuit 410 provides a decreasing IBIAS current for an increasing supply voltage [difference between input voltage and output voltage, reduces the initial quiescent current to the first quiescent current], see ¶ 0045; Figures 5 & 6b illustrate the input voltage at node 26 is lower than the output voltage VDD2 when the IBIAS decreases).
Scoones teaches the control unit is configured to control to increase the initial quiescent current of the electrical module to the third quiescent current for a preset time period and then reduce the initial quiescent current of the electrical module to the first quiescent current (the bias current IBIAS starts at time TX with a maximum magnitude IMAX and falls gradually with a falling slope DNSL until the minimum bias current magnitude IMIN is reached, see Col. 6, lines 14-20; Figure 3 illustrates an IBIAS increasing to an IMAX value for a time period and after said time period, decreasing to an IMIN value).
Lee, Asaki and Scoones do not expressly disclose wherein the electrical sub-module comprises a comparator and a control unit, the comparator is configured to compare whether there is the difference between the output voltage and the input voltage of the electrical module or not.
Lee 3 teaches wherein the electrical sub-module comprises a comparator and a control unit, the comparator is configured to compare whether there is the difference between the output voltage and the input voltage of the electrical module or not (a method of controlling a buffer circuit [electrical sub-module] is provided. The method include generating a slew-rate compensation current based on a voltage difference between an input voltage signal and an output voltage signal, see ¶ 0027; The comparator 162 compares the input voltage signal VIN with the output voltage signal VOUT to generate a first current I_VDIFF corresponding to a difference between the input voltage signal VIN and the output voltage signal VOUT, see ¶ 0081).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Lee 3 to teach wherein the electrical sub-module comprises a comparator and a control unit, the comparator is configured to compare whether there is the difference between the output voltage and the input voltage of the electrical module or not. The suggestion/motivation would have been in order to generate a push or pull compensation current when an input voltage signal of the buffer circuit is greater or lower than an output voltage signal of the buffer circuit by a predetermined voltage (see ¶ 0034).
As to Claim 10, Lee teaches a data-driven method comprising: reducing an initial quiescent current of the electrical module to a first quiescent current when the input voltage and the output voltage of the electrical module are equal (The level of the output voltage VOUT becomes equal to the level of the input voltage VIN if the AB class buffer amplifier 700 operates as a buffer. Here, the comparing unit 730 generates the first signal S1 at a level for saturating both the second and fifth transistors MP2 and MN5 in order to reduce the amount of the quiescent current IQ, see ¶ 0194),
Lee does not expressly disclose reducing the initial quiescent current of the electrical module to the first quiescent current when there is a difference between the input voltage and the output voltage of the electrical module.
Asaki teaches reducing the initial quiescent current of the electrical module to the first quiescent current, when there is a difference between the input voltage and the output voltage of the electrical module (an example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value, see Abstract; the bias circuit 410 provides a decreasing IBIAS current for an increasing supply voltage [difference between input voltage and output voltage, reduces the initial quiescent current to the first quiescent current], see ¶ 0045; Figures 5 & 6b illustrate the input voltage at node 26 is lower than the output voltage VDD2 when the IBIAS decreases).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee with Asaki to teach reducing the initial quiescent current of the electrical module to the first quiescent current when there is a difference between the input voltage and the output voltage of the electrical module. The suggestion/motivation would have been in order for the bias voltage to be based at least on a bias current (see ¶ 0055).
Lee and Asaki do not expressly disclose reducing the initial quiescent current of the electrical module to the first quiescent current after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period.
Scoones teaches reducing the initial quiescent current of the electrical module to the first quiescent current after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period (the bias current IBIAS starts at time TX with a maximum magnitude IMAX and falls gradually with a falling slope DNSL until the minimum bias current magnitude IMIN is reached, see Col. 6, lines 14-20; Figure 3 illustrates an IBIAS increasing to an IMAX value for a time period and after said time period, decreasing to an IMIN value).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee and Asaki with Scoones to teach reducing the initial quiescent current of the electrical module to the first quiescent current after increasing the initial quiescent current of the electrical module to a third quiescent current for a preset time period. The suggestion/motivation would have been in order for the electronic device to provide a quick response for a change from low loads to high loads (see Col. 2, lines 16-18).
Lee, Asaki and Scoones do not expressly disclose detecting whether there is the difference between the output voltage and the input voltage of the electrical module or not.
Lee 3 teaches detecting whether there is the difference between the output voltage and the input voltage of the electrical module or not (a method of controlling a buffer circuit [electrical sub-module] is provided. The method include generating a slew-rate compensation current based on a voltage difference between an input voltage signal and an output voltage signal, see ¶ 0027; The comparator 162 compares the input voltage signal VIN with the output voltage signal VOUT to generate a first current I_VDIFF corresponding to a difference between the input voltage signal VIN and the output voltage signal VOUT, see ¶ 0081).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Lee 3 to teach detecting whether there is the difference between the output voltage and the input voltage of the electrical module or not. The suggestion/motivation would have been in order to generate a push or pull compensation current when an input voltage signal of the buffer circuit is greater or lower than an output voltage signal of the buffer circuit by a predetermined voltage (see ¶ 0034).
As to Claim 19, Lee, Asaki and Scoones depending from Claim 11, Asaki teaches the control unit is configured to reduce the initial quiescent current of the electrical module to the first quiescent current, when there is a difference between the input voltage and the output voltage of the electrical module (an example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value, see Abstract; the bias circuit 410 provides a decreasing IBIAS current for an increasing supply voltage [difference between input voltage and output voltage, reduces the initial quiescent current to the first quiescent current], see ¶ 0045; Figures 5 & 6b illustrate the input voltage at node 26 is lower than the output voltage VDD2 when the IBIAS decreases).
Scoones teaches the control unit is configured to control to increase the initial quiescent current of the electrical module to the third quiescent current for a preset time period and then reduce the initial quiescent current of the electrical module to the first quiescent current (the bias current IBIAS starts at time TX with a maximum magnitude IMAX and falls gradually with a falling slope DNSL until the minimum bias current magnitude IMIN is reached, see Col. 6, lines 14-20; Figure 3 illustrates an IBIAS increasing to an IMAX value for a time period and after said time period, decreasing to an IMIN value).
Lee, Asaki and Scoones do not expressly disclose wherein the electrical sub-module comprises a comparator and a control unit, the comparator is configured to compare whether there is the difference between the output voltage and the input voltage of the electrical module or not.
Lee 3 teaches wherein the electrical sub-module comprises a comparator and a control unit, the comparator is configured to compare whether there is the difference between the output voltage and the input voltage of the electrical module or not (a method of controlling a buffer circuit [electrical sub-module] is provided. The method include generating a slew-rate compensation current based on a voltage difference between an input voltage signal and an output voltage signal, see ¶ 0027; The comparator 162 compares the input voltage signal VIN with the output voltage signal VOUT to generate a first current I_VDIFF corresponding to a difference between the input voltage signal VIN and the output voltage signal VOUT, see ¶ 0081).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Lee 3 to teach wherein the electrical sub-module comprises a comparator and a control unit, the comparator is configured to compare whether there is the difference between the output voltage and the input voltage of the electrical module or not. The suggestion/motivation would have been in order to generate a push or pull compensation current when an input voltage signal of the buffer circuit is greater or lower than an output voltage signal of the buffer circuit by a predetermined voltage (see ¶ 0034).
Claim(s) 9, 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2003/0210094 to Lee et al (“Lee”) in view of U.S. Patent Publication 2019/0172505 to Asaki et al (“Asaki”) in further view of U.S. Patent 8,970,199 to Scoones et al (“Scoones”) in further view of U.S. Patent Publication 2012/0249245 to Chen et al (“Chen”) and in further view of U.S. Patent Publication 2021/0183320 to Lee et al (“Lee 4”).
As to Claim 9, Lee, Asaki and Scoones depends from Claim 1, Lee, Asaki and Scoones do not expressly disclose wherein the drive circuit comprises an interface receiving module, a data shift module, a data register module, a data latch module, a level conversion module and a digital/analog conversion module, output terminals of the interface receiving module and the data shift module are connected to an input terminal of the data register module, an output terminal of the data register module is connected to an input terminal of the data latch module, an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module, an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module, an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module. Chen teaches wherein the drive circuit comprises an interface receiving module (receiver 10, Fig. 1), a data shift module (shift register 14, Fig. 1), a data register module (data register 12, Fig. 1), a data latch module (line latch 16, Fig. 1), a level conversion module (level shifter 18, Fig. 1) and a digital/analog conversion module (digital-to-analog converter 20, Fig. 1), output terminals of the interface receiving module are connected to an input terminal of the data register module (receiver 10 is coupled to the data register 12, see ¶ 0019; Figure 1 illustrates outputs of the receiver 10 connected to the data register 12), an output terminal of the data register module is connected to an input terminal of the data latch module (the data register 12 is coupled to the line latch 16, see ¶ 0019, Fig. 1), an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module (the line latch 16 is coupled to the level shifter 18, see ¶ 0019, Fig. 1), an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module (the level shifter 18 is coupled to the digital-to-analog converter 20, see ¶ 0019, Fig. 1), an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module (the digital-to-analog converter 20 is coupled to the output buffer 22, see ¶ 0019, Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Chen to teach wherein the drive circuit comprises an interface receiving module, a data shift module, a data register module, a data latch module, a level conversion module and a digital/analog conversion module, output terminals of the interface receiving module and the data shift module are connected to an input terminal of the data register module, an output terminal of the data register module is connected to an input terminal of the data latch module, an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module, an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module, an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module. The suggestion/motivation would have been in order to enhance the slew rate of the output buffer (see Abstract).
Lee, Asaki, Scoones and Chen do not expressly disclose output terminals of the data shift module are connected to an input terminal of the data register module.
Lee 4 teaches output terminals of the interface receiving module and data shift module are connected to an input terminal of the data register module (the data controller 131 [interface receiving module] transmits the digital image data DATA stored in the lookup table to the first latch circuit 135A [data register module], see ¶ 0154; The shift register 134 [data shift module] generates a first latch enable signal 1st LEN for operating the first latch circuit 135A [data register module], see ¶ 0155).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki, Scoones and Chen with Lee 4 to teach output terminals of the data shift module are connected to an input terminal of the data register module. The suggestion/motivation would have been in order for a first latch circuit that stores the digital image data and offset image data received from the data controller (see ¶ 0023).
As to Claim 20, Lee, Asaki and Scoones depends from Claim 11, Lee, Asaki and Scoones do not expressly disclose wherein the drive circuit comprises an interface receiving module, a data shift module, a data register module, a data latch module, a level conversion module and a digital/analog conversion module, output terminals of the interface receiving module and the data shift module are connected to an input terminal of the data register module, an output terminal of the data register module is connected to an input terminal of the data latch module, an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module, an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module, an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module. Chen teaches wherein the drive circuit comprises an interface receiving module (receiver 10, Fig. 1), a data shift module (shift register 14, Fig. 1), a data register module (data register 12, Fig. 1), a data latch module (line latch 16, Fig. 1), a level conversion module (level shifter 18, Fig. 1) and a digital/analog conversion module (digital-to-analog converter 20, Fig. 1), output terminals of the interface receiving module are connected to an input terminal of the data register module (receiver 10 is coupled to the data register 12, see ¶ 0019; Figure 1 illustrates outputs of the receiver 10 connected to the data register 12), an output terminal of the data register module is connected to an input terminal of the data latch module (the data register 12 is coupled to the line latch 16, see ¶ 0019, Fig. 1), an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module (the line latch 16 is coupled to the level shifter 18, see ¶ 0019, Fig. 1), an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module (the level shifter 18 is coupled to the digital-to-analog converter 20, see ¶ 0019, Fig. 1), an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module (the digital-to-analog converter 20 is coupled to the output buffer 22, see ¶ 0019, Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki and Scoones with Chen to teach wherein the drive circuit comprises an interface receiving module, a data shift module, a data register module, a data latch module, a level conversion module and a digital/analog conversion module, output terminals of the interface receiving module and the data shift module are connected to an input terminal of the data register module, an output terminal of the data register module is connected to an input terminal of the data latch module, an output terminal of the data latch module is electrically connected to an input terminal of the level conversion module, an output terminal of the level conversion module is connected to an input terminal of the digital/analog conversion module, an output terminal of the digital/analog conversion module is electrically connected to an input of the electrical sub-module. The suggestion/motivation would have been in order to enhance the slew rate of the output buffer (see Abstract).
Lee, Asaki, Scoones and Chen do not expressly disclose output terminals of the data shift module are connected to an input terminal of the data register module.
Lee 4 teaches output terminals of the interface receiving module and data shift module are connected to an input terminal of the data register module (the data controller 131 [interface receiving module] transmits the digital image data DATA stored in the lookup table to the first latch circuit 135A [data register module], see ¶ 0154; The shift register 134 [data shift module] generates a first latch enable signal 1st LEN for operating the first latch circuit 135A [data register module], see ¶ 0155).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee, Asaki, Scoones and Chen with Lee 4 to teach output terminals of the data shift module are connected to an input terminal of the data register module. The suggestion/motivation would have been in order for a first latch circuit that stores the digital image data and offset image data received from the data controller (see ¶ 0023).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EBONI N GILES/ Examiner, Art Unit 2622
/PATRICK N EDOUARD/ Supervisory Patent Examiner, Art Unit 2622
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