Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 6/29/2021 and IDS filed on 5/30/2023 and 9/26/2023. Claims 1-20 are pending.
Claim Rejections - 35 USC § 101
3. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because claim 20 recited a system with plurality of modules, however a system with plurality of modules is considered as being entire computer program and/or software. Computer program is not one of four categories of patent eligible subject matter.
Applicant should incorporate the system to include a processor and/or memory, in order to overcome the 35 U.S.C 101 rejection above.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 1-4, 10-14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ariyama et al. (U.S. Pub. No. 2006/0059447 A1) in view of Chen et al. (U.S. Pub. No. 2015/0187294 A1).
As per claim 1, Ariyama discloses:
An automatic conversion method of binding pins, comprising:
defining signal identifiers of binding pins of a device (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated); and
recognizing the signal identifiers of the binding pins of the device automatically by an electronic design automation program, and generating and outputting signal identifiers of binding pins of a circuit board (See Para [0077], i.e. the printed circuit board is designed by referring to the FPGA library 110. During the design of the printed circuit board, when a change is made to the pin layout in step S22, the change is reflected in the pin layout information in step S23, See Para [0078], i.e. pin layout information changed during the circuit design and/or mount design is reflected in the matrix sheet 108 and the FPGA library 110 so that the stored pin layout information is updated, See Para [0133]-[0140] –[prior art design mount device onto PCB based on the signal identifiers is considered as the recognizing as cited above]),
wherein the signal identifiers comprise first signal identifiers and second signal identifiers, and one of the second signal identifiers corresponds to a plurality of first signal identifiers (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3 – [Figure 3 illustrate identifier such as A-AB, and signal name such as GND…NC , wherein Two signal identifier such as NC is associate with row D, considered as teaching the signal identifiers as cited above]);
Ariyama does not teach: the device is a display panel.
However, Chen discloses: the device is a display panel (See Para [0002]-[0003], i.e. panel assembly includes a display panel …a printed circuit board (PCB), See Para [0031], i.e. corresponding port, which can automatically and controllably choose the resistance of the adjustable resistor group, thus, the PCB).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Chen into
the teaching of Ariyama because it would reduce the cost of designing of display panel
(See Para [0002]-[0003]).
As per claim 2, Ariyama and Chen discloses all of the features of claim 1 as discloses above wherein Ariyama also discloses wherein the signal identifiers of the binding pins of the display panel comprise pin serial numbers and pin signals, the first signal identifiers are the pin serial numbers, and the second signal identifiers are the pin signals (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3).
As per claim 3, Ariyama and Chen discloses all of the features of claim 2 as discloses above wherein Ariyama also discloses wherein the pin serial numbers of the binding pins of the display panel are Arabic numbers arranged in sequence, and the pin signals of the binding pins of the display panel are electric signals received by the binding pins of the display panel (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3 –[Figure illustrate 1-22 and signal such as NC]).
As per claim 4, Ariyama and Chen discloses all of the features of claim 2 as discloses above wherein Ariyama also discloses wherein defining the signal identifiers of the binding pins of the display panel comprises: defining the binding pins of the display panel manually, and identifying the binding pins of the display panel by two levels of the pin serial numbers and the pin signals, wherein each of the pin serial numbers respectively corresponds to one of the pin signals (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3 –[Figure 3, illustrate Pin A-AB, and 1-22 , to locate pin signals such as DIN….NC]).
As per claim 10, Ariyama and Chen discloses all of the features of claim 2 as discloses above wherein Ariyama also discloses wherein the plurality of pin serial numbers corresponding to one of the pin signals are not adjacent to each other (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3).
As per claim 11, Ariyama discloses:
An automatic conversion method of binding pins, comprising:
defining signal identifiers of binding pins of a device (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated); and
recognizing the signal identifiers of the binding pins of the device (See
Para [0077], i.e. the printed circuit board is designed by referring to the FPGA library 110. During the design of the printed circuit board, when a change is made to the pin layout in step S22, the change is reflected in the pin layout information in step S23, See Para [0078], i.e. pin layout information changed during the circuit design and/or mount design is reflected in the matrix sheet 108 and the FPGA library 110 so that the stored pin layout information is updated, See Para [0133]-[0140] –[prior art design mount device onto PCB based on the signal identifiers is considered as the recognizing as cited above]),
automatically by an electronic design automation program, and generating and outputting signal identifiers of binding pins of a circuit board (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3 – [prior art generate design of PCB for mounting the device based on signal identifiers, is considered as the automatically generating as cited above]);
Ariyama does not teach: the device is a display panel.
However, Chen discloses: the device is a display panel (See Para [0002]-[0003], i.e. panel assembly includes a display panel …a printed circuit board (PCB), See Para [0031], i.e. corresponding port, which can automatically and controllably choose the resistance of the adjustable resistor group, thus, the PCB).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Chen into
the teaching of Ariyama because it would reduce the cost of designing of display panel
(See Para [0002]-[0003]).
As per claim 12, Ariyama and Chen discloses all of the features of claim 11 as
discloses above wherein Ariyama also discloses wherein the signal identifiers of the binding pins of the display panel comprise pin serial numbers and pin signals (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3).
As per claim 13, Ariyama and Chen discloses all of the features of claim 12 as discloses above wherein Ariyama also discloses wherein the pin serial numbers of the binding pins of the display panel are Arabic numbers arranged in sequence, and the pin signals of the binding pins of the display panel are electric signals received by the binding pins of the display panel (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3 –[Figure illustrate 1-22 and signal such as NC]).
As per claim 14, Ariyama and Chen discloses all of the features of claim 12 as discloses above wherein Ariyama also discloses wherein defining the signal identifiers of the binding pins of the display panel comprises: defining the binding pins of the display panel manually, and identifying the binding pins of the display panel by two levels of the pin serial numbers and the pin signals, wherein each of the pin serial numbers respectively corresponds to one of the pin signals (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3 –[Figure 3, illustrate Pin A-AB, and 1-22 , to locate pin signals such as DIN….NC]).
As per claim 20, Ariyama discloses:
An automatic conversion system of binding pins, comprising:
a defining module configured to define signal identifiers of binding pins of a device (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated); and
a recognition module configured to recognize the signal identifiers of the binding pins of the display panel automatically (See Para [0077], i.e. the printed circuit board is designed by referring to the FPGA library 110. During the design of the printed circuit board, when a change is made to the pin layout in step S22, the change is reflected in the pin layout information in step S23, See Para [0078], i.e. pin layout information changed during the circuit design and/or mount design is reflected in the matrix sheet 108 and the FPGA library 110 so that the stored pin layout information is updated, See Para [0133]-[0140] –[prior art design mount device onto PCB based on the signal identifiers is considered as the recognizing as cited above]),
a conversion module configured to convert the signal identifiers of the binding pins of the display device into signal identifiers of binding pins of a circuit board (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3 – [prior art generate PCB for mounting the device based on the signal identifiers is considered as the conversion as cited above]); and
an output module configured to output the signal identifiers of the binding pins of the circuit board (See Para [0059], i.e. pin layout matrix, See Para [0068]-[0072], i.e. generated from the pin layout information arranged in the matrix, See Para [0075], i.e. created pin layout information. On the tool control card 112, pin numbers and logic signal names are associated, See Figure 3 – [prior art generate PCB for mounting the device based on the signal identifiers is considered output as cited above]).
Ariyama does not teach: the device is a display panel.
However, Chen discloses: the device is a display panel (See Para [0002]-[0003], i.e. panel assembly includes a display panel …a printed circuit board (PCB), See Para [0031], i.e. corresponding port, which can automatically and controllably choose the resistance of the adjustable resistor group, thus, the PCB).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Chen into
the teaching of Ariyama because it would reduce the cost of designing of display panel
(See Para [0002]-[0003]).
Allowable Subject Matter
6. Claims 5-9 and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claims 5 and/or 15, wherein claims 6-9 depend on claim 5 – wherein claims 16-19 depend on claim 15..
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/ Primary Examiner, Art Unit 2851
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