Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed March 15, 2026 have been fully considered. Applicant argues that the amended Claims overcome the art of record. Examiner does not agree that the amendment overcomes the art of record. Applicant argues that “Yu reference does not teach, suggest, or describe an insulating film that covers and that is in contact with a metal film and that is in contact with a chip, and further that extends along a side surface of a light emitting element as claimed”. However, the applicant’s argument is not persuasive because as shown in below the insulating film (206, 304, and 306) covers and that is in contact with a metal film (304 covers a metal film 208 ) and is in contact with a chip (306 is in contact with 104) and further extends along a side of the light emitting device (306 extend along side of 104)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 12, 14, are rejected as being unpatentable over 35 U.S.C. 103 over Yu et al. US 20200014169 in view of Hozoji et al. US 20060267218.
Regarding claim 1, Yu teaches An electronic device (Fig. 9) comprising:
a semiconductor substrate; (Fig. 21, 202 Paragraph 0029 “on the semiconductor substrate 202.”)
a chip (Fig. 21, 104) having a different thermal expansion rate from a thermal expansion rate of the semiconductor substrate; (Since the chip and the substrate are made from different materials they will have different thermal expansion rates), wherein the chip includes a light emitting element (Fig. 21, 104, the laser devices) and
a connection part (Fig. 21, 208, 210) including a metal layer (Fig. 21, 210) for connecting connection pads (Fig. 21, 204A & 126) that are arranged on opposing principle surfaces of the semiconductor substrate and the chip (Fig. 21 shows that the connection pads 204A and 126 are arranged on opposing principle surfaces of the substrate and the chip).
wherein the connection part includes a metal film (Fig. 21, 208) between the metal layer and a connection pad on the semiconductor substrate or between the metal layer and a connection pad on the chip, (Fig. 21 shows the metal film 208 is between the metal layer (210) and the connection pad 204A on the substrate.)
wherein the metal film is in contact with the metal layer. (Fig. 21 shows 208 and 210 in contact)
an insulating film (Fig. 21, 206, 304 and 306 Paragraph 0029 “The passivation layer 206 may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, solder resist, polybenzoxazole (PBO), benzocyclobutene (BCB), molding compound, the like, or a combination thereof.” Paragraph 0039 “The passivation layer 304 may be formed from silicon oxide, silicon nitride, or the like,”) is in contact with and disposed on a periphery of one of the connection pad on the semiconductor substrate or the connection pad on the chip (Fig. 21 shows that 304 and 306 are in contact with and on a periphery of the connection pad 126 and 204A.),
wherein the insulating film extends along a side surface of the light emitting element (element 306 extends along a side of the light emitting element 104) and
wherein at least one of the metal film, the connection pad on the semiconductor substrate or the connection pad on the chip is in contact with the insulating film. (Fig. 21 shows the metal film in contact with the insulating film) and,
wherein a periphery of the metal film is covered by an in contact with the insulating film. (Fig. 21 shows 304 overing the periphery of 208 and in contact with 208), and
wherein the chip is in contact with the insulating film. (See annotated Fig. 21 below)
Yu does not teach the metal layer is made from porous metal.
However,
Hozoji teaches the metal layer is made from porous metal. (Fig. 3, 104 Paragraph 0065 “Au bumps 104 are used for electrical connection between the MOSFET 101 and the substrate 1, and are each made up of Au particles having an average particle size of 5 nm”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the metal layer as taught by Yu by having the metal be porous as disclosed by Hozoji. One of ordinary skill in the art would have been motivated to make this modification in order to have a higher melting point than a solid metal layer. (Paragraph 0086 “Also, in a nano-particle bonding method according to the present invention, the nano-particle layer constituting the bonding layer exhibits properties of a solid metal or a solid metal alloy, and has a high melting point comparable to those of Au and Ag.”)
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Regarding claim 12, Yu teaches insulating resin is filled between the semiconductor substrate and the chip. (Fig. 21, 306 Paragraph 0040 “The isolation material 306 may be formed from an oxide (such as silicon oxide), a polymer (such as a polyimide, a low temperature polyimide (LTPI), PBO, or BCB), or the like.”)
Regarding claim 14, Yu teaches the metal film has a same component as a component of the porous metal layer (Paragraph 0030 “The second structure 200 further includes contact pads 208, such as aluminum or copper pads or pillars” Paragraph 0031 “The conductive connectors 210 may be formed from a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, bismuth, the like, or a combination thereof.” Both the film and the layer can be made from copper)
Regarding claim 24, Yu teaches the insulating film is a first insulating film (Fig. 21, 304), a periphery of the connection pad on the chip is covered by the first insulating film (Fig. 21 shows 304 touching the periphery of 126), and wherein a periphery of the connection pad on the semiconductor substrate is covered by a second insulating film (Fig. 21, 206 The periphery of 204A is touching 206).
Claim 2 is rejected as being unpatentable over 35 U.S.C. 103 over Yu and Hozoji in view of Feustel et al. US 20060246627.
Regarding claim 2, Yu does not teach a difference between the thermal expansion rates of the chip and the semiconductor substrate is 0.1 ppm/C or greater.
However,
Feustel teaches a difference between the thermal expansion rates of the chip and the semiconductor substrate is 0.1 ppm/C or greater. (Paragraph 0010 “For example, the semiconductor chip 110 may be substantially comprised of a semiconductive material, such as silicon, and may have a coefficient of thermal expansion of approximately three parts per million per degree Celsius (ppm/C), while the carrier substrate 120 may have a different coefficient, such as a difference of a few ppm/C for an alumina ceramic substrate and may be as high as approximately 17-22 ppm/C”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified laser device as taught by Yu by having the thermal expansion rates of the chip and the substrate to be greater than 0.1 ppm/C as disclosed by Feustel. One of ordinary skill in the art would have been motivated to make this modification in order to increase the reliability of the electronic device and reduce the probability of premature failure of the connection. (Feustel Paragraph 0010)
Claims 16-18 are rejected as being unpatentable over 35 U.S.C. 103 over Yu and Hoxoji in view of Hagihara US 20110147927.
Regarding claim 16, Yu does not explicitly teach the metal film is formed such that a ratio of a film thickness to the thickness of a connection part in a direction perpendicular to a principle surface is set to be less than 5%. Rather, Yu teaches the metal film having a thickness of 2 microns (Paragraph 0030 “In some embodiments, the contact pads 208 are multilayered, e.g., the contact pads 208 include a copper layer on a nickel layer, with the copper layer and the nickel layer each being about 1 μm thick.”) and that the thickness of the porous metal layer can have any thickness (Paragraph 0031 “The conductive connectors 210 may have any height.”)
However,
Hagihara teaches the metal layer having a thickness of 100 microns (Paragraph 0054 “he solder bump 4 is formed by, for example, forming on the UBM layer 3 a solder ball having a diameter of 100 µm”). By having the porous metal layer be 100 microns the ratio of the film thickness to the thickness of the connection part is 1.96% which is less than 5%.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the size of the porous metal layer as taught by Yu by changing the size of the metal layer to 100 microns as disclosed by Hagihara. One of ordinary skill in the art would have been motivated to make this modification in order to avoid shorting between the chip and the substrate.
Regarding claim 17, Yu does not explicitly teach the metal film is formed such that a ratio of a film thickness to a thickness of the connection part in a direction perpendicular to the principle surface is set to be 10% or smaller. Rather, Yu teaches the metal film having a thickness of 2 microns (Paragraph 0030 “In some embodiments, the contact pads 208 are multilayered, e.g., the contact pads 208 include a copper layer on a nickel layer, with the copper layer and the nickel layer each being about 1 μm thick.”) and that the thickness of the porous metal layer can have any thickness (Paragraph 0031 “The conductive connectors 210 may have any height.”)
However,
Hagihara teaches the metal layer having a thickness of 100 microns (Paragraph 0054 “he solder bump 4 is formed by, for example, forming on the UBM layer 3 a solder ball having a diameter of 100 µm”). By having the porous metal layer be 100 microns the ratio of the film thickness to the thickness of the connection part is 1.96% which is less than 10%.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the size of the porous metal layer as taught by Yu by changing the size of the metal layer to 100 microns as disclosed by Hagihara. One of ordinary skill in the art would have been motivated to make this modification in order to avoid shorting between the chip and the substrate.
Regarding claim 18, Yu does not explicitly teach the metal film is formed such that the ratio of the film thickness to the thickness of the connection part in the direction perpendicular to the principle surface is set to be less than 5%. Rather, Yu teaches the metal film having a thickness of 2 microns (Paragraph 0030 “In some embodiments, the contact pads 208 are multilayered, e.g., the contact pads 208 include a copper layer on a nickel layer, with the copper layer and the nickel layer each being about 1 μm thick.”) and that the thickness of the porous metal layer can have any thickness (Paragraph 0031 “The conductive connectors 210 may have any height.”)
However,
Hagihara teaches the metal layer having a thickness of 100 microns (Paragraph 0054 “he solder bump 4 is formed by, for example, forming on the UBM layer 3 a solder ball having a diameter of 100 µm”). By having the porous metal layer be 100 microns the ratio of the film thickness to the thickness of the connection part is 1.96% which is less than 5%.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the size of the porous metal layer as taught by Yu by changing the size of the metal layer to 100 microns as disclosed by Hagihara. One of ordinary skill in the art would have been motivated to make this modification in order to avoid shorting between the chip and the substrate.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINSUN OH HARVEY whose telephone number is (571)272-1835. The examiner can normally be reached Monday-Friday.
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MINSUN OH. HARVEY
Supervisory Patent Examiner
Art Unit 2828
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