Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 09/15/2025 have been fully considered but they are not persuasive.
Applicant argues Kimura does not teach acquiring a trigger signal based on a logical sum of an output of logic circuits, or detecting a state of a logic circuit based on a trigger signal and detected carry.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant only discusses Kimura, and simply says Emoto and Shirahama do not remedy the deficiencies of Kimura. However, in the non-final office action, Shirahama was used to teach logic circuits. Thus, this argument is not persuasive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 8, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 20200256962 A1) in view of Emoto (JP 2014107793 A) further in view of Shirahama (JP 2017147692 A).
Claim 1: Kimura teaches a light receiving device, comprising:
a single photon avalanche diode (SPAD) configured to receive light ([0032] and [0113] - describing Fig. 17);
a Time to Digital Converter (TDC) configured to ([0107]);
measure time information from a light emission timing of a light source to a light receiving timing of the SPAD ([0107])
generate a plurality of Time of Flight (ToF) values based on the time information ([0048]);
and circuitry configured to generate a histogram based on the plurality of ToF values ([0116] and Fig 17, histogram generating section 13b),
wherein the histogram includes N bits as frequency values of the plurality of ToF values ([0048] and Fig 1, conversion section 11),
the N bits include a plurality of low order bits and a plurality of high order bits ([0048]),
A processor […] configured to […] and store generate a low-order bit of the N bits,
each […] circuit of the plurality of […] circuits is configured to detect carry of a corresponding low-order bit of the N bits, of the plurality of low order bits […] (Fig 4 - changing DU (high order) based on DL (low order) - implies some detection of DL),
the one of the [memory] is configured to:
store a high-order bit of the plurality of high order bits ([0047] - outputs DU (high order bit) to processing section 13 – wherein updating frequency is simply adding it to the memory),
acquire a trigger signal […] ([0050]);
detect that a bit state of at least one logic circuit of the plurality of logic circuits is in on condition, wherein the bit state of the at least one logic circuit is detected based on the trigger signal and the detected carry of the at least one logical circuit ([0053]),
and count, based on the detection that the bit state […] is in the on condition, a specific frequency value of the high- order bit stored in the one of the SRAM or the DRAM, wherein the high- order bit corresponds to the detected carry of the at least one logic circuit (Fig. 5 and [0056]-[0060]),
Kimura does not teach that the circuitry includes a plurality of Flip-Flop circuits,
a plurality of logic circuits,
one of a static random access memory (SRAM) or a dynamic random access (DRAM),
and a processor,
each Flip-Flop circuit of the plurality of Flip-Flop circuits is configured to operate at a first speed,
[…]
each logic circuit of the plurality of logic circuits corresponds to a Flip-Flop circuit of the plurality of Flip-Flop circuits,
operate at a second speed slower than the first speed.
Emoto teaches a counting device which includes both a high speed counter for lower order bits, and a low speed counter for higher order bits (See attached PDF – page 1, highlighted portion).
It would have been obvious to use the counting speeds as taught by Emoto with the measurement unit as taught by Kimura because this optimizes the access speed (See Emoto, pg 3, highlighted portion).
Kimura, as modified in view of Emoto, still does not teach the circuitry includes a plurality of Flip-Flop circuits, a plurality of logic circuits, one of a static random access memory (SRAM) or a dynamic random access (DRAM), and a processor, each Flip-Flop circuit of the plurality of Flip-Flop circuits is configured to operate at a first speed, each logic circuit of the plurality of logic circuits corresponds to a Flip-Flop circuit of the plurality of Flip-Flop circuits.
Shirahama teaches a histogram counter which includes high and low bit counters. The low order bit counter can be comprised of a flip flop circuit (page 3, highlighted portion of PDF) and the high order counter can be comprised of DRAM or SRAM (Page 13 of attached PDF, highlighted portion).
It would have been obvious to use the SRAM, DRAM, and flip flop as taught by Shirahama with the device as taught by Kimura because SRAM, DRAM, and flip flop are well-known in the art, commercially available, and would yield predictable results.
Claim 4: Kimura, as modified in view of Emoto, further in view of Shirahama, teaches the light receiving device according to claim 3, wherein the processor is further configured to: check the bit states of the plurality of logic circuits (Kimura [0053], taken with Shirahama pg. 3).
Claim 8 is a method claim corresponding to Claim 1. Thus, see rejection above.
Claim 9: Kimura teaches an illumination device comprising a light source configured to emit illumination light (Fig 1, light emitting section 2);
and a light receiving device comprising (Fig 17, light receiving section 3b and [0032], [0113] - describing Fig 17 - note although light emitting unit is not shown, it would be easily integrated):
a single photon avalanche diode (SPAD) configured to receive reflected light of the illumination light [[0032]);
a Time to Digital Converter (TDC) configured to ([0107]);
measure time information from a light emission timing of a light source to a light receiving timing of the SPAD ([0107])
generate a plurality of Time of Flight (ToF) values based on the time information ([0048]);
and circuitry configured to generate a histogram based on the plurality of ToF values ([0116] and Fig 17, histogram generating section 13b),
wherein the histogram includes N bits as frequency values of the plurality of ToF values ([0048] and Fig 1, conversion section 11),
A processor […] configured to […] and store generate a low-order bit of the N bits,
each […] circuit of the plurality of […] circuits is configured to detect carry bit of the low-order bit of the N bits (Fig 4 - changing DU (high order) based on DL (low order) - implies some detection of DL),
the one of the [memory] is configured to:
store a high-order bit of the N bits ([0047] - outputs DU (high order bit) to processing section 13 – wherein updating frequency is simply adding it to the memory),
acquire a trigger signal […] ([0050]);
detect that a bit state of at least one logic circuit of the plurality of logic circuits is in on condition, wherein the bit state of the at least one logic circuit is detected based on the trigger signal and the detected carry of the at least one logical circuit ([0053]),
and count, based on the detection that the bit state […] is in the on condition, a specific frequency value of the high- order bit stored in the one of the SRAM or the DRAM, wherein the high- order bit corresponds to the detected carry of the at least one logic circuit (Fig. 5 and [0056]-[0060]),
Kimura does not teach that the circuitry includes a plurality of Flip-Flop circuits,
a plurality of logic circuits,
one of a static random access memory (SRAM) or a dynamic random access (DRAM),
and a processor,
each Flip-Flop circuit of the plurality of Flip-Flop circuits is configured to operate at a first speed,
[…]
each logic circuit of the plurality of logic circuits corresponds to a Flip-Flop circuit of the plurality of Flip-Flop circuits,
operate at a second speed slower than the first speed.
Emoto teaches a counting device which includes both a high speed counter for lower order bits, and a low speed counter for higher order bits (See attached PDF – page 1, highlighted portion).
It would have been obvious to use the counting speeds as taught by Emoto with the measurement unit as taught by Kimura because this optimizes the access speed (See Emoto, pg 3, highlighted portion).
Kimura, as modified in view of Emoto, still does not teach the circuitry includes a plurality of Flip-Flop circuits, a plurality of logic circuits, one of a static random access memory (SRAM) or a dynamic random access (DRAM), and a processor, each Flip-Flop circuit of the plurality of Flip-Flop circuits is configured to operate at a first speed, each logic circuit of the plurality of logic circuits corresponds to a Flip-Flop circuit of the plurality of Flip-Flop circuits.
Shirahama teaches a histogram counter which includes high and low bit counters. The low order bit counter can be comprised of a flip flop circuit (page 3, highlighted portion of PDF) and the high order counter can be comprised of DRAM or SRAM (Page 13 of attached PDF, highlighted portion).
It would have been obvious to use the SRAM, DRAM, and flip flop as taught by Shirahama with the device as taught by Kimura because SRAM, DRAM, and flip flop are well-known in the art, commercially available, and would yield predictable results.
Claim 10: Kimura, as modified in view of Emoto and Shirahama, teaches the light receiving device according to claim 1. Only Shirahama teaches wherein the processor is further configured to reset a bit state of the at least one logical circuit, and the bit state of the at least one logical circuit is reset after the count of the specific frequency value of the high-order bit stored in the one of the SRAM or the DRAM (Pg. 6, paragraph starting with “In the State S3, the histogram …”).
It would have been obvious before the effective filing date been obvious to reset the count, as taught by Shirahama, because this allows for the next process to occur independently.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 20200256962 A1) in view of Emoto (JP 2014107793 A) in view of Shirahama (JP 2017147692 A). further in view of Matsumoto (US 20190067359 A1).
Claim 6: Kimura, as modified in view of Emoto and Shirahama, teaches the light receiving device according to claim 1, but not wherein further comprising one chip, wherein the chip comprises a stack structure of three substrates.
Matsumoto teaches an image sensor which comprises multiple substrates. One substrate has a plurality of pixels ([0022]), while the other substrates process bit signals ([0054], low order bit signals on third substrate and high order on fourth substrate).
It would have been obvious that using multiple substrates (note although Matsumoto teaches 4, 3 substrates falls in the range), two of which process different bits, would be obvious as using separate substrates is well known in the art, and would yield predictable results.
Claim 7: Kimura, as modified in view of Emoto and Shirahama, and further in view of Matsumoto, teaches the light receiving device according to claim 6, wherein the three substrates includes a first substrate, a second substrate, and a third substrate, the comprises a pixel array (Matsumoto [0022]), the plurality of flip flop circuits are on the second substrate, and the one of the SRAM or the DRAM, and the processor are on the third substrate (Matsumoto [0054], low order bit signals on third substrate and high order on fourth substrate).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CLARA G CHILTON/Examiner, Art Unit 3645
/ROBERT W HODGE/Supervisory Patent Examiner, Art Unit 3645