DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/15/2026 has been entered.
Claims 1 – 3, 5 – 6, and 21 – 30 are pending for examination.
Information Disclosure Statement
The information disclosure statement filed 02/18/2026, 12/10/205, 02/18/2026, 04/15/2026 and 06/16/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 – 3, 5 – 6, and 21 - 30 are rejected under 35 U.S.C. 103 as being unpatentable over Appu et al., (US PUB 2018/00308201 hereinafter Appu) in view of Surti et al., (US PUB 2018/0308200 hereinafter Surti) and further in view of Cherukuri et al., (US PUB 2014/0006714 hereinafter Cherukuri).
As to claim 1, Appu teaches an apparatus comprising:
processing circuitry coupled to a memory, the processing circuitry comprises a multi-tile graphics processing circuitry having processor tiles to process data (“...Additionally, graphics processor 2910 includes an inter-core task manager 2905, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2915A-2915N and a tiling unit 2918 to accelerate tiling operations for tile-based rendering,..” para. 0297), [the processor tiles are coupled to a substrate, wherein the multi-tile graphics processing circuitry having the processor tiles represents a single graphics processor socket on a common substrate], wherein a processor tile comprises a semiconductor die (“High end graphics processors (e.g., discrete package and on-package graphics die) typically implement high bandwidth memory (HBM), which is a high-performance RAM interface. HBM is included in the same package as a GPU, and is connected via a silicon bridge. The silicon bridge includes a high density of wires that connect the GPU die...” para. 0151), wherein the multi-tile graphics processing circuitry is further to:
receive compute work for processing (“...The scheduler 210 can allocate work to the clusters 214A-214N of the processing cluster array 212 using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising...” para. 0046);
analyze the compute work by partitioning the compute work into multiple work units (“...divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations to multiple clusters 214A-214N of the processing cluster array...” para. 0050) for processing by the processor tiles utilizing a multi-tile walker associated with the multi-tile graphics processing circuitry (“...Additionally, graphics processor 2910 includes an inter-core task manager 2905, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2915A-2915N and a tiling unit 2918 to accelerate tiling operations for tile-based rendering...” para. 0297).
[select a first set of the processor tiles to process a first work unit and a second set of the processor tiles to process a second work unit, wherein the first and second sets of the processor tiles are associated with first and second work units to optimize the processing of the compute work; and
process the compute work based on the first and second work units using the first and second sets of processor tiles].
Appu does not but Surti teaches select a first set of the processor tiles to process a first work unit and a second set of the processor tiles to process a second work unit (“The graphics processor of claim 14, wherein the compute logic selects the EUs of the first type to process a first type of application workload and selects the EUs of the second type to process a second type of application workload” claim 16) and (Example 5 includes the subject matter of Examples 1-4, wherein the compute logic selects the EUs of the first type to process a first type of application workload and selects the EUs of the second type to process a second type of application workload” para. 0306) and (Example 15 includes the subject matter of Examples 11-14, wherein the compute logic selects the EUs of the first type to process a first type of application workload and selects the EUs of the second type to process a second type of application workload.“ para. 0316), wherein the first and second sets of the processor tiles are associated with first and second work units to optimize the processing of the compute work (“During an application, when GPU 614 is invoked, compute mechanism 610 selects the EUs that are to be implemented to execute a workload. In one embodiment, compute mechanism 610 may include a compiler that statically selects the EUs prior to execution of the application such that the EU configuration remains the same during the lifetime of a specific application....” para. 0156. Note: an execution unit is a processor tile as graphic processor is of system on chip (SoC)) and (“...optimizing computing of a graphics processor is disclosed. In some embodiments, the compute mechanism includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type...” para. 0035) and (“...graphics processor of a system on a chip integrated circuit” para. 0034 and figures 15, 27 and 29); and
process the compute work based on the first and second work units using the first and second sets of processor tiles (“...process a first type of application workload...process a second type of application workload.“ para. 0316).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Appu by applying the teachings of Surti teaches because selecting EU type to execute particular type of application workload to optimize the execution (para. 0035).
Appu and Surti do not but Cherukuri teaches
the processor tiles are coupled to a substrate, wherein the multi-tile graphics processing circuitry having the processor tiles represents a single graphics processor socket on a common substrate (“...the tiles are generally all disposed on the same semiconductor substrate (e.g., an integrated circuit die or chip). An interconnect 334 (e.g., an on-die or on-substrate interconnect) couples the tiles together....” para. 0034) and (“...Thus, the processor 1400 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1400 may be a part of and/or may be implemented on one or more substrates ...” para. 0088).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Appu and Surti by applying the teachings of Cherukuri because Cherukuri teaches the same field of graphic processing on system on chip (SoC) to execute graphic workloads. Cherukuri provides substrate as additional name and/or graphic component for the system (figure 3 and associated text, especially para. 0034).
As to claim 2, Appu modified by Surti and Cherukuri teaches The apparatus of claim 1, Appu and Cherukuri do not but Surti teaches wherein the multi-tile graphics processing circuitry is further to organize the compute work in multiple dimensions such that the partitioning of the compute work is based on partitioning the compute work into the multiple work units that are spread over the multiple dimensions (“..The dimensionality reduction performed within the convolutional layers is one aspect that enables the CNN to scale to process large images.” Para. 0185) and (“..However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 1810. In some embodiments, GPE 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations....” para. 0231).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Appu by applying the teachings of Surti teaches because Surti provides dimension array implementation to process graphic and media operations more efficiently (para. 0212).
As to claim 3, Appu modified by Surti and Cherukuri teaches the apparatus of claim 1, Appu teaches wherein the(“...Additionally, graphics processor 2910 includes an inter-core task manager 2905, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2915A-2915N and a tiling unit 2918 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.” para. 0297).
Appu and Cherukuri do not but Surti teaches in one or more dimensions (“..The dimensionality reduction performed within the convolutional layers is one aspect that enables the CNN to scale to process large images.” Para. 0185) and (“..However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 1810. In some embodiments, GPE 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations....” para. 0231). See motivation for claim 2 above.
As to claim 5, Appu modified by Surti and Cherukuri teaches The apparatus of claim 1, Appu teaches wherein the processing circuitry is further to:
assign a single processor tile of the processor tiles to the compute work such that the compute work remains unpartitioned; and process the compute work using the single processor tile (“..single processor desktop system...” para. 0209) and (“...Graphics processor 2910 includes one or more shader core(s) 2915A-2915N (e.g., 2915A, 2915B, 2915C, 2915D, 2915E, 2915F, through 2915N-1, and 2915N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code...” para. 0297).
As to claim 6, Appu modified by Surti and Cherukuri teaches The apparatus of claim 1, Appu teaches wherein the first and second processor tiles are assigned to the first and second sets of work units based on varying characteristics of the first and second processor tiles (“The graphics processor of claim 14, wherein the compute logic selects the EUs of the first type to process a first type of application workload and selects the EUs of the second type to process a second type of application workload” claim 16) and (Example 5 includes the subject matter of Examples 1-4, wherein the compute logic selects the EUs of the first type to process a first type of application workload and selects the EUs of the second type to process a second type of application workload” para. 0306) and (Example 15 includes the subject matter of Examples 11-14, wherein the compute logic selects the EUs of the first type to process a first type of application workload and selects the EUs of the second type to process a second type of application workload.“ para. 0316).
As to claim 21, this is a method claim of claim 1. See rejection for claim 1 above.
As to claims 22 - 23, these claims recite similar scope of claim 2 – 3. See rejection for claims 2 – 3 above.
As to claims 24 - 25, these claims recite similar scope of claim 5 – 6. See rejection for claims 5 – 6 above.
As to claim 21, this is a computer-readable medium claim of claim 1. See rejection for claim 1 above. Further, Appu teaches computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations (“..a computer program product which may include one or more machine-readable media having stored thereon machine-executable instructions that, when executed...” para. 0149).
As to claims 27 - 28, these claims recite similar scope of claim 2 – 3. See rejection for claims 2 – 3 above.
As to claims 29 - 30, these claims recite similar scope of claim 5 – 6. See rejection for claims 5 – 6 above.
Response to Arguments
Applicant’s arguments, with respect to IDS objection, has been fully considered and are persuasive. The objection has been withdrawn.
Applicant’s arguments, with respect to 112(b) have been fully considered and are persuasive. The 112(b) rejection has been withdrawn.
Applicant’s arguments, with respect to 103 rejection, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure.
Ray, (US PUB 2018/0293690), discloses a method for managing data in graphics processor of a system on a chip (title, abstract and figures 1 – 31).
Benthin, (US PUB 2018/0040096), discloses a method for accelerating graphics workloads in a multi-core processor, wherein first and second workloads are selected for processing by first and second processing cores (title, abstract and figures 1 – 17).
Bose, (US PUB 2018/0052499), discloses a multi-core processor in a integrated circuit (IC) chip (title, abstract and figures 1 – 15).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG N HOANG whose telephone number is (571)272-3763. The examiner can normally be reached 9:5-30.
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/PHUONG N HOANG/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
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