DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art.
Claims 1 – 30 are pending for examination. Claims 1 – 3, 5 – 6 are amended. Claims 7 – 20 are cancelled. Claims 21 – 30 are new.
References were cite in previous office action.
Information Disclosure Statement
One of the information disclosure statements filed 08/12/25 and 09/12/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
One of the information disclosure statement filed 08/12/25 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document (Document # 5 - 7 of Foreign Patent is not provided with a copy of the listed document); each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 3, 5 – 6 and 21 – 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
As to claim 1, last limitation “process the compute work based on the first and second work unit using the first second set of processor titles” is not clearly understood. For examination purpose, examiner treats the limitation as -- process the compute work based on the first and second work unit using the first and second set of processor titles --.
As to claims 2 – 3, 5 - 6, they are rejected as they depends on their independent claim.
As to claim 21, it is a method claim of claim 1. It is rejected for the same reason as to claim 1.
As to claims 22 – 25, they are rejected as they depends on their independent claim.
As to claim 26, it is a method claim of claim 1. It is rejected for the same reason as to claim 1.
As to claims 27 – 30, they are rejected as they depends on their independent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 3, 6, 21 – 23, 25 – 28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Cui et al., (US PUB 2020/0042362 hereinafter Cui) in view of Dally et al., (US PUB 2014/0266417 hereinafter Dally), and further in view of Kessler et al., (US PUB 2015/0254104 hereinafter Kessler).
As to claim 1, An apparatus comprising:
processing circuitry coupled to a memory (“…memory…” para. 0028), the processing circuitry comprises [multi-tile] graphics processing circuitry having processor tiles to process data (“…a cluster of accelerator devices (e.g., GPU devices) performing a distributed, data parallel DL model training task…” para. 0014), [the processor tiles are coupled to a substrate, wherein a processor tile comprises a semiconductor die]
wherein the [multi-tile] graphics processing circuitry is further to:
receive compute work (“… input dataset…” para. 0015 and 0029) for processing (“…a self-adaptive batch dataset partitioning control process which is utilized in conjunction with a distributed deep learning model training process to optimize load balancing among a set of accelerator resources. An iterative batch size tuning process is configured to determine an optimal job partition ratio for partitioning mini-batch datasets into sub-batch datasets for processing by a set of hybrid accelerator resources…” abstract) and (“…a cluster of accelerator devices (e.g., GPU devices) performing a distributed, data parallel DL model training task” para. 0014);
analyze the compute work by partitioning the compute work into multiple work units for processing by the processor [tiles] (“…implementing a self-adaptive batch dataset partitioning control process which is utilized in conjunction with a distributed deep learning model training process to optimize load balancing among a set of accelerator resources. As explained in further detail below, embodiments of the invention include systems and methods for implementing an iterative batch size tuning process which is configured to determine an optimal job partition ratio for partitioning mini-batch datasets into sub-batch datasets for processing by a set of hybrid accelerator resources…” para. 0013);
[select a first set of the processor tiles] to process a first work unit and [a second set of the processor tiles] to process a second work unit, wherein the first and second sets of the processor [tiles] are associated with first and second work units to optimize the processing of the compute work (“…An initial mini-batch iteration of the distributed deep learning model training process is performed by each of the accelerator resources processing a corresponding one of the sub-batch datasets of the initial mini-batch dataset…” para. 0005. Note: each of the accelerator resource would comprise first and second accelerator to be claimed processor and corresponding sub-batch datasets would comprise first and second dataset); and
process the compute work based on the first and second work units using the first second sets (“…The accelerators 320-1, 320-2, 320-3, and 320-4 execute a model training task by processing the respective sub-batch datasets 390-1, 390-2, 390-3, and 390-4 using the model computation graph 375…” para. 0047).
Cui does not but Dally teaches the multi-tile GPU (“Multi-Chip GPU system…” para. 0086 and figures 6. Note: chip is tile) including a plurality of processor tiles (“…A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package…” title, abstract) and the plurality of processor tiles are coupled a substrate (“…electrical traces within MCM package 190. Each electrical trace may comprise a conductive element affixed to a dielectric substrate, such as an organic substrate layer of MCM package 190…” para. 0108), a processor tile comprising a semiconductor die (“…a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation….” Para. 0127).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention to modify Cui by adopt the teachings of Dally because Dally would provide multi-chip GPU to interconnect chips for graphical processing with higher performance and higher density systems (para. 0034 - 0035).
Cui and Dally do not but Kessler teaches select a first and second set of processor tiles (“…a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing,…” abstract) and (“According to at least one example embodiment, a new processor architecture, for a new generation of processors, allows a group of chip devices to operate as a single chip device. Each chip device includes an inter-chip interconnect interface configured to couple the chip device to other chip devices forming a multi-chip system. Memory coherence methods are employed in each chip device to enforce memory coherence between memory components associated with different chip devices in the multi-chip system. Also, methods for assigning processing tasks to different core processors in the multi-chip system …” para. 0026. Note: different core processor would comprise first and second core processors/processor tiles).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention to modify Cui and Dally by adopt the teachings of Kessler because Kessler would reduce consumption of available inter-chip interconnect interface intra-chip interconnect interface memory transactions, and reduces bandwidth consumption (para. 0127).
As to claim 2, Cui modified by Dally and Kessler teaches the apparatus of claim 1, Cui teaches wherein multi-tile graphics processing circuitry is further to organize the compute work in multiple dimensions such that the partitioning of the compute work is based on partitioning the compute work into the multiple work units that are spread over multiple dimensions to generate (”…wherein the sub-batch datasets are partitioned into optimal batch sizes for processing by respective accelerator resources…” abstract, para. 0013 and 0032).
As to claim 3, Cui modified by Dally and Kessler teaches the apparatus of claim 1, Cui teaches wherein the compute work is partitioned and processed using [multi-tile] walker (“…An iterative batch size tuning process is configured to determine an optimal job partition ratio …” abstract and para. 0013).
Cui and Kessler do not but Dally teaches multi-tile (“…A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package…” title, abstract).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention to modify Cui by adopt the teachings of Dally because Dally would provide multi-chip GPU to interconnect chips for graphical processing with higher performance and higher density systems (para. 0034 - 0035).
As to claim 6, Cui modified by Dally and Kessler teaches the apparatus of claim 1, Cui teaches wherein the first and second processor tiles are assigned to the first and second sets of work units based on varying characteristics of the first and second processor [titles] (“…FIG. 3, assume that each mini-batch dataset 390 of the training dataset 380 comprises 128 samples of training data (e.g., 128 pictures). Assume further that the accelerators 320-1 and 320-2 (Type A) are faster than the accelerators 320-3 and 320-4 (Type B), wherein the Type A accelerators are implemented using, for example, NVIDIA Tesla P100 GPU Accelerators, and wherein the Type B accelerators are implemented using, for example, NVIDIA Tesla K40c GPU computing processors…” para. 0050 and figure 3).
Cui and Kessler do not but Dally teaches tiles (“…A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package…” title, abstract).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention to modify Cui and Kessler by adopt the teachings of Dally because Dally would provide multi-chip GPU to interconnect chips for graphical processing with higher performance and higher density systems (para. 0034 - 0035).
As to claims 21, this is a method claim of claim 1. See rejection for claim 1 above.
As to claims 22 – 23 and 25, they recite similar scope of claims 2 – 3 and 6. See rejection for claims 2 - 3 and 6 above.
As to claims 26, this is a computer-readable medium claim of claim 1. See rejection for claim 1 above. Further, Cai teaches computer-readable medium (...“processor-readable storage media” that store executable program code of one or more software programs...” para. 0039 and para. 0071).
As to claims 22 – 23 and 25, they recite similar scope of claims 2 – 3 and 6. See rejection for claims 2 - 3 and 6 above.
9. Claims 5, 24 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Cui in view of Dally and Kessler, as applied to claims 1, 8 and 15, and further in view of Inglett et al., (US PUB 2008/0288746 hereinafter Inglett).
10. Inglett reference was cited in previous office action.
As to claim 5, Cui modified by Dally and Kessler teaches the apparatus of claim 1, Cui teaches wherein the processing circuitry is further to:
[assign a single processor tile of the plurality of processor tiles to the compute work such that the compute work remain unpartitioned; and ]
process the compute work using the single processor [tile] (“…The accelerators 320-1, 320-2, 320-3, and 320-4 execute a model training task by processing the respective sub-batch datasets 390-1, 390-2, 390-3, and 390-4 using the model computation graph 375…” para. 0047).
Cui and Kessler do not but Dally teaches tiles (“…A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package…” title, abstract).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention to modify Cui by adopt the teachings of Dally because Dally would provide multi-chip GPU to interconnect chips for graphical processing with higher performance and higher density systems (para. 0034 - 0035).
Cui, Dally and Kessler do not but Inglett teaches assign a single processor [tile] of the plurality of processor [tiles] to the compute work such that the compute work remain unpartitioned (“…Parallel computing may be implemented in architectures optimized to execute in a mode of `Single Instruction, Multiple Data` (`SIMD`)….” Para. 0005) and (“….the SIMD machine may be booted without partitions, so that all the compute nodes in the SIMD machine operate as one large operational group for parallel…” para. 0033).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention to modify Cui, Dally and Kessler by adopt the teachings of Inglett because Inglett’s SIMD method are ubiquitous on a small scale, graphical processors (para. 0007). Cui would apply the SIMD to execute on GPU with multiple chipsets or tiles as claimed for the GPU run more efficient (para. 0017).
As to claims 24 and 29, they recite similar scope of claim 5. See rejection for claim 5 above.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
(1) Cui and Dally
Applicant argued
“...However, the rebalancing operation presented in Cui does not describe analyzing the compute work by partitioning the compute work into multiple work units for processing by the processor tiles as recited by claim 1. Further, the Cui reference does not describe, upon determining that the processing of the compute work by the GPU will be more efficient with partitioning of the compute work, selecting a first set of the processor tiles to process a first work unit and a second set of the processor tiles to process a second work unit, wherein the first and second sets of the processor tiles are associated with first and second work units to optimize the processing of the compute work and processing the compute work based on the first and second work units using the first second sets of processor tiles as recited by claim 1.” (pages 7 - 11 of remark).
In response,
It is combination of Cui, Dally and Kessler, not any alone, teaches amended claim 1. The claim recites “analyzing the compute work by partitioning...”, so when Cui teaches partition, then Cui teaches analyzing... Further, Cui teaches determining an optimal job partition ratio (para. 0013). The analyzing has to be done with the determining. Cui teaches partitioning to optimize the load balance that would optimize processing the plurality of work units which would includes first and second work units (para. 0013 and 0051).
Cui does not but Dally teaches the multi-tile GPU (“Multi-Chip GPU system…” para. 0086 and figures 6. Note: chip is tile) including a plurality of processor tiles (“…A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package…” title, abstract).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention to modify Cui by adopt the teachings of Dally because Dally would provide multi-chip GPU to interconnect chips for graphical processing with higher performance and higher density systems (para. 0034 - 0035).
Cui and Dally do not but Kessler teaches select a first and second set of processor tiles (abstract and para. 0026).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention to modify Cui and Dally by adopt the teachings of Kessler because Kessler would reduce consumption of available inter-chip interconnect interface intra-chip interconnect interface memory transactions, and reduces bandwidth consumption (para. 0127).
Applicant argued
“...Applicant respectfully contends Kessler, like Dally, does not make up for any of the deficiencies of Cui. Hence, Cui, Dally, and Kessler, individually or when combined, do not teach or reasonably suggest the elements of claim 1, such as receiving compute work for processing, analyzing the compute work by partitioning the compute work into multiple work units for processing by the processor tiles, select a first set of the processor tiles to process a first work unit and a second set of the processor tiles to process a second work unit, wherein the first and second sets of the processor tiles are associated with first and second work units to optimize the processing of the compute work, and processing the compute work based on the first and second work units using the first second sets of processor tiles as recited by claim 1. Accordingly, for at least the reasons set forth above, Applicant respectfully requests the withdrawal of the rejection of claim 1 and its dependent claims.” (pages 11 – 12 of remark).
In response,
Examiner refers to response for claim 1 above. Further, Cui teaches last limitation of processing the compute work based on the first and second work units as recited by claim 1 where the accelerators 320-1 to 320-4 process the respective sub-batch datasets 390-1 – 390-4.
(2) Cui, Dally, and Inglett
Applicant argued
“...Claim 5 depends from claim 1 and thus includes all the limitations of the corresponding base claim. Accordingly, for at least the reasons set forth above with respect to claim 1, Applicant respectfully requests the withdrawal of the rejection of claim 5.” (pages 12 of remark).
In response,
Claim 5 is rejected as it depends on their rejected independent claim.
Conclusion
The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure.
Li, (US PUB 2009/0135180), discloses a method for rendering on multiple graphics processing units (GPUs) by partitioning block sequence into plurality of groups and allocating each group to a plurality of respective GPUs (title, abstract and figures 1 – 3).
Nuyttens, (US PUB 2007/0033289), discloses a method of dividing, distributing and processing graphical content (title, abstract and figures 1 – 28).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG N HOANG whose telephone number is (571)272-3763. The examiner can normally be reached 9:5-30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KEVIN YOUNG can be reached at 571-270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUONG N HOANG/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
Prosecution Insights