Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is an AIA application filed August 13, 2021.
The earliest effective filing date of this AIA application is seen as August 13, 2021, the actual filing date, there being no earlier priority applications.
The present application is also related to:
PCT international application number PCT/US22/74734 filed August 10, 2022.
The claims filed October 14, 2025 are entered, currently outstanding, and subject to examination.
This action is in response to the filing of the same date.
The current status and history of the claims is summarized below:
Last Amendment/Response
Previously
Amended:
1, 2, 5, 7, 11-15, & 19-24
1, 2, 4, 5, 7, 9, 11-16, & 18-20
Cancelled:
none
3, 8, 17 & 18
Withdrawn:
none
none
Added:
none
21-24
No changes were made to the claims.
Claims 1, 2, 4-7, 9-16, and 19-24 are currently pending and outstanding.
Regarding the last reply:
Claims 1, 2, 5, 7, 11-15, and 19-24 were amended.
No claims were cancelled.
No claims were withdrawn.
No claims were added.
Claims 1, 2, 4-7, 9-16, and 19-24 are currently outstanding and subject to examination.
As no substantial changes were made to the claims, the Response to Arguments section, below, primarily contains new portions to the examination of the instant application.
This is a final action and is the sixth action on the merits.
Allowable subject matter is not indicated below.
Often, in the substance of the action below, formal matters are addressed first, claim rejections second, and any response to arguments third.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 14, 2025 has been entered.
Special Definitions for Claim Language - MPEP § 2111.01(IV)
No special definitions are seen as present in the specification regarding the language used in the claims. Consequently, the words and phrases of the claims are given their plain meaning. MPEP §§ 2173.01, 2173.05(a), and 2111.01.
If special definitions are present, Applicant should bring those to the attention of the examiner and the prosecution history with its next response in a manner both specific and particular. In doing so, there will be no mistake, confusion, and/or ambiguity as to what constitutes the special definition(s).
To date, Applicant has provided no indication of special definitions.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o).
Applicant must provide the same terminology/vocabulary/phrasing in the specification that is present in the claims. At least one term or phrase is missing from the specification present in the claim(s).
Correction is required as the following amendment(s)/text in the claims find(s) no antecedent in the specification.
Claim(s)
Antecedent Missing For
1, 9, 19, and 20
second integrated circuit
19
first surface of a package substrate
As set forth in MPEP § 608.01(o):
The meaning of every term used in any of the claims should be apparent from the descriptive portion of the specification with clear disclosure as to its import; and in mechanical cases, it should be identified in the descriptive portion of the specification by reference to the drawing, designating the part or parts therein to which the term applies. A term used in the claims may be given a special meaning in the description. See MPEP § 2111.01 and § 2173.05(a).
Usually the terminology of the original claims follows the nomenclature of the specification, but sometimes in amending the claims or in adding new claims, new terms are introduced that do not appear in the specification. The use of a confusing variety of terms for the same thing should not be permitted.
. . . While an applicant is not limited to the nomenclature used in the application as filed, he or she should make appropriate amendment of the specification whenever this nomenclature is departed from by amendment of the claims so as to have clear support or antecedent basis in the specification for the new terms appearing in the claims. This is necessary in order to insure [sic, ensure] certainty in construing the claims in the light of the specification, Ex parte Kotler, 1901 C.D. 62, 95 O.G. 2684 (Comm’r Pat. 1901). See 37 CFR 1.75 and MPEP §§ 608.01(i), § 1302.01.
Consequently, identity between terms and phrases in the specification and claims is preferred and is seen as mandatory to ensure “certainty in construing the claims in the light of the specification”.
Applicant may have confused the formal requirement antecedent basis in the claims under 37 C.F.R. § 1.75 and the MPEP with the substantial requirement for antecedent basis and definiteness under 35 U.S.C. § 112.
Further, under 37 C.F.R. § 1.121(e) regarding disclosure consistency in making amendments:
The disclosure must be amended, when required by the Office, to correct inaccuracies of description and definition, and to secure substantial correspondence between the claims, the remainder of the specification, and the drawings.
Examiner considers direct correspondence between the specification and the claims to be important with respect to determining the scope of the claims.
Examiner strongly urges Applicant to review its claims with a fine-toothed comb and scrutinize them for any discrepancies between claim language and language that is used in the written description/specification as originally filed. Applicant is responsible for what it drafts. Discrepancies may be interpreted to Applicant’s detriment.
Applicant’s arguments are not sufficient to overcome the objection, the citations do not appear to be on target, and the objection is maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4, 5, 10-14, and 19-23 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Application Publication Appl. 20190200450 of Mellitz et al. (Mellitz).
With respect to claim 1, Mellitz discloses an apparatus (Figs. 8 and 11, ¶¶ 32 et seq., 38 et seq., circuit assemblies 800, 1100) comprising:
a first integrated circuit (Fig. 11, IC 102);
a first interposer substrate (flex circuit 1110 is seen to have some substrate, particularly to support axial port 1106);
a circuit board (multilayer PCB 1118),
at least a first portion of the circuit board (1118) being disposed between the first integrated circuit (102) and the first interposer substrate (1110, "Flex circuit 1110 is mounted by means of a BGA 1114 to the bottom layer of a multilayer PCB 1118, through which vias 1120 and 1122 are formed. As before, IC 102 is mounted to a top layer of multilayer PCB 1118 using a ball grid array 112.” Restating, interposer/flex circuit at bottom of PCB 1118 and IC 102 at the top.),
wherein the first integrated circuit is disposed above the circuit board, wherein the first interposer is disposed below the circuit board (per Fig. 11), and
wherein the first integrated circuit (102) is disposed above the circuit board (1118 and per Fig. 11),
wherein the first interposer substrate (1110) is disposed below the circuit board (1118 and per Fig. 11), and
wherein the circuit board (1118) is configured to provide electrical connection between the first interposer substrate (1110) and the first integrated circuit (102) via a connection element (BGA 112 to vias 1120) on a first surface of the first interposer (1110; ¶ 39, "In circuit assembly 1100, the high-speed data channel is routed from IC 102 through BGA 112 to vias 1120, BGA 1114, flex circuit 1110, axial port 1106, twin axial cable 1104, axial port 1108, flex circuit 1112, BGA 1118, vias 1122, layer L2, and then to connector 104.");
an interface (axial ports 1106 and 1108) disposed on a second surface of the first interposer substrate (1110, opposite the BGAs per Fig. 11; at least axial port 1106 forms an interface), and
the interface (1106/1108) being configured to provide signals from the first integrated circuit (102) to an electrical component (Connector 104; ¶ 38, "Meanwhile, at the opposing end of flexible twin axial attachment 1102 [the first end is attached to flex circuit/interposer 1110], flex circuit 1112 is mounted to the bottom layer of multilayer PCB 1118 by means of BGA 1124, which are electrically connected to vias 1122, which in turn are electrically connected to layer L2 to which connector 104 is coupled.” Connector 104 is seen as an electrical component.).
Mellitz Fig. 11 as set forth above does not disclose:
the interface being configured to provide signals from the first integrated circuit to a second integrated circuit;
and a first package substrate disposed below the first interposer substrate, wherein
(i) a first surface of the first package substrate is coupled to the second surface of the first interposer substrate,
(ii) the second integrated circuit is disposed below the first package substrate, is coupled to a second surface of the first package substrate, and is electrically coupled to the first integrated circuit through the circuit board, the first interposer substrate, and the first package substrate,
(iii) the first surface of the first interposer substrate and the second surface of the first interposer substrate are opposite surfaces of the first interposer substrate, and
(iv) the first surface of the first package substrate and the second surface of the first package substrate are opposite surfaces of the first package substrate.
By simply duplicating the circuitry (102/112) that is above the printed circuit board/PCB 1118 of Mellitz Fig. 11 to a location below the printed circuit board/PCB 1118 of Mellitz Fig. 11, parts of Mellitz are duplicated in a manner consistent with legal precedence set forth in MPEP § 2144.04(VI)(B). In doing so, all the criteria, limitations, elements, and connections of the claim are met. Mellitz shows all that is needed to inform the person of ordinary skill in the art before the effective filing date of the claimed invention what to do and the motivation/rationale is all there.
Mere duplication of parts has no distinguishing significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP § 2144.04(VI)(B).
Further, Mellitz provides for many different types of ICs (¶ 18):
"Example ICs includes central processing units (CPUs), system-on-chip (SoC) chips, including processors with SoC architectures, and Platform Controller Hubs (PCH)."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide additional ICs along the lines of Mellitz in a system according to Mellitz as set forth above in order to provide additional signal processing. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the circuit connections of Mellitz are seen as providing the person of ordinary skill in the art before the effective filing date of the claimed invention knowledge of the many different configurations available to such a second IC. Any connection configuration for a circuit element shown in Mellitz is deemed to be sufficient and adequate for connecting a second IC.
The preceding shows how a second IC may be introduced into the present analysis and its knowledge of same to the person of ordinary skill in the art before the effective filing date of the claimed invention, including connections therefor.
Shifting this same analysis to a different circuit, the one shown in Fig. 8, the same also applies to a package such as that of Fig. 8, ¶ 32, where "a package comprising multi-level BGA/chip carrier 802 and a package to board flex circuit 804". The shift here aligns with and corresponds to the shift Applicant has made in the claims over the course of prosecution. Examiner believes the analysis here is linear, but a bit tortuous in a manner similar to the claim amendment history. As can be seen above in the specification objection, elements have been included in the claims that are not explicitly set forth in the specification as originally filed.
By simply duplicating the circuitry (Fig. 8, 802, generally, including 102, 806, 808, 810, and 814) that is above the printed circuit board/PCB 812 of Mellitz Fig. 8 to a location below the printed circuit board/PCB 812 of Mellitz Fig. 8, parts of Mellitz are duplicated in a manner consistent with legal precedence set forth in MPEP § 2144.04(VI)(B). In doing so, all the criteria, limitations, elements, and connections of the claim are met. Mellitz shows all that is needed to inform the person of ordinary skill in the art before the effective filing date of the claimed invention what to do and the motivation/rationale is all there.
In duplicating the structure 802 et al. located above printed circuit board/PCB 812 for installation below the PCB 812, the following analysis is seen as valid:
Per Mellitz Fig. 8 and ¶ 32:
a first package substrate (duplicate/lower 802/804) disposed below the first interposer substrate (interposer 808 with its BGA supporting substrate. "a package comprising multi-level BGA/chip carrier 802 and a package to board flex circuit 804" that may be a duplicate of that shown in Fig. 8 and connected on a bottom portion of the PCB along the lines shown in Fig. 11 to achieve what is generally shown at Fig. 10 above the PCB; such a configuration is seen to include a duplicate/lower interposer 808 per Fig. 8), wherein
(i) a first surface (duplicate/lower 802 facing upward) of the first package substrate (duplicate/lower 802 below the PCB 812. Please note that use of the term “duplicate” is meant to indicate the corresponding duplicated part below the PCB 812. This is emphasized by the inclusion of the “/lower” designation.) is coupled to the second surface (facing downward) of the first interposer substrate (duplicate/lower 808),
(ii) the second integrated circuit (duplicate/lower 102) is disposed below the first package substrate (duplicate/lower 802), is coupled to a second surface of the first package substrate (facing downward, similarly as the second surface of the first package substrate, the one facing downward), and is electrically coupled to the first integrated circuit through the circuit board (812/1118, per the basic connections of Fig. 11 between BGA 112 AND BGA 1114), the first interposer substrate (duplicate/lower 808), and the first package substrate (duplicate/lower 802),
(iii) the first surface (with duplicated BGAs 1114 per above and situated below the PCB) of the first interposer substrate (duplicate/lower 808) and the second surface (opposite surface) of the first interposer substrate (duplicate/lower 808) are opposite surfaces of the first interposer substrate (duplicate/lower 808), and
(iv) the first surface of the first package substrate (duplicate/lower 802 surface coupled to duplicated/lower interposer 808) and the second surface of the first package substrate are opposite surfaces of the first package substrate (opposite surface).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a second, duplicate package structure with accompanying elements (810-102 on the left side of Fig. 8) along the lines of Mellitz in a system according to Mellitz as set forth above in order to provide additional signal processing and corresponding utility. This provides one rationale to combine the references.
Adding such a second, duplicate package structure with accompanying elements (810-102 on the left side of Fig. 8) along the lines of Mellitz is seen as a duplication of parts per above with connections already shown in Mellitz (Fig. 11) as well.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
the interface being configured to provide signals from the first integrated circuit to a second integrated circuit;
and a first package substrate disposed below the first interposer substrate, wherein
(i) a first surface of the first package substrate is coupled to the second surface of the first interposer substrate,
(ii) the second integrated circuit is disposed below the first package substrate, is coupled to a second surface of the first package substrate, and is electrically coupled to the first integrated circuit through the circuit board, the first interposer substrate, and the first package substrate,
(iii) the first surface of the first interposer substrate and the second surface of the first interposer substrate are opposite surfaces of the first interposer substrate, and
(iv) the first surface of the first package substrate and the second surface of the first package substrate are opposite surfaces of the first package substrate.
See also the rejection analysis of claim 1 for the immediately preceding final rejection of August 12, 2024. That analysis is seen to provide basis for the many configurations and combinations available to the person of ordinary skill in the art before the effective filing date of the claimed invention arising from Mellitz. See, particularly, page 10 bottom to page 11 top where it states:
Figs. 7-10 all show structures that are similar to and electrically equivalent to the circuit arrangement of Fig. 11. Figs. 7-10 show electrical connections on top of printed circuit board/PCB 1018/914/812/704 while Fig. 11 shows alternative and equivalent connections below PCB 1118.
From these disclosures, it can be seen that connections/installation both above and below the PCB 1118 are known from Mellitz and can be combined according to the knowledge of the person of ordinary skill in the art before the effective filing date of the claimed invention.
And page 12 bottom to page 13 top which states:
From Figs. 7-11, combining both upper and lower circuit elements on a PCB is seen as taught by Mellitz to the person of ordinary skill in the art before the effective filing date of the claimed invention
Here, Fig. 9’s top circuitry above the PCB 914 combined with that of Fig. 8 in a bottom configuration per Fig. 11 provides all the elements of claim 1.
With respect to claim 2, Mellitz as set forth above discloses the apparatus of claim 1, including one wherein
the circuit board (1118) comprises a via (vias 1120 and 1122, ¶ 38) coupling a connection element (inherent, it’s connected) of the first integrated circuit (102) to the connection element (inherent, same) on the first surface (top) of the first interposer substrate (1110).
With respect to claim 4, Mellitz as set forth above discloses the apparatus of claim 1, including one wherein
the first integrated circuit (102, Fig. 8) is disposed on a second package substrate (package 802) disposed above the circuit board (1118 and per Fig. 8).
With respect to claim 5, Mellitz as set forth above discloses the apparatus of claim 1, including one further comprising
one or more cables (twin axial cable 1104) coupled to the interface (axial port 1106) on the interposer substrate (flex circuit 1110 left),
the one or more cables (1104) being electrically coupled to the first integrated circuit (102) through the first interposer substrate (1110) and the circuit board (1118).
With respect to claim 10, Mellitz as set forth above discloses the apparatus of claim 1, including one wherein
the connection element is part of a ball grid array (BGA).
Fig. 11, BGA 1114, ¶ 38.
With respect to claim 11, Mellitz as set forth above discloses the apparatus of claim 1, including one further comprising
a second interposer substrate (flex circuit 1112) coupled to a second portion (right, Fig. 11) of the circuit board (multilayer PCB 1118),
wherein the interface (axial port 1106) is configured to communicatively couple the first interposer substrate (flex circuit 1110) and the second interposer substrate (1112).
With respect to claim 12, Mellitz as set forth above discloses the apparatus of claim 11, including one further comprising
one or more cables (twin axial cable 1104) coupled between the interface (axial port 1106) and the second interposer substrate (1112).
With respect to claim 13, Mellitz as set forth above discloses the apparatus of claim 11, including one further comprising
a pluggable module connector (¶ 19, "In FIG. 1 [and Fig. 11], connector 104 is a small form-factor pluggable (SFP) connector."),
wherein the second portion (right, Fig. 11) of the circuit board (multilayer PCB 1118) is disposed between the second interposer substrate (1112) and the pluggable module connector (connector 104).
Fig. 11.
With respect to claim 14, Mellitz as set forth above discloses the apparatus of claim 11, but not one further comprising
a third integrated circuit,
wherein the second portion of the circuit board is disposed between the second interposer substrate and the third integrated circuit.
Mere duplication of parts has no distinguishing significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP § 2144.04(VI)(B).
Duplicating the IC 102 of Mellitz Fig. 11 at generally L2 would provide additional signal processing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use an additional IC with a known general configuration along the lines of Mellitz IC 102 in a system according to Mellitz as set forth above in order to provide additional signal processing and/or distribution of same. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A).
Further, the combination would then provide:
a third integrated circuit,
wherein the second portion of the circuit board is disposed between the second interposer and the third integrated circuit.
With respect to claim 19, Mellitz as set forth above discloses a method comprising:
generating,
via a first integrated circuit,
a signal to be communicated with a second integrated circuit, providing the signal to an interposer substrate through a circuit board configured to provide electrical connection between the interposer substrate and the first integrated circuit via connection elements on a first surface of the interposer substrate, wherein at least a portion of the circuit board is disposed between the first integrated circuit and the interposer substrate, wherein the first integrated circuit is disposed above the circuit board,
wherein the interposer substrate is disposed below the circuit board,
wherein a first surface of a package substrate is coupled to a second surface of the interposer substrate, and wherein the first surface of the interposer substrate and the second surface of the interposer substrate are opposite surfaces of the interposer substrate; and
communicating,
via an interface on the second surface of the interposer substrate and via the package substrate,
the signal to the second integrated circuit,
wherein (i) the package substrate is disposed below the interposer substrate, (ii) the second integrated circuit is disposed below the package substrate,
is coupled to a second surface of the package substrate, and
is electrically coupled to the integrated circuit through the circuit board,
the interposer substrate, and the package substrate, and
(iii) the first surface of the package substrate and the second surface of the package substrate are opposite surfaces of the package substrate.
The method of claim 19 above would naturally occur in the use of a device as set forth in claim 1, above.
With respect to claim 20, Mellitz as set forth above discloses a method comprising:
disposing a first integrated circuit on a circuit board;
disposing an interposer substrate on the circuit board such that at least a portion of the circuit board is disposed between the first integrated circuit and the interposer substrate, the first integrated circuit is disposed above the circuit board, and
the interposer substrate is disposed below the circuit board,
wherein:
the circuit board is configured to provide electrical connection between the interposer substrate and the first integrated circuit via connection elements on a first surface of the interposer substrate;
and an interface is formed on a second surface of the interposer substrate, the interface being configured to provide signals from the first integrated circuit to a second integrated circuit;
and disposing a package substrate on the second surface of the interposer substrate, such that the package substrate is disposed below the interposer substrate and a first surface of the package substrate is coupled to the second surface of the interposer substrate, wherein
(i) the second integrated circuit is disposed below the package substrate, is coupled to a second surface of the package substrate, and is electrically coupled to the first integrated circuit through the circuit board, the interposer substrate, and the package substrate,
the first surface of the interposer substrate and the second surface of the interposer substrate are opposite surfaces of the interposer substrate, and
the first surface of the package substrate and the second surface of the package substrate are opposite surfaces of the package substrate.
The method of claim 20 above would naturally occur in the construction and/or manufacture of a device as set forth in claim 1, above.
With respect to claim 21, Mellitz as set forth above discloses the apparatus of claim 1, but not one further comprising
a third integrated circuit coupled to the second surface of the first interposer substrate.
Mere duplication of parts has no distinguishing significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP § 2144.04(VI)(B).
Duplicating the IC 102 of Mellitz Fig. 11 at generally L2 would provide additional signal processing and make for a third IC at the area at/about interposer 1110 with the second IC being at L2 for purposes of the combination. ICs would then be present at the upper and lower left on the PCB 1118 and another one at L2.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use an additional IC with a known general configuration along the lines of Mellitz IC 102 in a system according to Mellitz as set forth above in order to provide additional signal processing and/or distribution of same. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A).
Further, the combination would then provide:
a third integrated circuit coupled to the second surface of the first interposer substrate.
With respect to claim 22, Mellitz as set forth above discloses the apparatus of claim 1, further comprising:
a second interposer substrate (flex circuit 1112) coupled to a second portion (right, Fig. 11) of the circuit board (multilayer PCB 1118),
wherein the interface (axial port 1106) is configured to communicatively couple the first interposer substrate (flex circuit 1110) and the second interposer substrate (1112).
a third interposer substrate coupled to a third portion of the circuit board (duplication of parts per claim 14, above);
an interface disposed on a bottom surface of the second interposer substrate and configured to communicatively couple the second interposer substrate and the third interposer substrate (duplication of parts re the coupling between the first and second interposers);
a third integrated circuit (duplication of parts per claim 14, above),
wherein the second portion of the circuit board is disposed between the second interposer substrate and the third integrated circuit (duplication of parts per claim 14, above),
wherein the circuit board is further configured to provide electrical connection between the second interposer substrate and the third integrated circuit (duplication of parts per claim 1, above, and the electrical connection between the first interposer (1110) and the first integrated circuit (102)); and
a pluggable module connector (¶ 19, "In FIG. 1 [and Fig. 11], connector 104 is a small form-factor pluggable (SFP) connector."),
wherein the third portion of the circuit board is disposed between the third interposer substrate and the pluggable module connector (as the third portion of the circuit board would be as the third interposer can be on either side of the PCB and, in this case, on the same side as the second interposer 1112),
wherein the circuit board is further configured to provide electrical connection between the third interposer substrate and the pluggable module connector (PCB 1118 is seen as so configured as for via 1122).
With respect to claim 23, Mellitz as set forth above discloses the apparatus of claim 22, including one wherein
the interface disposed on the bottom surface of the second interposer substrate comprises a first one or more solder pads designated for signal communication and a second one or more solder pads designated for electrical ground.
Per ¶ 20:
"As depicted in various drawing figures herein, the use of one or more BGAs are used. A ball grid array is a type of packaging under which an array of pads arranged in a grid (the grid array) on the underside of an integrated circuit (commonly referred to as an IC or chip) are electrically coupled to a similar array of pads having the same grid configuration and patterned on an outer layer on a PCB, wherein respective pairs of pads on the IC and PCB are coupled via a solder ball. During a manufacturing process, the solder balls are melted (e.g., via a reflow operation), resulting in the respective pairs of pads being electrically coupled, enabling signals to pass from the IC to “wiring” on one or more PCB layers connected to the array of pads patterned on the surface of the PCB."
As such, solder pads are considered to be present at any solder connection.
Claim 6 is rejected under 35 U.S.C. § 103 as being unpatentable over Mellitz as set forth above in view of U.S. Patent Application Publication No. 20200037448 of Kim et al. (Kim).
With respect to claim 6, Mellitz as set forth above discloses the apparatus of claim 5, but not one wherein
the interface comprises one or more solder pads, and
wherein the one or more cables are soldered to the one or more solder pads.
Kim discloses a direct connection of high speed signals on PCB chip that includes (Figs. 2A/B, ¶ 26 and adjacent):
the interface (PCB 10) comprises one or more solder pads (at both ends of the plated through-hole vias 24, Fig. 1), and
wherein the one or more cables (high-speed cables or twinax cables 42) are soldered (ball grid array 21 made up of multiple solder balls 22) to the one or more solder pads (via end plates).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to solder pads along the lines of Kim in a system according to Mellitz as set forth above in order to connect cables in a known manner for signal transmission/reception. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A).
Further, the combination would then provide:
the interface comprises one or more solder pads, and
wherein the one or more cables are soldered to the one or more solder pads.
See also claim 23, above.
Claims 7, 9, and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over Mellitz as set forth above in view of U.S. Patent Application Publication No. 2014/0321803 of Thacker et al. (Thacker).
With respect to claim 7, Mellitz as set forth above discloses the apparatus of claim 1, but not one wherein
the first interposer substrate comprises a ground plane .
Thacker discloses a hybrid-integrated photonic chip package with an interposer that includes (¶ 87):
In some embodiments, the interposers in the preceding embodiments include passive components (such as capacitors, power and ground planes, etc.) to decouple the electrical signals. However, in other embodiments the interposers include active circuits, such as those used for signal conditioning.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use an interposer having a ground plane along the lines of Thacker in a system according to Mellitz as set forth above in order to provide electrical options and/or connections. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A).
With respect to claim 9, Mellitz as set forth above discloses the apparatus of claim 1, including one wherein
the second integrated circuit comprises an optical module .
Thacker, Fig. 11, optional optical source 160.
With respect to claim 15, Mellitz as set forth above discloses the apparatus of claim 11, but not one further comprising
one or more optical modules,
wherein the second portion of the circuit board is disposed between the second interposer substrate and the one or more optical modules.
Thacker discloses a hybrid-integrated photonic chip package with an interposer that includes:
one or more optical modules.
Fig. 8, ¶ 63 and adjacent, optical integrated circuits 128-1, -2.
Mellitz, Fig. 11, shows that circuit elements of any kind (here they are IC 102 and interposer 1110) can be attached/electrically connected across a circuit board (here, 1118).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use one or more optical modules along the lines of Thacker in a system according to Mellitz as set forth above in order to provide optical functioning/operation. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to place circuit elements on one or both sides of an intervening circuit board along the lines of Mellitz in a system according to Mellitz in view of Thacker as set forth above in order to provide manufacturing options and/or design efficiencies. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A).
Further, the combination would then provide:
one or more optical modules,
wherein the second portion of the circuit board is disposed between the second interposer and the one or more optical modules.
Claim 16 is rejected under 35 U.S.C. § 103 as being unpatentable over Mellitz as set forth above in view of U.S. Patent Application Publication No. 20210400813 of Thibado et al. (Thibado) and U.S. Patent Application Publication No. 20130273752 of Rudisill et al. (Rudisill).
With respect to claim 16, Mellitz as set forth above discloses the apparatus of claim 1, including one wherein
the interface comprises a pad array.
¶ 20 re BGAs and Fig. 11 with BGA 1114.
Mellitz as set forth above does not disclose the apparatus further comprising a socket connector configured to be coupled to the
pad array and
a cable stack coupled to the socket connector.
Thibado discloses a removable and low insertion force connector system that includes (¶ 99):
Connection pads and solder BGA can correspond to the CPU 1564, so that communication from the MB to one or more components on the RGA interposer 1560 is routed through CPU 1564. CPU 1564 can be soldered to the RGA interposer 1560 through a first upper BGA (e.g., corresponding to a CPU socket) connecting a corresponding array of connection pads on the bottom of the CPU package 1564 with a first array of upper connection pads 1572 on the top of the RGA interposer 1560.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a BGA-socket connection along the lines of Thibado in a system according to Mellitz as set forth above in order to removable connection means for pinned circuit elements. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A).
Further, the combination would then provide:
the apparatus further comprising a socket connector configured to be coupled to the pad array.
Rudisill discloses an interposer connectors with magnetic components that includes:
FIG. 34 is a partially unassembled exploded isometric view of the first electronic device with interposer installed into a case, with a variety of mating magnetic accessories such as stacking cables that are magnetically attached to the case contacts.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include stacking cables along the lines of Rudisill in a system according to Mellitz in view of Thibado in order to provide signal and/or power transmission/communication. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A).
Further, the combination would then provide:
a cable stack coupled to the socket connector.
Both magnetic and pin connection means are contemplated for the connection/coupling between the cable stack and socket connector as any known means are seen as available for such connection/coupling.
In combination, Mellitz in view of Thibado and Rudisill would provide a socket connector configured to be coupled to the
pad array and
a cable stack coupled to the socket connector.
Claim 24 is rejected under 35 U.S.C. § 103 as being unpatentable over Mellitz in view of Thacker as set forth above in view and further in view of U.S. Patent Application Publication No. 2009/0032921 of Koga (Koga).
With respect to claim 24, Mellitz as set forth above discloses the apparatus of claim 22, but not one wherein:
the second interposer substrate comprises a power plane;
and the third integrated circuit comprises a power module configured to provide power to the power plane.
Thacker discloses a hybrid-integrated photonic chip package with an interposer that includes (¶ 87):
In some embodiments, the interposers in the preceding embodiments include passive components (such as capacitors, power and ground planes, etc.) to decouple the electrical signals. However, in other embodiments the interposers include active circuits, such as those used for signal conditioning.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a second interposer having a power and/or ground plane along the lines of Thacker in a system according to Mellitz as set forth above in order to provide electrical options and/or connections. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Koga discloses a printed wiring board structure and electronic apparatus that includes (¶ 39, Fig. 7):
"The circuit component 40 is a circuit module comprising a de-coupling capacitor and a power circuit for the BGA components 20 and 30."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a power module for a circuit, including in conjunction with an integrated circuit along the lines of Koga in a system according to Mellitz in view of Thacker as set forth above in order to supply power to a circuit in a modular and spatially-efficient manner. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (a circuit apparatus) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
the second interposer comprises a power plane;
and the third integrated circuit comprises a power module configured to provide power to the power plane.
Response to Arguments
Applicant's arguments filed October 14, 2025 have been fully considered but they are not persuasive and the claim rejections are not rebutted.
Applicant argues that:
With regard to claim 1, Applicant submits that the Final Office Action fails to demonstrate that Mellitz teaches or suggests an apparatus comprising "a first integrated circuit,""a first interposer substrate,""a circuit board, at least a first portion of the circuit board being disposed between the first integrated circuit and the first interposer substrate,""an interface disposed on a second surface of the first interposer substrate, the interface being configured to provide signals from the first integrated circuit to a second integrated circuit," and "a first package substrate disposed below the first interposer substrate, wherein (i) a first surface of the first package substrate is coupled to the second surface of the first interposer substrate, (ii) the second integrated circuit is disposed below the first package substrate, is coupled to a second surface of the first package substrate, and is electrically coupled to the first integrated circuit through the circuit board, the first interposer substrate, and the first package substrate, (iii) the first surface of the first interposer su