DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/11/2025 has been entered.
Response to Amendment
Examiner acknowledges the amended claims 1 and 15 as well as amended figures 4a, and 7a-c as well as amended Specification that includes the label parts from the amended figures 4a and 7a-c.
Response to Arguments
Applicant’s arguments with respect to claim(s) claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
Previous objection has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weber (US Patent US-20150303649-A1) in the view of Hagimoto (US Patent US-20180278015-A1) hereinafter Hagimoto and Hwang (US Patent US-10418780-B1) hereinafter Hwang.
Regarding claim 1, Weber teaches a circuit (Fig. 4 equivalent circuit of integrated photonic module IPM #20 in Fig. 1-2), comprising: a top metal layer (Fig. 1 second patterned metal layer #28 in Fig. 1 corresponding to feed lines #58 and #60 in Fig. 2; see paragraph [0031]) that includes an anode and a cathode (Annotated Fig. 4 below shows that feed lines #60 and #58 are connected to the anode and cathode respectively which corresponding to second patterned layer #28 in Fig. 1); one or more capacitors connected to the anode (annotated Fig. 4 shows capacitor #54 is connected to the anode; Fig. 1 passive #36 is considered a capacitor, see paragraph [0029]); a laser connected to the anode and the cathode (Fig. 4 laser diode #48, corresponding to OE #32 in Fig. 1, is connected to the anode and cathode as seen in the annotated figure below); a driver connected to the cathode (Fig. 2 driver #52 is connected the cathode side of laser diode #48, see cathode side of #48 in annotated Fig. 4 below); a bottom metal layer arranged below the top metal layer (Fig. 1 first patterned metal layer #24 is bellowed the second patterned metal layer #28), wherein the bottom metal layer (Fig. 1 first patterned metal layer #24 ) is connected to ground (paragraph [0028] states “ first patterned metal layer 24 may be configured to serve as a ground plane” Fig. 2 shows #46 as the ground plane, see also paragraph [0031]); and a dielectric layer (Fig. 1 second insulating layer #30) separating the top metal layer and the bottom metal layer (Fig. 1 second insulating layer #30 separates metal layers #28 and #24), wherein a first surface of the top metal layer (Fig. 1 top side of metal layer 28) physically bonded to a substrate (Fig. 1 top side of metal layer 28 is physically bonded to pattern spacer 40); wherein a first surface of the dielectric layer is in physical contact with the top metal layer (annotated Fig. 1 illustrates first surface of #30 in physical contact with second patterned metal layer #28), wherein a second surface of the dielectric layer is in physical contact with the bottom metal layer (annotated Fig. 1 illustrates second surface of #30 in physical contact with first patterned metal layer #24), wherein the dielectric layer has a thickness between the first surface and the second surface (Fig. 3 shows thickness “h” of insulating layer #66 which corresponds to the second insulating layer #30 which is between transmission lines #60 & #58 -corresponding to layer #28 in Fig. 1- and ground layer #46 -corresponding to layer #24 in Fig. 1-), that is under sixty micrometers (paragraph [0036] states “when h is very small, for example 0.5 μm ,”; hence thickness is under 60 μm) and a thermal resistance between the first surface and the second surface (Fig. 1 second isolation layer #30; it is inherent that there is a thermal resistance between first and second surface of second insulation layer #30), wherein a current loop (Fig. 4 shows the current loop of the device in Figs. 1-2) flowing vertically across the dielectric layer (Figs. 3 and 4 shows the transmission lines #56; paragraph [0034] states “ The impedance -of the transmission line #56- depends on the effective dielectric constant Eeff of an insulating layer 66… ”; since the effective dielectric constant Eeff depends on the thickness “h” as seen in equation for eeff in paragraph [0034]; hence current loop #56 in Fig. 4 includes flowing vertically across the second insulation layer #30) has a self- inductance based on the thickness of the dielectric layer (it is inherent that that second insulation layer #30 in Fig. 1 would have a self- inductance based on the thickness “h”; thickness “h” of layer #30 also seen as layer #66 in Fig. 3 has a thickness of 0.5 μm which is in compliance with the Applicant); the bottom metal layer (Fig. 1 first patterned metal layer #24) is arranged to dissipate heat (it is inherent that first patterned metal layer #4 would dissipate heat for being a metallic material) generated by the current loop flowing vertically across the dielectric layer (it is inherent that current loop #56 in Fig. 4 would generate heat; current loop in Fig. 4 flows vertically across the second insulated layer #30 since the impedance of transmission line #58 depends of the dielectric thickness “h”, see paragraph [034]).
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Weber fails to teach laser is a VCSEL; thermal resistance between the first surface and the second surface is under fifteen degrees Celsius per watt; and a first surface of the top metal layer is electrically bonded to a substrate.
However, Hagimoto teaches a VCSEL (Fig. 2 LD #20; paragraph [0085] states “LD chip 20 is a vertical type LD chip having an n-side electrode arranged on one face of the substrate and a p-side electrode arranged on the other face”; therefore, LD #20 is a VCSEL); a dielectric layer (for example Fig. 2 insulating film #15a is in between first conductive layer #13 and second conductive layer #14); the dielectric layer (for example Fig. 2 insulating film #15a) has a thickness under sixty micrometers (for example paragraph [0049] states “ when the insulating film 15a is made of AlN, the insulating film 15a preferably has the film thickness equal to or greater than 0.2 μm and equal to or less than 10 μm, and more preferably has the film thickness equal to or less than 4 μm”) a thermal resistance under fifteen degrees Celsius per watt (for example Fig. 2 insulating film #15a paragraph [0049] states “ when the insulating film 15a is made of AlN, the insulating film 15a preferably has the film thickness equal to or greater than 0.2 μm and equal to or less than 10 μm, and more preferably has the film thickness equal to or less than 4 μm”; from the applicant’s specification paragraph [0051] states “may be as low as 5mm when dielectric layer 412 is made from AlON orAlN”; therefore insulating film #15a from Hagimoto has a dielectric with thermal resistance under fifteen degrees Celsius per watt because the material and its thickness is under the same specifications as the applicant).
It would have been obvious to a person of ordinary skill in the art to prior to the effective filing date of the claimed invention to modify Weber’s device by having a VCSEL as a laser as taught by Hagimoto; and the dielectric with thermal resistance under fifteen degrees Celsius per watt as taught by Hagimoto (e.g. having insulated layer #27 from Halbritter made of the same material of Hagimoto) because having a VCSEL would allow to emit light vertically; and having a dielectric as per Hagimoto teachings would prevent to have short circuits.
Weber modified device fails to teach a first surface of the top metal layer is electrically bonded to a substrate.
However, Hwang teaches a first surface of a substrate is electrically bonded to a housing (Fig. 3C shows housing 36 which is equivalent to “substrate” from Fig. 4A from the applicant is bonded to the top surface 311 of substrate 31 – substrate 31 includes a second conductive pad 3112 as seen in Fig. 4A- with bonding layer 301 which is made of metal, see column 5 lines 17-25. Since the bonding material is metallic material as the Applicant see Specification paragraph [0035] to bond the substrate 420 in Fig. 4a; hence Hwang teaches a first surface of the top metal layer is electrically bonded to a substrate). It would have been obvious to a person of ordinary skill in the art to prior to the effective filing date of the claimed invention to modify Weber in the view of Hagimoto with to add a bonding layer in order to electrically bond the first surface of the top metal to a substrate (e.g. bond 40 to the top surface of metal layer 28 from Fig. 1 of Weber with a metallic bonding layer) as taught by Hwang because having a metallic bonding layer would result to have a robust and sturdy device.
Regarding claim 2, Weber modified device teaches the circuit of claim 1, wherein the current loop flows horizontally through the one or more capacitors, the VCSEL, and the driver (from Weber Fig. 4 current loop flows horizontally because current loop #56 flows through capacitor #54, laser diode #48, and driver #52 which corresponds to #36, #32 and #34 in Fig. 1; from Hagimoto Fig. 2 LD #20; paragraph [0085] LD #20 is a VCSEL), vertically across the dielectric layer (Figs. 3 and 4 shows the transmission lines #56; paragraph [0031] states “The current loop and ground plane are connected respectively to a power supply pin (VCC) 62 and a ground pin 64 of IPM 42”; paragraph [0034] states “ The impedance -of the transmission line #56- depends on the effective dielectric constant Eeff of an insulating layer 66… ”; hence, current loop flows vertically since the effective dielectric constant Eeff depends on the thickness “h” as seen in equation for eeff), horizontally through the bottom metal layer (paragraph [0031] states “The current loop and ground plane are connected respectively to a power supply pin (VCC) 62 and a ground pin 64 of IPM 42”; the ground plane corresponds to first patterned layer #24 in Fig. 1, see paragraph [0028]; hence, current loop flows horizontally through first patterned metal layer #24), and vertically across the dielectric layer (Figs. 3 and 4 shows the transmission lines #56; paragraph [0031] states “The current loop and ground plane are connected respectively to a power supply pin (VCC) 62 and a ground pin 64 of IPM 42”; paragraph [0034] states “ The impedance -of the transmission line #56- depends on the effective dielectric constant Eeff of an insulating layer 66… ”; hence, current loop flows vertically since the effective dielectric constant Eeff depends on the thickness “h” as seen in equation for eeff).
Regarding claim 3, Weber modified device teaches the circuit of claim 1, wherein the self-inductance of the current loop (from Weber Fig. 4 current loop #56; it is inherent that current loop #56 has a self-inductance) is proportional to an area enclosed by the current loop (from Weber Fig. 4 current loop; it is inherent that the current loop would be proportional of the area from which the current flows).
Regarding claim 4, Weber modified device the circuit of claim 3, wherein the area enclosed by the current loop (from Weber Fig. 4 current loop #56; it is inherent that the current loop would be proportional of the area from which the current flows) includes a vertical dimension based on a combined thickness of the dielectric layer (from Weber paragraph [0034] states “ The impedance -of the transmission line #56- depends on the effective dielectric constant Eeff of an insulating layer 66… ”; since the effective dielectric constant Eeff depends on the thickness “h” as seen in equation for eeff, area enclose in current loop #56 includes a vertical dimension based on the thickness of the second insulated layer #30) and the top metal layer (from Weber paragraph [0031] states “The current loop and ground plane are connected respectively to a power supply pin (VCC) 62 and a ground pin 64 of IPM 42”; ground plane corresponds to first patterned metal layer #24, see paragraph [0028], therefore, area enclose in current loop #56 includes a vertical dimension based on the thickness of the first patterned metal layer #24).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weber (US Patent US-20150303649-A1) in the view of Hagimoto (US Patent US-20180278015-A1) and Hwang (US Patent US-10418780-B1), as per claim 1, in further view of Du (Foreign Patent CN-111224317-A) hereinafter Du.
Regarding claim 5, Weber modified device teaches the circuit of claim 1, further comprising: a metal-filled via (from Weber paragraph [0028] states “Layers 24, 26, 28 and 30 are patterned, using photolithography or other techniques that are known in the art of integrated circuits, to define electrical connections, as illustrated in the figures that follow. These connections typically include conductive lines, vias…or connecting an optoelectronic (OE) element 32, such as a laser diode chip, to a driver chip 34”).
Weber modified device fails to teach a first metal-filled via through the dielectric layer, to provide an electrical connection between the bottom metal layer and the driver, and a second metal-filled via, through the dielectric layer, to provide an electrical connection between the bottom metal layer and the one or more capacitors.
However, Du teaches a first metal-filled via (for example Fig. 1 first hole ground #2031), through the dielectric layer (Fig. 2 driver #101 is connected to ground layer #334, 334 in Fig. 3b is part of layer 304 in Fig. 2, through hole ground #2031; from Fig. 3b dielectric #324 is on top of ground layer #334; therefore, ground hole #2031 reaches the ground layer #334 through dielectric #324), to provide an electrical connection between the bottom metal layer and the driver (for example Fig. 2 driver #101 and first hole ground #2031; page 6 paragraph 1 states “the driving chip 101 can be connected between the output end and the grounding end”), and a second metal-filled via (for example Fig. 2 second ground hole #2032), through the dielectric layer (for example Fig. 2 capacitor #303 is connected to ground layer #334 through hole ground #2032; from Fig. 3b dielectric #324 is on top of ground layer #334; therefore, ground hole #3042 reaches the ground layer #334 through dielectric #324), to provide an electrical connection between the bottom metal layer and the one or more capacitors (for example Fig. 2 capacitor #103 and hole ground #2032; page 6 paragraph 1 states “capacitor 103 is connected with the ground terminal through the second grounding hole 2032”).
It would have been obvious to a person of ordinary skill in the art to prior to the effective filling date of the claimed invention to modify Weber’s device in the view of Hagimoto and Hwang to include first and second metal filled via through the dielectric as taught by Du (e.g. from Weber having a first via under driver #34 to connect first patterned metal layer #24 through the second insulated layer #30 and having a second via under passive #36 to connected with the first patterned metal layer #24, see figure below) because having first and second metal filled vias would allow to secure connections minimizing risk of wire disconnection.
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Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weber (US Patent US-20150303649-A1) in the view of Hagimoto (US Patent US-20180278015-A1) and Hwang (US Patent US-10418780-B1), as per claim 1, in further view of Kub (US Patent US-9246305-B1) hereinafter Kub.
Regarding claim 6, Weber modified device teaches the circuit of claim 1, wherein the thickness of the dielectric layer is twenty micrometers or less (from Weber Fig. 3 “h” is the thickness of insulating layer #66 which corresponds to the second insulated layer #30 in Fig. 1; paragraph [0036] states “when h is very small, for example 0.5 μm “).
Weber modified device fails to teach the dielectric layer includes aluminum oxynitride AlON.
However, Kub teaches the dielectric layer includes aluminum oxynitride (for example Fig. 5 dielectric layer # 515; column 9 lines 21-24 states “Dielectric layer 515 may be formed from any suitable thermally conductive material such as AlON” ). It would have been obvious to a person of ordinary skill in the art to prior to the effective filing date of the claimed invention to modify Weber’s device in the view of Hagimoto and Hwang with a dielectric made of AlON as taught by Kub because having a dielectric material made of AlON would help to dissipate the heat generated by the laser.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weber (US Patent US-20150303649-A1) in the view of Hagimoto (US Patent US-20180278015-A1) and Hwang (US Patent US-10418780-B1), as per claim 1, in further view of Toeniskoetter (US Patent US-4226626-A) hereinafter Toeniskoetter.
Regarding claim 7, Weber modified device teaches the circuit of claim 1, wherein the thickness of the dielectric layer is twenty micrometers or less (from Weber Fig. 3 “h” is the thickness of insulating layer #66 which corresponds to the second insulated layer #30 in Fig. 1; paragraph [0036] states “when h is very small, for example 0.5 μm “).
Weber modified device fails to teach the dielectric layer includes aluminum phosphate (AlPO4).
However, Toeniskoetter teaches the dielectric layer includes aluminum phosphate (for example column 4 lines 8-9 state “ the aluminum phosphate and free alkaline earth metal oxide whereby the presence of aggregate acts as a heat sink”). It would have been obvious to a person of ordinary skill in the art to prior to the effective filing date of the claimed invention to modify Weber’s device in the view of Hagimoto and Hwang with a dielectric made of aluminum phosphate because having a dielectric material made of aluminum phosphate would help to dissipate the heat generated by the laser.
Allowable Subject Matter
Claims 15-23 are allowed.
Weber in the view of Hagimoto and Vail teaches the projector module in claim 15 as per previous rejection in page 14. Weber modified device by Hagimoto and Vail fail to teach a substrate that, in combination with a printed circuit board, defines a cavity; a submount, in the cavity.
Yoo (US Patent US-12144103-B2) teaches a substrate that, in combination with a printed circuit board, defines a cavity (Fig. 3 holder 300 in combination with substrate 210 defines a cavity; substrate 210 is a printed circuit board, column 16 lines 53-54). However, Yoo fails to teach a submount, in the cavity in which the submount includes all the elements described in claim 15.
Pertinent prior art Halbritter (US Patent US-10637206-B2) and Hwang (US-10418780-B1) does not overcome the deficiencies of Weber modified device and Yoo.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDA ADRIANA CAMACHO ALANIS whose telephone number is (703)756-1545. The examiner can normally be reached Monday-Friday 7:30am-5:30pm Friday off.
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/FERNANDA ADRIANA CAMACHO ALANIS/ Examiner, Art Unit 2828
/MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828