DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 5, 2025 has been entered.
Response to Arguments
Applicant’s arguments filed November 05, 2025 have been fully considered.
Applicant Argues that the amendment presented overcomes the art of record. Examiner agrees with Applicant; however a new 103 rejection is made based on Kaji in view of Li, Kriman, Chen and Wu for Claims 1 and 17 and Kaji in view of Li, Kaji2, Kriman, Chen and Wu for Claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1,3-10, 17 are rejected as being unpatentable over 35 U.S.C. 103 over Kaji et al. US 20220344897 in view of Li et al. US 20210151949, Kriman et al. US 11374381, Chen US20200373732 and Wu et al. US 20220359427.
Regarding claim 1, Kaji teaches an Optical subassembly (Figs. 3-6), comprising:
an integrated circuit (IC) driver chip; (Fig. 3, 200 “Paragraph 0090 the laser driver 200”)
a redistribution layer (RDL) structure (See annotated Fig 6 below) that includes one or more dielectric layers (Figs. 14A-18P 161, 162, 163) that is disposed on a surface of the IC driver chip, (Fig. 6 shows the RDL is on the IC driver chip); and
a capacitor disposed over the IC driver chip; (Fig. 3, 500 Paragraph 0076 “The passive component 500 is a circuit component except for active elements such as a capacitor, an inductor, and a resistor. The passive component 500 includes a de-coupling capacitor for driving the semiconductor laser 300.”)
wherein a width of the capacitor is within a width of the IC driver chip; (See annotated Fig 3) and
a first vertical cavity surface emitting laser (VCSEL) device (Fig. 3, 300 Paragraph 0089 “the semiconductor laser 300” Paragraph 0073 “The semiconductor laser 300 is a semiconductor device that emits laser light by allowing a current to flow through a p-n junction of a compound semiconductor. Specifically, a vertical cavity surface emitting laser (VCSEL) is assumed.”) disposed over the IC driver chip on a first region of the surface of the RDL structure. (See Fig. 3 having the VSCEL be disposed over the IC driver chip. Paragraph 0103 “In the present embodiment, in order to provide a region for the connecting via 101 described above, the amount of overlap is desirably larger than 0%. On the other hand, considering that a certain number of thermal vias 102 are arranged immediately below the semiconductor laser 300, the amount of overlap is desirably 50% or less. Therefore, by setting the amount of overlap to be more than 0% and 50% or less”)
wherein a width of the VCSEL device is within the width of the IC driver chip; (See annotated Fig. 3)
the width of the capacitor and the VCSEL device is parallel with the width of the IC driver chip. (See annotated Fig. 3 below)
Kaji does not teach that the RDL structure includes a cavity, and wherein an entire width of the cavity is within an entire width of the IC driver chip and the VCSEL is disposed within the cavity of the RDL structure, the entire width of the capacitor and the entire width of the VCSEL are within an entire width of the IC driver chip and a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns.
However,
Li teaches that the RDL structure includes a cavity (Fig. 4, 405) and the VCSEL is deposed within the cavity of the RDL structure. (Fig. 6 shows that the VCSEL is within the cavity Paragraph 0027 “FIG. 6 illustrates a longitudinal sectional view of showing the VCSEL die bonded with the recessed substrate”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the RDL structure as taught by Kaji by adding the cavity as disclosed by Kaji. One of ordinary skill in the art would have been motivated to make this modification in order to easily align and place the VCSEL on the RDL. (Paragraph 0025 “A recess 405 may be created in the dielectric layer 408 formed on top of the interconnect layer to expose the portion of the interconnect metal layer 404b that is to be coated with the composite layer 406. Note that the sidewalls 407a and 407b of the recess 405 may be sloped, as shown in FIG. 4, to easily align and place the VCSEL die onto the composite layer 406 forming a first ohmic contact.”)
Kaji in combination with Li does not teach the entire width of the capacitor and the entire width of the VCSEL are within an entire width of the IC driver chip and a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns, and wherein an entire width of the cavity is within an entire width of the IC driver chip.
However,
Kriman teaches the entire width of the capacitor, the entire width of the VCSEL and the width of the entire cavity are within an entire width of the IC driver chip and the entire widths of the capacitor, the IC driver chip and the VCSEL are parallel with each other. (Fig. 2F shows the width of the VCSEL, 20 (Shown in Fig. 2C), and the width of the capacitor, 40 (Col. 4, Lines 26-28 “The redistribution layer can also be designed to accommodate surface-mounted passive components, such as coupling capacitors” Col. 6, Lines 8-10 “To complete the fabrication of device 42, surface-mounted components 40 are mounted on and connected to traces 38 in RDL 35”), in the horizontal direction, entirely within the horizontal width of the IC driver chip 22. With the IC driver being over the entire device the width of the cavity will also be within the width of the IC driver chip.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified IC driver chip as taught by Kaji by having the IC driver chip be disposed across the entire device as disclosed by Kriman. One of ordinary skill in the art would have been motivated to make this modification in order to allow dicing to occur at the wafter scale easing the manufacturing process. (Col. 4 Lines 53-58 “After fabrication, the GaAs wafer is diced to produce multiple dies 20, which are then mounted on respective dies 22 within the silicon wafer. Dicing of the silicon wafer typically takes place only after assembly of dies 20 and the other device components on dies 22, so that the process steps can all be carried out at wafer scale.”)
Kaji in combination with Lee and Kriman does not teach a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns.
However,
Chen teaches a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it. (Fig. 4B show two separate VCSEL structures with a third region between with no VCSEL disposed on it. Both VCSELs and the third region are on an RDL structure Paragraph 0036 ” In some embodiments, one or more redistribution layers (not shown) may be disposed between the TSVs 424 and the solder bumps 422 and/or one or more redistribution layers (not shown) may be disposed between the TSVs 424 and the lower contact pads 428.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified device as taught by Kaji by two VCSEL devices on an RDL structure with a third Region between them also on the RDL structure as disclosed by Chen. One of ordinary skill in the art would have been motivated to make this modification in order to emit more light from the device.
Kaji in combination with Lee, Kriman and Chen does not teach each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns,
However,
Wu teaches each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns (Wu Paragraph 0073 “For example, the dielectric layer 406B may be thinner than the dielectric layer 406A. In some embodiments, the dielectric layers of the second redistribution layers 408B each have a thickness in the range of about 2 μm to about 15 μm, although other thicknesses are possible.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have thickness of the one or more dielectric layers as taught by Kaji by having the thickness be less than or equal to 5 microns disclosed by Wu. One of ordinary skill in the art would have been motivated to make this modification in order to create shorter linear electrical pathways saving material cost. (Wu Paragraph 0075 “In some embodiments, longer linear electrical pathways are formed in the first redistribution layers 408A using thicker and/or wider metallization dimensions, while second redistribution layers 408B have overall shorter linear electrical pathways.”)
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Regarding claim 3, Kaji teaches the VCSEL device comprises:
a short-wave infrared (SWIR) VCSEL device;
an oxide confined VCSEL device;
an implant confined VCSEL device;
a mesa confined VCSEL device;
a top emitting VCSEL device; or
a bottom emitting VCSEL device.
(Paragraph 0073 “Specifically, a vertical cavity surface emitting laser (VCSEL) is assumed. In this regard, either a back-emission type or a top-emission type may be used”)
Regarding claim 4, Kaji teaches a passivation layer (Fig. 16J, 162 & 163 Paragraph 0131 “Then, the similar roughening step for the wiring pattern and the similar formation step for an interlayer insulating resin 162 are performed repeatedly.” Paragraph 0133 “Next, as illustrated in FIG. 16J, an interlayer insulating resin 163 is thermocompression-bonded by roll lamination or lamination press.” Paragraph 0120 “FIG. 14A to FIG. 18P are views each illustrating an example of the manufacturing process of the substrate 100” These figures shows that the IC driver chip is surrounded by a dielectric or passivation layer in the creation of the substrate), wherein the passivation layer is disposed on at least a portion of the surface of the IC driver chip. (Fig. 16 shows the Passivation layer disposed on both sides of the IC driver 200.)
Regarding claim 5, Kaji teaches the RDL structure includes one or more bond pads, (Fig. 13E, 260 Paragraph 0118 “Next, as illustrated in FIG. 13E, a copper land—copper wiring layer (RDL) 260 for electrical bonding is formed on the adhesion layer—seed layer 240 by a plating method.”)
wherein the one or more bond pads are disposed on respective regions of the surface of the IC driver chip. (Figs. 13E & F shows the bond pads on are disposed on their respective regions of the surface of the IC driver chip)
Regarding claim 6, Kaji teaches the RDL structure includes one or more metal layers. (Figs. 16K – 17M Paragraph 0135 “Here, the shallow via hole 171 is a filled via filled with copper plating.”)
Regarding claim 7, Kaji teaches the RDL structure includes one or more metal layers (Figs. 16K – 17M Paragraph 0135 “Here, the shallow via hole 171 is a filled via filled with copper plating.”), and
wherein the one or more metal layers and the one or more dielectric layers are arranged in an alternating order. (Fig. 17M shows the metal and dielectric layers are arranged in alternating order)
Regarding claim 8, Kaji teaches a particular metal layer, of the one or more metal layers, is configured as a ground for the VCSEL device. (Fig. 5 shows that the metal layer connects the VCSEL to ground 201)
Regarding claim 9, Kaji teaches a particular metal layer, of the one or more metal layers, is configured as a cathode for the VCSEL device. (Paragraph 0086 “The semiconductor laser 300 has an anode connected to the LDVCC terminal 203 and a cathode connected to the LDOUT 202 terminal.”)
Regarding claim 10, Kaji teaches wherein the capacitor is disposed on another region of the surface of the RDL structure that is not within the cavity of the RDL structure. (Fig. 6 shows that the capacitor is disposed on another region of the surface of the RDL structure that is not within the cavity of the RDL Structure)
Regarding claim 17, Kaji teaches An optical assembly , comprising:
a substrate (Fig. 2, 30); and
an optical subassembly that is disposed on a region of a surface of the substrate, (See annotated Fig. 2 below)
Wherein the optical subassembly comprises:
an integrated circuit (IC) driver chip; (Fig. 6, 200 “Paragraph 0090 the laser driver 200”)
a redistribution layer (RDL) structure (See annotated Fig 6 below) that includes one or more dielectric layers (Figs. 14A-18P 161, 162, 163) that is disposed on a surface of the IC driver chip, (Fig. 6 shows the RDL is on the IC driver chip); and
a capacitor disposed over the IC driver chip; (Fig. 3, 500 Paragraph 0076 “The passive component 500 is a circuit component except for active elements such as a capacitor, an inductor, and a resistor. The passive component 500 includes a de-coupling capacitor for driving the semiconductor laser 300.”)
wherein a width of the capacitor is within a width of the IC driver chip; (See annotated Fig. 3 below) and
a vertical cavity surface emitting laser (VCSEL) device (Fig. 6, 300 Paragraph 0089 “the semiconductor laser 300” Paragraph 0073 “The semiconductor laser 300 is a semiconductor device that emits laser light by allowing a current to flow through a p-n junction of a compound semiconductor. Specifically, a vertical cavity surface emitting laser (VCSEL) is assumed.”) a vertical cavity surface emitting laser (VCSEL) device (Fig. 6, 300 Paragraph 0089 “the semiconductor laser 300” Paragraph 0073 “The semiconductor laser 300 is a semiconductor device that emits laser light by allowing a current to flow through a p-n junction of a compound semiconductor. Specifically, a vertical cavity surface emitting laser (VCSEL) is assumed.”) disposed over the IC driver chip. (See annotated Fig. 3 below Paragraph 0103 “In the present embodiment, in order to provide a region for the connecting via 101 described above, the amount of overlap is desirably larger than 0%. On the other hand, considering that a certain number of thermal vias 102 are arranged immediately below the semiconductor laser 300, the amount of overlap is desirably 50% or less. Therefore, by setting the amount of overlap to be more than 0% and 50% or less”)
wherein a width of the VCSEL device is within the width of the IC driver chip; (See annotated Fig. 3 below)
the width of the capacitor and the VCSEL device is parallel with the width of the IC driver chip. (See annotated Fig. 3 below)
Kaji does not teach that the RDL structure includes a cavity and wherein an entire width of the cavity is within an entire width of the IC driver chip and the VCSEL is deposed within the cavity of the RDL structure the entire width of the capacitor and the entire width of the VCSEL are within an entire width of the IC driver chip and a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns..
However,
Li teaches that the RDL structure includes a cavity (Fig. 4, 405) and the VCSEL is deposed within the cavity of the RDL structure. (Fig. 6 shows that the VCSEL is within the cavity Paragraph 0027 “FIG. 6 illustrates a longitudinal sectional view of showing the VCSEL die bonded with the recessed substrate”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the RDL structure as taught by Kaji by adding the cavity as disclosed by Kaji. One of ordinary skill in the art would have been motivated to make this modification in order to easily align and place the VCSEL on the RDL. (Paragraph 0025 “A recess 405 may be created in the dielectric layer 408 formed on top of the interconnect layer to expose the portion of the interconnect metal layer 404b that is to be coated with the composite layer 406. Note that the sidewalls 407a and 407b of the recess 405 may be sloped, as shown in FIG. 4, to easily align and place the VCSEL die onto the composite layer 406 forming a first ohmic contact.”)
Kaji in combination with Lee does not teach the entire width of the capacitor and the entire width of the VCSEL are within an entire width of the IC driver chip and a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns, and wherein an entire width of the cavity is within an entire width of the IC driver chip.
However,
Kriman teaches the entire width of the capacitor, the entire width of the VCSEL and the width of the entire cavity are within an entire width of the IC driver chip and the entire widths of the capacitor, the IC driver chip and the VCSEL are parallel with each other. (Fig. 2F shows the width of the VCSEL, 20 (Shown in Fig. 2C), and the width of the capacitor, 40 (Col. 4, Lines 26-28 “The redistribution layer can also be designed to accommodate surface-mounted passive components, such as coupling capacitors” Col. 6, Lines 8-10 “To complete the fabrication of device 42, surface-mounted components 40 are mounted on and connected to traces 38 in RDL 35”), in the horizontal direction, entirely within the horizontal width of the IC driver chip 22. With the IC driver being over the entire device the width of the cavity will also be within the width of the IC driver chip.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified IC driver chip as taught by Kaji by having the IC driver chip be disposed across the entire device as disclosed by Kriman. One of ordinary skill in the art would have been motivated to make this modification in order to allow dicing to occur at the wafter scale easing the manufacturing process. (Col. 4 Lines 53-58 “After fabrication, the GaAs wafer is diced to produce multiple dies 20, which are then mounted on respective dies 22 within the silicon wafer. Dicing of the silicon wafer typically takes place only after assembly of dies 20 and the other device components on dies 22, so that the process steps can all be carried out at wafer scale.”)
Kaji in combination with Lee and Kriman does not teach a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns.
However,
Chen teaches a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it. (Fig. 4B show two separate VCSEL structures with a third region between with no VCSEL disposed on it. Both VCSELs and the third region are on an RDL structure Paragraph 0036 ” In some embodiments, one or more redistribution layers (not shown) may be disposed between the TSVs 424 and the solder bumps 422 and/or one or more redistribution layers (not shown) may be disposed between the TSVs 424 and the lower contact pads 428.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified device as taught by Kaji by two VCSEL devices on an RDL structure with a third Region between them also on the RDL structure as disclosed by Chen. One of ordinary skill in the art would have been motivated to make this modification in order to emit more light from the device.
Kaji in combination with Lee, Kriman and Chen does not teach each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns,
However,
Wu teaches each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns (Wu Paragraph 0073 “For example, the dielectric layer 406B may be thinner than the dielectric layer 406A. In some embodiments, the dielectric layers of the second redistribution layers 408B each have a thickness in the range of about 2 μm to about 15 μm, although other thicknesses are possible.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have thickness of the one or more dielectric layers as taught by Kaji by having the thickness be less than or equal to 5 microns disclosed by Wu. One of ordinary skill in the art would have been motivated to make this modification in order to create shorter linear electrical pathways saving material cost. (Wu Paragraph 0075 “In some embodiments, longer linear electrical pathways are formed in the first redistribution layers 408A using thicker and/or wider metallization dimensions, while second redistribution layers 408B have overall shorter linear electrical pathways.”)
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Claim 2 is rejected as being unpatentable over 35 U.S.C. 103 over Kaji, Li, Kriman, Chen and Wu in view of Ouchi et al. US 6222868
Regarding claim 2, Kaji teaches the IC driver chip is made of a semiconductor wafer (Paragraph 0114 “First, as illustrated in FIG. 12A, an input/output (I/O) pad 210 including, for example, aluminum or the like is formed on a semiconductor wafer.”)
Kaji does not teach the IC driver chip comprises at least one of the specific semiconductors:
silicon (Si);
indium phosphide (InP); or
gallium arsenide (GaAs).
However,
Ouchi teaches the IC driver chip comprises at least one of the specific semiconductors:
silicon (Si);
indium phosphide (InP); or
gallium arsenide (GaAs).
(Col. 11, Lines 42-43 “Si substrate with an integrated circuit thereon is performed.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor of the IC driver chip as taught by Kaji by having it be made of Silicon as disclosed by Ouchi. One of ordinary skill in the art would have been motivated to make this modification in order to reduce cost in manufacturing. (Ouchi Col. 11 Lines 19-23 “In the third embodiment, the optical device and an integrated circuit fabricated on the Si substrate 12 can be provided on a common substrate, and hence an opto-electronic integrated device can be constructed at a relatively inexpensive cost.”)
Claims 11, 14, 16 are rejected as being unpatentable over 35 U.S.C. 103 over Kaji in view of Li Kaji US 20220294181 (herein after referred to Kaji2) Kriman and Chen and Wu.
Regarding claim 11, Kaji teaches An optical assembly, comprising:
a substrate (Fig. 2, 30);
an optical subassembly that is disposed on a region of a surface of the substrate (See annotated Fig. 2 below which is disposed on the surface of the substrate);
a housing that is disposed on another region of the surface of the substrate; (See annotated Fig. 2 below using the definition of on as “used as a function word to indicate position in close proximity with” see pertinent art #1)
a first support component of the housing (Fig. 4, 600 left side); and
an optical element that is disposed on a second support component (Fig. 4, 600 right side) of the housing, (Fig. 4, 700 Paragraph 0081 “The upper surface surrounded by the side wall 600 is covered by a diffuser plate 700.”)
Wherein the optical subassembly comprises:
an integrated circuit (IC) driver chip; (Fig. 6, 200 “Paragraph 0090 the laser driver 200”)
a redistribution layer (RDL) structure (See annotated Fig 6 below) that includes one or more dielectric layers (Figs. 14A-18P 161, 162, 163) that is disposed on a surface of the IC driver chip, (Fig. 6 shows the RDL is on the IC driver chip); and
a capacitor disposed over the IC driver chip; (Fig. 3, 500 Paragraph 0076 “The passive component 500 is a circuit component except for active elements such as a capacitor, an inductor, and a resistor. The passive component 500 includes a de-coupling capacitor for driving the semiconductor laser 300.”)
wherein a width of the capacitor is within a width of the IC driver chip; (See annotated Fig. 3 below) and
a vertical cavity surface emitting laser (VCSEL) device (Fig. 6, 300 Paragraph 0089 “the semiconductor laser 300” Paragraph 0073 “The semiconductor laser 300 is a semiconductor device that emits laser light by allowing a current to flow through a p-n junction of a compound semiconductor. Specifically, a vertical cavity surface emitting laser (VCSEL) is assumed.”) a vertical cavity surface emitting laser (VCSEL) device (Fig. 6, 300 Paragraph 0089 “the semiconductor laser 300” Paragraph 0073 “The semiconductor laser 300 is a semiconductor device that emits laser light by allowing a current to flow through a p-n junction of a compound semiconductor. Specifically, a vertical cavity surface emitting laser (VCSEL) is assumed.”) disposed over the IC driver chip. (See annotated Fig. 3 below Paragraph 0103 “In the present embodiment, in order to provide a region for the connecting via 101 described above, the amount of overlap is desirably larger than 0%. On the other hand, considering that a certain number of thermal vias 102 are arranged immediately below the semiconductor laser 300, the amount of overlap is desirably 50% or less. Therefore, by setting the amount of overlap to be more than 0% and 50% or less”)
wherein a width of the VCSEL device is within the width of the IC driver chip; (See annotated Fig. 3 below) and
the width of the capacitor and the VCSEL device is parallel with the width of the IC driver chip. (See annotated Fig. 3 below)
Kaji does not teach that the RDL structure includes a cavity and wherein an entire width of the cavity is within an entire width of the IC driver chip and the VCSEL is deposed within the cavity of the RDL structure a another optical element which is the first optical element that is disposed on a first support component of the housing the entire width of the capacitor and the entire width of the VCSEL are within an entire width of the IC driver chip and a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns.
However,
Li teaches that the RDL structure includes a cavity (Fig. 4, 405) and the VCSEL is deposed within the cavity of the RDL structure. (Fig. 6 shows that the VCSEL is within the cavity Paragraph 0027 “FIG. 6 illustrates a longitudinal sectional view of showing the VCSEL die bonded with the recessed substrate”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the RDL structure as taught by Kaji by adding the cavity as disclosed by Kaji. One of ordinary skill in the art would have been motivated to make this modification in order to easily align and place the VCSEL on the RDL. (Paragraph 0025 “A recess 405 may be created in the dielectric layer 408 formed on top of the interconnect layer to expose the portion of the interconnect metal layer 404b that is to be coated with the composite layer 406. Note that the sidewalls 407a and 407b of the recess 405 may be sloped, as shown in FIG. 4, to easily align and place the VCSEL die onto the composite layer 406 forming a first ohmic contact.”)
Kaji in combination with Lee does not teach a another optical element which is the first optical element that is disposed on a first support component of the housing the entire width of the capacitor and the entire width of the VCSEL are within an entire width of the IC driver chip and a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns, and wherein an entire width of the cavity is within an entire width of the IC driver chip..
However,
Kaji2 teaches a another optical element (Fig. 4, 610 Collimator Lens) which is the first optical element that is disposed on a first support component of the housing; (Fig. 4 is attached to the frame)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the optical assembly as taught by Kaji by adding the optical element as disclosed by Kaji2. One of ordinary skill in the art would have been motivated to make this modification in order to collimate the light. (Paragraph 0059)
Kaji in combination with Lee and Kaji2 does not teach the entire width of the VCSEL are within an entire width of the IC driver chip and a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns, and wherein an entire width of the cavity is within an entire width of the IC driver chip..
However,
Kriman teaches the entire width of the capacitor, the entire width of the VCSEL and the width of the entire cavity are within an entire width of the IC driver chip and the entire widths of the capacitor, the IC driver chip and the VCSEL are parallel with each other. (Fig. 2F shows the width of the VCSEL, 20 (Shown in Fig. 2C), and the width of the capacitor, 40 (Col. 4, Lines 26-28 “The redistribution layer can also be designed to accommodate surface-mounted passive components, such as coupling capacitors” Col. 6, Lines 8-10 “To complete the fabrication of device 42, surface-mounted components 40 are mounted on and connected to traces 38 in RDL 35”), in the horizontal direction, entirely within the horizontal width of the IC driver chip 22. With the IC driver being over the entire device the width of the cavity will also be within the width of the IC driver chip.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified IC driver chip as taught by Kaji by having the IC driver chip be disposed across the entire device as disclosed by Kriman. One of ordinary skill in the art would have been motivated to make this modification in order to allow dicing to occur at the wafter scale easing the manufacturing process. (Col. 4 Lines 53-58 “After fabrication, the GaAs wafer is diced to produce multiple dies 20, which are then mounted on respective dies 22 within the silicon wafer. Dicing of the silicon wafer typically takes place only after assembly of dies 20 and the other device components on dies 22, so that the process steps can all be carried out at wafer scale.”)
Kaji in combination with Lee, Kaji2 and Kriman does not teach a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it and wherein each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns.
Chen teaches a second VCSEL disposed on a second region and a third region between the first and second region that does not comprise a VCSEL device on it. (Fig. 4B show two separate VCSEL structures with a third region between with no VCSEL disposed on it. Both VCSELs and the third region are on an RDL structure Paragraph 0036 ” In some embodiments, one or more redistribution layers (not shown) may be disposed between the TSVs 424 and the solder bumps 422 and/or one or more redistribution layers (not shown) may be disposed between the TSVs 424 and the lower contact pads 428.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified device as taught by Kaji by two VCSEL devices on an RDL structure with a third Region between them also on the RDL structure as disclosed by Chen. One of ordinary skill in the art would have been motivated to make this modification in order to emit more light from the device.
Kaji in combination with Lee, Kaji2, Kriman and Chen does not teach each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns,
However,
Wu teaches each of the one or more dielectric layers has a thickness that is less than or equal to 5 microns (Wu Paragraph 0073 “For example, the dielectric layer 406B may be thinner than the dielectric layer 406A. In some embodiments, the dielectric layers of the second redistribution layers 408B each have a thickness in the range of about 2 μm to about 15 μm, although other thicknesses are possible.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have thickness of the one or more dielectric layers as taught by Kaji by having the thickness be less than or equal to 5 microns disclosed by Wu. One of ordinary skill in the art would have been motivated to make this modification in order to create shorter linear electrical pathways saving material cost. (Wu Paragraph 0075 “In some embodiments, longer linear electrical pathways are formed in the first redistribution layers 408A using thicker and/or wider metallization dimensions, while second redistribution layers 408B have overall shorter linear electrical pathways.”)
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Regarding claim 14, Kaji teaches the second optical element is at least one of a diffractive optical element (DOE) or a diffuser and is attached to the second support component via an attachment material. (Paragraph 00142 “a frame 600 and the diffuser plate 700 are attached.”)
Regarding claim 16, Kaji teaches the optical subassembly is connected to the substrate via an attachment material that comprises at least one of:
silver-epoxy (Ag-epoxy);
sintered Ag-epoxy;
semi-sintered Ag-epoxy; or
a solder.
(Fig. 2 shows the substrate and the optical subassembly are connected. Paragraph 0141 “Also, a cream solder may be printed and applied as a connection terminal on a land for external connection, and a ball grid array (BGA) of a solder ball may be mounted”)
Claim 12 is rejected as being unpatentable over 35 U.S.C. 103 over Kaji, Li, Kaji2, Kriman, Chen and Wu in view of Pelley et al. US 20090263143
Regarding claim 12, Kaji does not teach the substrate is a lead frame or an open-cavity ceramic substrate.
However,
Pelley teaches the substrate is a lead frame or an open-cavity ceramic substrate. (Paragraph 0053 “The singulated IC die may be packaged into integrated circuit packages. In one embodiment, a die would be positioned on a lead frame”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate as taught by Kaji by having it be a lead frame substrate as disclosed by Pelley. One of ordinary skill in the art would have been motivated to make this modification in order to more effectively dissipate heat and reduce cost in manufacturing.
Claim 13 is rejected as being unpatentable over 35 U.S.C. 103 over Kaji, Li, Kaji2, Kriman, Chen and Wu in view of Maxik US 20070285926
Regarding claim 13, Kaji in combination with Kaji teaches the first optical element is a collimating lens (Kaji2 Fig. 4, 610 collimator lens) and is attached to the first support component.(Fig. 4 shows the lens is attached to the first support)
Kaji does not teach the lens is a plastic lens and ultrasonic welds or one or more laser welds are used to attach the support.
However,
Maxik teaches the lens is a plastic lens and ultrasonic welds or one or more laser welds are used to attach the support. (Paragraph 0044 “the lens 18 are each made of a plastic material, and are fixedly secured together by an ultrasonic weld that”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the lens as taught by Kaji by having it be a plastic lens attached via ultrasonic weld as disclosed by Maxik. One of ordinary skill in the art would have been motivated to make this modification in order to secure the lens to frame and allow certain wavelengths of light through the lens.
Claim 15 is rejected as being unpatentable over 35 U.S.C. 103 over Kaji, Li, Kaji2, Kriman, Chen, and Wu in view Yang et al. US 20210273403.
Regarding claim 15, Kaji does not teach a conductive trace, wherein:
the conductive trace is disposed on a surface of the housing and is electrically connected to the optical subassembly and a conductive path associated with at least one of the first optical element or the second optical element.
(Fig. 9A, 460 Paragraph 0036 “A first electrical conducting layer 460 connects the conducting layer of the optical component 350 and the electrical conducting member 442.”)
However,
Yang teaches a conductive trace (Fig. 9A, 442), wherein:
the conductive trace is disposed on a surface of the housing (Fig. 9A shows the trace disposed on an inside surface of the housing) and is electrically connected to the optical subassembly (Fig. 9A shows the trace line connected to circuit board 32 which is connected to a semiconductor chip which is a light emitting chip this trace which means it is electrically connected to the optical subassembly) and a conductive path associated with at least one of the first optical element or the second optical element. (Fig. 9A, 460 Paragraph 0036 “A first electrical conducting layer 460 connects the conducting layer of the optical component 350 and the electrical conducting member 442.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the optical assembly as taught by Kaji by adding the conductive trace as disclosed by Yang. One of ordinary skill in the art would have been motivated to make this modification in order to provide power to the optical component.
Claim 18 is rejected as being unpatentable over 35 U.S.C. 103 over Kaji, Li, Kriman, Chen and Wu in view of Pelley.
Regarding claim 18, Kaji does not teach the substrate is a lead frame or an open-cavity ceramic substrate.
However,
Pelley teaches the substrate is a lead frame or an open-cavity ceramic substrate. (Paragraph 0053 “The singulated IC die may be packaged into integrated circuit packages. In one embodiment, a die would be positioned on a lead frame”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate as taught by Kaji by having it be a lead frame substrate as disclosed by Pelley. One of ordinary skill in the art would have been motivated to make this modification in order to more effectively dissipate heat and reduce cost in manufacturing.
Claim 19 is rejected as being unpatentable over 35 U.S.C. 103 over Kaji, Li, Kriman, Chen and Wu in view of Maxik.
Regarding claim 19, Kaji teaches comprising a housing (Fig. 4, 600) and an optical element (Fig. 4, 700), wherein:
the optical element is attached to the housing (Fig. 4 shows 700 and 600 are attached)
Kaji does not teach the optical element is plastic and ultrasonic welds or one or more laser welds are used to attach the support.
However,
However,
Maxik teaches the optical element is a plastic lens and ultrasonic welds or one or more laser welds are used to attach the support. (Paragraph 0044 “the lens 18 are each made of a plastic material, and are fixedly secured together by an ultrasonic weld that”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the optical element as taught by Kaji by having it be a plastic lens attached via ultrasonic weld as disclosed by Maxik. One of ordinary skill in the art would have been motivated to make this modification in order to secure the lens to frame and allow certain wavelengths of light through the lens and have collimated light.
Claim 20 is rejected as being unpatentable over 35 U.S.C. 103 over Kaji, Li, Kriman, Chen and Wu in view of Johnson et al. US 20190296522
Regarding claim 20, Kaji teaches a housing (Fig. 4, 600) and a optical element (Fig. 4, 700), wherein:
the optical element is attached to the housing via an attachment material. (Fig. 4 shows that 700 and 600 are attached and if attached there must be an attachment material)
Kaji does not teach the optical element is made of glass.
However,
Johnson teaches the optical element is made of glass. (Paragraph 0075 “A diffuser can consist of ground glass, or can be a structure etched or embossed into a glass or polymer material.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the optical element as taught by Kaji by having it be made of glass as disclosed by Johnson. One of ordinary skill in the art would have been motivated to make this modification in order to allow certain wavelengths of light through the optical element.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/STEPHEN SUTTON KOTTER/Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828