DETAILED ACTION
This office action addresses Applicant’s response filed on 4 February 2026. Claims 1, 3-13, 16-18, and 21-24 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-11, 13, 16-18, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizrahi (US 2017/0010892) in view of Aga (US 2021/0374055), Yu (US 2016/0049195), Kesiraju (US 2020/0272597), and Cheng (US 10,541,205).
Regarding claim 1, Mizrahi discloses a memory device (Fig. 1), comprising:
a memory array (¶36); and
programmable circuitry comprising control logic circuitry configured to access data stored in the memory array (¶¶20, 36);
the programmable circuitry configured to be programmed using manifest loop instructions received from an external instruction set processor (Fig. 1, decode 32 receives instructions from fetch 28, which in turn receives them from processor L1 instruction cache 40; ¶40, parallelization circuitry may be run on a separate processing core; ¶¶201, 204),
wherein once programmed, the periphery circuitry is configured to autonomously access data stored in the memory array in accordance with the received manifest loop instructions (¶206), wherein the programmable circuitry is configured to receive the manifest loop instructions from the external instruction set processor, and derive, by the control logic circuitry of the programmable circuitry a set of input parameters and a set of output parameters in accordance with the manifest loop instructions and control operation of the input logic circuitry of the periphery circuitry in accordance with the derived set of input parameters and operation of the output logic circuitry of the periphery circuitry in accordance with the derived set of output parameters (¶¶49, 164, 201, 202, 203, 210, 213, 229).
Mizrahi does not appear to explicitly disclose that the memory device is a non-volatile memory device configured for in-memory processing, that the programmable circuitry is monolithically integrated with the non-volatile memory array on a same chip, that the control logic circuitry is configured to process the data stored in the non-volatile memory array and to perform on-chip logical compute operations, and once programmed, the programmable circuitry is configured to autonomously process the data stored in the non-volatile memory array in accordance with the received manifest loop instructions; periphery circuitry monolithically integrated with the programmable circuitry and the non-volatile memory array on the same chip, comprising input logic circuitry disposed adjacent to the non-volatile memory array at a first lateral side and connected to word lines as a word line driver to drive word lines and to control writing of data to the non-volatile memory array, output logic circuitry disposed adjacent to the non-volatile memory array at a second lateral side and connected to bit lines as a bit line driver to drive bit lines and to control reading of data from the non-volatile memory array, and control logic circuitry of the programmable circuitry disposed at one of lateral sides of the non-volatile memory array.
Aga discloses a non-volatile memory device configured for in-memory processing (¶¶3, 6), comprising: a non-volatile memory array of bit cells (Fig. 6; ¶3); programmable circuitry monolithically integrated with the non-volatile memory array on a same chip and comprising control logic circuitry configured to access and process data stored in the non-volatile memory array and to perform on-chip logical compute operations (Fig. 6, ACU and PIM execution unit), wherein once programmed, the programmable circuitry is configured to autonomously access and process the data stored in the non-volatile memory array in accordance with the received instructions (¶¶6, 7, 77); and
periphery circuitry monolithically integrated with the programmable circuitry and the non-volatile memory array on the same chip and comprising: input logic circuitry disposed adjacent to the non-volatile memory array at a first lateral side and connected to word lines as a word line driver to drive word lines and to control writing of data to the non-volatile memory array, output logic circuitry disposed adjacent to the non-volatile memory array at a second lateral side and connected to bit lines as a bit line driver to drive bit lines and to control reading of data from the non-volatile memory array (Fig. 6, row and column selectors and decoders), and
wherein the programmable circuitry is configured to: derive, by the control logic circuitry of the programmable circuitry disposed at one of lateral sides of the non-volatile memory array, a set of input parameters and a set of output parameters in accordance with the instructions; and control operation of the input logic circuitry of the periphery circuitry in accordance with the derived set of input parameters and operation of the output logic circuitry of the periphery circuitry in accordance with the derived set of output parameters (Fig. 6, ACU, row/col selectors and decoders; ¶101).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi and Aga, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of improving computation latency by locating data processing elements near data storage. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mizrahi discloses a processing system that transmits loop instructions to a separate processor that accesses data stored in a memory for executing the loop instructions. Aga teaches that the memory architecture should include the address generation and processing elements in order to avoid the need to transfer data far from the memory. The teachings of Aga are directly applicable to Mizrahi in the same way, so that Mizrahi would similarly integrate the processing elements with the memory to improve computation latency.
If Aga is found to be unclear about the input and output circuitry, Yu discloses periphery circuitry monolithically integrated with the non-volatile memory array on the same chip (Fig. 1) and comprising input logic circuitry disposed adjacent to the non-volatile memory array at a first lateral side and connected to word lines as a word line driver to drive word lines and to control writing of data to the non-volatile memory array (¶10), output logic circuitry disposed adjacent to the non-volatile memory array at a second lateral side and connected to bit lines as a bit line driver to drive bit lines and to control reading of data from the non-volatile memory array (¶14), and control logic circuitry of the programmable circuitry disposed at one of lateral sides of the non-volatile memory array (Fig. 1, circuitry 14 or 28). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, and Yu, because doing so would have involved merely the routine the routine combination of known elements according to known techniques, or the use of a known technique to improve similar devices in the same way, to achieve the predictable results of correctly selecting memory cells for read/write operations. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mizrahi discloses a processing system that includes a memory. As discussed above, Aga teaches a memory having wordlines and bitlines, integrated with logic circuitry. Persons having ordinary skill in the art would recognize that memory logic circuitry conventionally comprises wordline and bitline drivers connected to the wordlines and bitlines, respectively, to control read/write operations for specific memory cells, as taught by Yu. The teachings of Yu are directly applicable to Mizrahi in the same way, so that Mizrahi’s memory would similarly include wordline and bitline drivers to perform read/write operations on the correct memory cells.
If Mizrahi is found to be unclear on the programmable circuitry receiving the manifest loop instructions from an instruction set processor, Kesiraju also discloses these limitations (¶¶35, 36). In particular, Kesiraju teaches that vector instructions are passed from an instruction set processor to a coprocessor, which decodes the instructions and performs corresponding memory access (load/store) operations. It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Yu, and Kesiraju, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of speeding up execution of vector operations by a conventional instruction set processor. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mizrahi discloses programmable circuitry that receives manifest loop instructions, derives memory access parameters from the instructions, and performs memory access operations in accordance with the derived parameters. Notably, Mizrahi’s programmable circuitry can be implemented in various ways, such as any subunit of a processor, or a separate processing core, and receives the instructions from the processor instruction cache and fetch unit. Kesiraju further teaches that the instructions can be part of an instruction set that is a subset of the instruction set of a processor, and that the instructions are transmitted from the instruction set processor to a coprocessor (which then decodes the instructions and performs memory access operations, analogously to Mizrahi’s programmable circuitry). The teachings of Kesiraju are directly applicable to Mizrahi in the same way, so that Mizrahi’s programmable circuitry would similarly be embodied in a coprocessor that receives loop instructions from an instruction set processor, enabling acceleration of loop memory accesses for the instruction set processor.
If Aga is found to be unclear regarding the integration of periphery circuitry, programmable circuitry, and the non-volatile memory being monolithic integration, Cheng discloses that such monolithic integration is conventional (col. 3, lines 46-34). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Yu, Kesiraju, and Cheng, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of conventional monolithic integration of multiple IC types on the same chip, thus improving packaging and communication speed. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mizrahi discloses programmable circuitry, such as an FPGA, communicating with a memory array. Aga teaches that the memory array architecture should include the programmable circuitry, and Cheng teaches conventional monolithic devices including FPGA and memory on the same chip. The teachings of Cheng are directly applicable to Mizrahi in the same way, so that Mizrahi’s FPGA and memory would similarly be monolithically integrated on the same chip, in the conventional manner, to achieve improved communication speed and packaging.
Regarding claim 7, Mizrahi discloses that the periphery circuitry is arranged to select one or more groups of consecutive rows of the memory array in accordance with the set of parameters (¶¶164, 201, 202, 207, 210, 213, 218, 229). Specifically, Mizrahi reads multiple contiguous memory blocks (cache lines), and multiple cache lines, using a periodic pattern of memory addresses. ‘Row’ can be chosen to be any direction in the memory. If Mizrahi is found to be unclear about rows, Yu discloses the same (Fig. 1). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Kesiraju, Cheng, and Yu, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using accessing conventional memory arrays. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mizrahi discloses a memory array. Memory arrays are conventionally arranged and addressed by rows and columns, as evidenced by Yu. The application of conventional row/column memory array addressing to Mizrahi would involve merely the direct application of the conventional arrangement to Mizrahi’s memory array, so that Mizrahi’s memory array would similarly be arranged/addressed in rows/columns.
Regarding claim 8, Mizrahi discloses that the periphery circuitry is arranged to select one or more groups of consecutive columns of the memory array in accordance with the set of parameters (¶¶164, 201, 202, 207, 210, 213, 218, 229). Specifically, Mizrahi reads multiple contiguous memory blocks (cache lines), and multiple cache lines, using a periodic pattern of memory addresses. ‘Column’ can be chosen to be any direction in the memory. If Mizrahi is found to be unclear about columns, Yu discloses the same (Fig. 1). Motivation to combine remains consistent with claim 7.
Regarding claim 9, Mizrahi discloses that the output logic circuitry arranged to select columns of the memory array, and wherein the programmable circuitry is configured to control the operation of the output logic circuitry in accordance with the manifest loop instructions (¶¶35, 164, 201, 202, 207, 210, 213, 218, 229). Specifically, Mizrahi reads multiple contiguous memory blocks (cache lines), and multiple cache lines, using a periodic pattern of memory addresses. ‘Column’ can be chosen to be any direction in the memory. If Mizrahi is found to be unclear about columns, Yu discloses the same (Fig. 1). Motivation to combine remains consistent with claim 7.
Regarding claim 10, Mizrahi discloses that the input logic circuitry arranged to select rows to the memory array, and wherein the programmable circuitry is configured to control the operation of the input logic circuitry in accordance with the manifest loop instructions (¶¶35, 49, 164, 201, 202, 207, 210, 213, 218, 229). Specifically, Mizrahi reads multiple contiguous memory blocks (cache lines), and multiple cache lines, using a periodic pattern of memory addresses. ‘Row’ can be chosen to be any direction in the memory. If Mizrahi is found to be unclear about rows, Yu discloses the same (Fig. 1). Motivation to combine remains consistent with claim 7.
Regarding claim 11, Mizrahi discloses that the programmable circuitry is configured, during operation, to derive an output set of parameters for the output logic (¶¶35, 164, 201, 202, 229).
Regarding claim 13, Mizrahi does not appear to explicitly disclose that the memory array is a two- or a higher-dimensional array. However, conventional memories are two- or higher-dimensional arrays, as evidenced by Yu (Fig. 1). Motivation to combine remains consistent with claim 7.
Regarding claim 16, Mizrahi discloses a method for controlling the operation of the non-volatile memory device according to claim 1, the method comprising: obtaining the manifest loop instructions from the external instruction set processor (Fig. 1, decode 32 receives instructions from fetch 28, which in turn receives them from processor L1 instruction cache 40; ¶40, parallelization circuitry may be run on any suitable subunits of the processor, or a separate processing core; ¶¶201, 204); deriving the set of parameters based on the manifest loop instructions (¶¶201, 202, 213, 229); and controlling the operation of the memory macro in accordance with the set of parameters (¶¶201, 202, 206, 216).
If Mizrahi is found to be unclear on the programmable circuitry receiving the manifest loop instructions from an instruction set processor, Kesiraju also discloses these limitations (¶¶35, 36). Motivation to combine remains consistent with claim 1.
Regarding claim 17, Mizrahi (Fig. 1) and Aga (¶¶2, 4) disclose a processing system comprising the non-volatile memory device according to claim 1. Motivation to combine remains consistent with claim 1.
Regarding claim 18, Mizrahi discloses that the programmable circuitry comprises a field programmable gate array (¶46).
Regarding claim 23, Mizrahi does not appear to explicitly disclose that the non-volatile memory array comprises one of a resistive random access memory, an oxide-based random access memory, a phase change memory, a spin-transfer torque magnetic random access memory, and a spin-orbit torque magnetic random access memory. Yu discloses the same (¶9). Motivation to combine remains consistent with claim 1.
Claim(s) 3, 12, 21, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizrahi in view of Aga, Yu, Kesiraju, Cheng, Fu (“Stride Directed Prefetching in Scalar Processors”), and Sassone (US 2013/0185516).
Regarding claim 3, Mizrahi discloses that the manifest loop instructions implements a loop structure formed by one or more loop iterators (¶¶201, 202), and wherein the set of parameters comprise: a memory address pattern that indicates for cells to access in the memory array, a number of loop iterations that indicates a number of times that the manifest loop instructions are to be executed according to the loop iterator, and a stride that indicates how to derive a next memory address for bit cells from the memory address pattern for a subsequent value of the loop iterator (¶¶202, 213, 229). As discussed above, Aga (¶3) and Yu (¶9) disclose that the memory is a non-volatile memory. Motivation to combine remains consistent with claim 1.
If Mizrahi is found to be unclear regarding manifest loop instructions implementing a loop structure formed by one or more loop iterators, Fu discloses the same (p. 103, Fig. 1). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Yu, Kesiraju, Cheng, and Fu, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of parallelizing load instructions for common loop structures. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mizrahi teaches parallelizing loads in program loops by determining a predictable address pattern accessed by repeated load instructions in the loop. Persons having ordinary skill in the art would recognize that such loops with predictable repeated loads would constitute typical manifest loop instructions formed by one or more loop iterators, and Fu provides explicit disclosure of the same. The teaching of Fu are directly applicable to Mizrahi in the same way, so that Mizrahi would similarly parallelize loads in typical manifest loop instructions.
If Mizrahi is found to be unclear regarding the set of parameters comprising a memory address pattern that indicates for cells to access in the memory array, a number of loop iterations that indicates a number of times that the manifest loop instructions are to be executed according to the loop iterator, and a stride that indicates how to derive a next memory address for bit cells from the memory address pattern for a subsequent value of the loop iterator, Sassone also discloses the same (¶¶28, 29). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Yu, Kesiraju, Cheng, Fu, and Sassone, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of improving accuracy and efficiency of prefetching data accessed in manifest loop instructions. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mizrahi discloses parallelizing memory accesses in manifest loop instructions by determining memory address patterns, stride, and number of loop iterations. Sassone similarly teaches that when memory accesses are determined to be part of manifest loop instructions that have fixed control flow, the accuracy and efficiency of prefetching data for memory accesses can be improved by determining memory address patterns, stride, and number of loop iterations. The teachings of Sassone are directly applicable to Mizrahi in the same way, so that Mizrahi would similarly improve efficiency and accuracy of memory accesses in manifest loop instructions by prefetching data using determined address patterns, stride, and number of loop iterations.
Regarding claim 12, Mizrahi discloses that the memory address pattern (U) comprises a column selection pattern (Uc) and a row selection pattern (Ur) (¶¶164, 201, 202, 207, 210, 213, 218, 229). Specifically, Mizrahi reads multiple contiguous memory blocks (cache lines), and multiple cache lines, using a periodic pattern of memory addresses. If Mizrahi is found to be unclear about rows and columns, Yu discloses the same (Fig. 1). Motivation to combine remains consistent with claims 3 and 7.
Regarding claim 21, Mizrahi discloses that the manifest loop instructions implement a loop structure (¶¶201, 202), but does not appear to explicitly disclose that the loop structure comprises two for-loops nested in one another, each for-loop containing a loop iterator, and wherein a loop condition of each for-loop is data independent and formed by the loop iterators associated with each for-loop, but these limitations are strongly implied because Mizrahi discloses more complex access patterns such as reading two or more columns from an array (e.g. matrix) (¶203), which persons having ordinary skill in the art would recognize is performed by nested loops iterating through rows and columns of the matrix. This form of loop is typical in the art, and is disclosed, for example, in Fu (p. 103, Fig. 1). Sassone also discloses data-independent loop conditions (¶¶29, 32). Motivation to combine remains consistent with claim 3.
Regarding claim 22, Mizrahi discloses that the manifest loop instructions implement a loop structure formed by one or more loop iterators (¶206), and wherein the manifest loop instructions comprise the loop structure characterized by a static control flow of accessing the data, and wherein the static control is independent of the data (¶202).
If Mizrahi is found to be unclear regarding manifest loop instructions implementing a loop structure formed by one or more loop iterators, and the manifest loop instructions comprising the loop structure characterized by a static control flow of accessing the data, and wherein the static control is independent of the data, Fu discloses the same (p. 103, Fig. 1). If Mizrahi and Fu are found to be unclear regarding the manifest loop instructions comprising the loop structure characterized by a static control flow of accessing the data, and wherein the static control is independent of the data, Sassone discloses the same (¶¶28, 29, 32). Motivation to combine remains consistent with claim 3.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizrahi in view of Aga, Yu, Kesiraju, Cheng, Fu, Sassone, and Alexander (US 2020/0210187).
Regarding claim 4, Mizrahi discloses that the logic circuitry is configured to perform a logical shift operation and to store the memory address pattern and wherein the control logic circuitry is configured to shift the stored memory address pattern in the logic circuitry in accordance with the stride parameter (¶¶202, 213). If Mizrahi is found to be unclear regarding these limitations, Alexander discloses the same (¶147). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Yu, Kesiraji, Cheng, Fu, Sassone, and Alexander, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of loading data without needing to compute new memory addresses. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mizrahi discloses parallelizing memory accesses by reading from multiple addresses shifted by an offset, or stride. Alexander teaches that stride functionality allows shifting memory addresses to subsequent data without requiring separate arithmetic computation of the new memory addresses. The teachings of Alexander are directly applicable to Mizrahi in the same way, so that Mizrahi would similarly use stride functionality to shift memory addresses so that separate arithmetic computation of new addresses is unnecessary.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizrahi in view of Aga, Yu, Kesiraju, Cheng, and Adams (US 2014/0149818).
Regarding claim 5, Mizrahi does not appear to explicitly disclose that the logic circuitry comprises one or more rotating shift registers or one or more chains of shift registers. Adams discloses the same (¶43). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Yu, Kesiraju, Cheng, and Adams, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using conventional shift registers to shift values. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mizrahi discloses shifting an addresses by a stride. Adams discloses that addresses can be provided by rotating shift registers. The teachings of Adams are directly applicable to Mizrahi in the same way, so that Mizrahi would similarly use rotating shift registers to shift the addresses.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizrahi in view of Aga, Yu, Kesiraju, Cheng, Adams, and Chirca (US 2020/0371800).
Regarding claim 6, Mizrahi discloses that the control logic circuitry is configured to control the shifting (¶¶202, 213), but does not appear to explicitly disclose that the one or more rotating shift registers or the one or more chains of shift registers are hierarchically stacked. Adams discloses the one or more rotating shift registers or the one or more chains of shift registers (¶43). Motivation to combine remains consistent with claim 5. Chirca further discloses that the registers are hierarchically stacked (claims 1 and 4). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Yu, Kesiraju, Cheng, Adams, and Chirca, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using nested shift registers to shift addresses for a loop. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Mizrahi discloses shifting addresses based on loop instructions. Adams discloses providing addresses using rotating shift registers. Chirca discloses that registers should be hierarchically stacked to handle nested loops. The teachings of Adams and Chirca are directly applicable to Mizrahi in the same way, so that Mizrahi would similarly use hierarchically stacked rotating shift registers to shift addresses for nested loops.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizrahi in view of Aga, Yu, Kesiraju, Cheng, Fu, Sassone, and Gschwind (US 2007/0186077).
Regarding claim 24, Mizrahi does not appear to explicitly disclose that the set of parameters further comprises a mask that indicates a confinement of the memory address pattern. Gschwind discloses these limitations (¶200). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Mizrahi, Aga, Yu, Kesiraju, Cheng, Fu, Sassone, and Gschwind, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of ensuring valid memory addresses for loads. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Mizrahi discloses parallelizing multiple loads from memory by generating memory addresses based on a memory address pattern and stride. Gschwind discloses that generated addresses should be modified by a mask based on the boundary of the storage area so that the address is valid. The teachings of Gschwind are directly applicable to Mizrahi in the same way, so that Mizrahi’s generated addresses would be masked to confine accesses to the valid storage area.
Response to Arguments
Applicant's arguments filed 4 February 2026 have been fully considered but they are not persuasive.
Amended limitations are addressed above in the new grounds of rejection, and are not further addressed here.
As an initial matter, although Applicant highlights that the rejection involves five references, the number of references applied is not, on its own, an indication of non-obviousness. That is especially the case here, where references such as Kesiraju, Cheng, and even Yu are used for explicit clarification of features that persons having ordinary skill in the art would recognize as conventional or already present in the other references, such as the instruction set processor, monolithic integration, or the memory input/output circuitry.
Applicant asserts that Mizrahi fails to teach programmable circuitry that controls operation of the memory. Remarks 8. The examiner disagrees. The cited portions of Mizrahi are explicitly directed to determining memory access parameters for load and store operations. For example, ¶¶205-206 disclose that the programmable circuitry identifies sequences of repetitive load instructions and the predictable pattern of addresses being read from, and then accesses the plurality of addresses. Thus, Mizrahi clearly discloses programmable circuitry controller operation of the memory.
Applicant asserts that Yu is silent as to the input logic circuitry and output logic circuitry. Remarks 9. The examiner disagrees. Yu ¶10 explicitly discloses a write circuit in each word line driver, and ¶14 explicitly discloses a read circuit in each word line driver and each bit line driver. Thus, Yu clearly discloses the input logic circuitry and output logic circuitry. Furthermore, the claimed input logic circuitry and output logic circuitry are conventional; memories use input and output logic to activate specific wordlines and bitlines to perform read/write operations.
Applicant asserts that Asnaashari and Cheng fail to teach monolithically integrating the periphery circuitry, programmable circuitry, and the non-volatile memory array on the same chip. Remarks 9. The examiner disagrees. Cheng does not only disclose general monolithic integration, as asserted by Applicant, but also explicitly teaches the monolithic integration of processors, memory, ASICs, and programmable logic (col. 3, lines 48-51), which is directly applicable to Mizrahi’s memory and programmable logic. Furthermore, periphery circuitry (the word/bit line drivers/control) are conventionally integrated with the memory array, as taught by Yu.
Conclusion
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19 June 2026
/ARIC LIN/ Examiner, Art Unit 2851
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