Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed 16 July 2025. Claim 1, 8, 9, 13, 20 have been amended. Claims 7, 10, 18-19 have been canceled. Claims 1-6, 8-9, 11-17, 20 are pending and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4, 6, 8-9, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruestle et al. (US 2015/0262074 A1) in view of Sharma et al. (US 11,586,966 B2) and further in view of Yang et al. (US 2004/0193719 A1) and Mukerjee et al. (US 2009/0112905 A1).
Claim 1. Bruestle discloses a computer-implemented method for controlling a classical computer comprising one or more classically-executable-nodes of a classical-quantum hybrid algorithm, wherein the classical computer is operatively coupled to a quantum computer, a classical computer, comprising a plurality of classical computers linked via a network, and a quantum computer are communicably interconnected (P 0020, 0021 Fig 1), the method comprising:
sending, by the one or more classically-executable-nodes, a first-circuit to the quantum computer for evaluation, a problem input to a quantum computer to be evaluated (P 0017) is expressed as a logic circuit and a set of constrained inputs and/or outputs into a form that can be analyzed by the quantum computer to be solved (P 0022) the representation of the circuit is converted by a classical computer (P 0030) into the appropriate form for the specific quantum computer (P 0063);
receiving a first-circuit-evaluation of the first-circuit from the quantum computer, the results are retrieved from the quantum computer (P 0064) and interpreted by the classical computer (P 0065);
processing, by the one or more classically-executable-nodes, the first-circuit evaluation during a first-time interval, the results of the quantum computer are interpreted by the classical computer (P 0065).
Bruestle does not explicitly disclose sending, by the one or more classically-executable-nodes, a second-circuit to the quantum computer for evaluation, by the quantum computer, at least in part during the first-time-interval; and receiving a second-circuit-evaluation of the second-circuit, from the quantum computer, for processing by the one or more classically-executable-nodes, as disclosed in the claims. However, Bruestle discloses the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). That is, at least the circuit problem being evaluated is changed and the process is repeated, Bruestle does not explicitly disclose that the changed circuit problem is a second circuit problem, and while it is obvious that the process would be repeated during a same time interval, this is not explicitly disclosed in Bruestle. In the same field of invention, Sharma discloses modifications are made to a quantum computing circuit template over a period of time and an analysis is performed of the quantum computing program over the course of development over the period of time (C 3 L 14-26) the quantum computing programs may be one or more programs (C 19 L 4-10) or multiple versions of the quantum computing program (Claim 1) the analysis performed on a quantum computer (C 20 L 50-58). Therefore, considering the teachings of Bruestle and Sharma, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine sending, by the one or more classically-executable-nodes, a second-circuit to the quantum computer for evaluation, by the quantum computer, at least in part during the first-time-interval; and receiving a second-circuit-evaluation of the second-circuit, from the quantum computer, for processing by the one or more classically-executable-nodes with the teachings of Bruestle with the motivation to provide an improved method for developing quantum computing programs and providing results for modifications to or integration of different programs or versions of a program (Sharma: C 1 L 21-34).
Bruestle does not disclose sending a plurality of quantum circuits, comprising the first-circuit and the second-circuit, to a circuit-buffer of the classical computer; selecting a quantum-circuit of the plurality of quantum circuits; sending, if a value of a buffer-counter satisfies a threshold-value, the selected quantum-circuit to the quantum computer for: storage in a fixed-length-buffer; and evaluation by the quantum computer; and incrementing the value of the buffer-counter by one, as disclosed in the claims. However, Bruestle discloses the classical computer loops through the inputs (P 0027) and assigns a unique number to intermediate results (P 0028) the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). Sharma discloses operational data for the quantum computing program in an experimental archive comprising datasets of returned results (C 20 L 59-65) modifying the quantum computing program (C 20 L 66 – C 21 L 8) storing additional operational data (C 21 L 17-30). In the same field of invention, Yang discloses status of a transmission buffer is determined as the number additional data packets that could be stored or as the number of data packets currently stored for a fix size buffer (P 0016) the number of stored packets is compared to a first capacity threshold (P 0017) the number of additional data packets that could be stored in the transmission buffer is compared to a second capacity threshold (P 0018) a data packet counter is incremented for each data packed removed from the transmission buffer, if the packet counter is greater than or equal to an established packet counter threshold, a flow control message is issued (P 0020). Therefore, considering the teachings of Bruestle, Sharma and Yang, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine sending a plurality of quantum circuits, comprising the first-circuit and the second-circuit, to a circuit-buffer of the classical computer; selecting a quantum-circuit of the plurality of quantum circuits; sending, if a value of a buffer-counter satisfies a threshold-value, the selected quantum-circuit to the quantum computer for: storage in a fixed-length-buffer; and evaluation by the quantum computer; and incrementing the value of the buffer-counter by one with the teachings of Bruestle and Sharma with the motivation to ensure that data is transmitted from one processor to an execution processor in a manner to expedite execution when processing resources are available.
Bruestle does not disclose wherein the selecting of the quantum-circuit is based on a selection-policy comprising: partitioning the plurality of quantum circuits into respective partitions based on identifying, for each respective circuit of the plurality of quantum circuits, a common originating node of the one or more classically-executable-nodes; determining a number of circuits present in each respective partition; and selecting the selected quantum-circuit from a respective partition with the determined number of circuits that is smallest, as disclosed in the claims. However, in the same field of invention, Mukerjee discloses raw baseline features from a broad range of sources are identified in an input signal and are aggregated, abstracted and indexed for later retrieval or manipulation (P 0022) sequences of indexed features are clustered together to form a sequence or pattern for indexing and represented as a vector (P 0026) buffers are accessed to process the sequence of feature indexes associated with a particular data set to generate one or more clusters, then a graph-like data structure is assembled with all of the clusters being tied to a common node that is associated with and indexed to the underlying data (P 0034) feature indexes are compared to identify common nodes with one or more feature indexes associated with the sequence either as leaf nodes or as clusters of leaf nodes with a common root node (P 0065) and node clusters from a common node can be split into a new root node (P 0067). Therefore, considering the teachings of Bruestle, Sharma, Yang and Mukerjee, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine wherein the selecting of the quantum-circuit is based on a selection-policy comprising: partitioning the plurality of quantum circuits into respective partitions based on identifying, for each respective circuit of the plurality of quantum circuits, a common originating node of the one or more classically-executable-nodes; determining a number of circuits present in each respective partition; and selecting the selected quantum-circuit from a respective partition with the determined number of circuits that is smallest with the teachings of Bruestle, Sharma and Yang with the motivation to provide an improved data storage method that avoids redundant storage that provides better efficiency and flexibility (Mukerjee: P 0003, 0004).
Claim 2. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, and the combination of Bruestle in view of Sharma discloses processing, by the one or more classically-executable-nodes, the second-circuit-evaluation during a second-time interval; sending, by the one or more classically-executable-nodes, a third-circuit to the quantum computer for evaluation, by the quantum computer, at least in part during the first-time-interval and/or the second-time-interval; and receiving a third-circuit-evaluation of the third-circuit, from the quantum computer, for processing by the one or more classically-executable-nodes, with the motivation used in the rejection of Claim 1. Sharma discloses wherein the visualization component updates the quantum state visualization based on respective modifications associated with the multiple versions of the quantum computing program, and wherein the quantum state visualization depicts the characterization at: a first time prior to a first modification within the period of time, a second time of the first modification within the period of time, and a third time a second modification within the period of time (Claim 3). Sharma discloses that first, second and third versions of the program can be analyzed over first, second and third periods of time.
Claim 4. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, and the combination of Bruestle and Sharma disclose wherein the one or more classically-executable-nodes comprise: a first-node configured to: send the first-circuit to the quantum computer; receive the first-circuit-evaluation from the quantum computer; and process the first-circuit-evaluation during the first-time interval, and a second-node, different than the first-node, the second-node configured to: send the second-circuit to the quantum computer for evaluation at least in part during the first-time-interval; receive the second-circuit-evaluation from the quantum computer; and process the second-circuit-evaluation, with the same motivation used in the rejection of Claim 1. Bruestle discloses the classical computer 20 may comprise one or more processors (P 0019) the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). Sharma discloses a computer may comprise multiple processors for parallel processing (C 31 L 7-15) for analyzing multiple programs or versions of a program (Claim 3).
Claim 6. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, and the combination of Bruestle in view of Sharma discloses tagging the first-circuit with a first-circuit-repeat-count; sending the first-circuit to the quantum computer for evaluation a plurality of times in accordance with the first-circuit-repeat-count; and receiving and processing a plurality of first-circuit-evaluations, with the same motivation used in the rejection of Claim 1. Bruestle discloses intermediate results are labeled (P 0027, 0028 Claim 6) the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). Sharma discloses execution statistics can be provided including the date and/or time of a run operation, the date and/or time of a returned result, and/or a runtime), statistics regarding a subject backend device, the number of iterations performed (C 16 L 66 – C 17 L 8).
Claim 7. Canceled.
Claim 8. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, but Bruestle does not disclose receiving the first-circuit-evaluation of the first-circuit from the quantum computer; decrementing the value of the buffer-counter by one; and checking the circuit-buffer for a further quantum-circuit, as disclosed in the claims. Bruestle discloses the classical computer loops through the inputs (P 0027) and assigns a unique number to intermediate results (P 0028) the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). Sharma disclose operational data for the quantum computing program in an experimental archive comprising datasets of returned results (C 20 L 59-65) modifying the quantum computing program (C 20 L 66 – C 21 L 8) storing additional operational data (C 21 L 17-30). Yang discloses status of a transmission buffer is determined as the number additional data packets that could be stored or as the number of data packets currently stored for a fix size buffer (P 0016) the number of stored packets is compared to a first capacity threshold (P 0017) the number of additional data packets that could be stored in the transmission buffer is compared to a second capacity threshold (P 0018) a data packet counter is incremented for each data packed removed from the transmission buffer, if the packet counter is greater than or equal to an established packet counter threshold, a flow control message is issued (P 0020). Therefore, considering the teachings of Bruestle, Sharma, Yang and Mukerjee, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine the first-circuit-evaluation of the first-circuit from the quantum computer; decrementing the value of the buffer-counter by one; and checking the circuit-buffer for a further quantum-circuit with the teachings of Bruestle, Sharma, Yang and Mukerjee with the motivation to ensure that data is transmitted from one processor to an execution processor in a manner to expedite execution when processing resources are available.
Claim 9. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, Bruestle discloses the classical computer loops through the inputs (P 0027) and assigns a unique number to intermediate results (P 0028) the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). Sharma disclose operational data for the quantum computing program in an experimental archive comprising datasets of returned results (C 20 L 59-65) modifying the quantum computing program (C 20 L 66 – C 21 L 8) storing additional operational data (C 21 L 17-30). Yang discloses status of a transmission buffer is determined as the number additional data packets that could be stored or as the number of data packets currently stored for a fix size buffer (P 0016) the number of stored packets is compared to a first capacity threshold (P 0017) the number of additional data packets that could be stored in the transmission buffer is compared to a second capacity threshold (P 0018) a data packet counter is incremented for each data packed removed from the transmission buffer, if the packet counter is greater than or equal to an established packet counter threshold, a flow control message is issued (P 0020). Therefore, considering the teachings of Bruestle, Sharma, Yang and Mukerjee, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine wherein the value of the buffer-counter satisfies the threshold-value if the value of the buffer-counter corresponds to a number of quantum-circuits present in the fixed-length-buffer that is less than a capacity of the fixed-length-buffer with the teachings of Bruestle, Sharma, Yang and Mukerjee with the motivation to ensure that data is transmitted from one processor to an execution processor in a manner to expedite execution when processing resources are available.
Claim 10. Canceled.
Claim 12. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, and Bruestle discloses wherein the classical-quantum hybrid algorithm is one or more of: a Variational Quantum Eigensolver; an optimization algorithm; and a quantum processor benchmarking algorithm, systems and methods to solve optimization problems (P 0017) the classical computer may optimize the circuit (P 0026).
Claim(s) 13-15, 17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruestle et al. (US 2015/0262074 A1) in view of Sharma et al. (US 11,586,966 B2) and further in view of Mukerjee et al. (US 2009/0112905 A1).
Note: Claim 13 is directed to the same limitations as Claim 1, but are recited from the perspective of receiving by and sending from the quantum processor unit.
Claim 13. Bruestle discloses a computer-implemented method for controlling a quantum computer comprising a quantum-processor-unit, the method comprising:
receiving a plurality of quantum-circuits from one or more classically-executable-nodes of a classical-quantum hybrid algorithm, wherein the plurality of quantum-circuits comprises a first-circuit and a second-circuit, a problem input to a quantum computer to be evaluated (P 0017) is expressed as a logic circuit and a set of constrained inputs and/or outputs into a form that can be analyzed by the quantum computer to be solved (P 0022) the representation of the circuit is converted by a classical computer (P 0030) into the appropriate form for the specific quantum computer (P 0063);
evaluating, using the quantum-processor-unit, the first-circuit to determine a first-circuit-evaluation, the results are retrieved from the quantum computer (P 0064) and interpreted by the classical computer (P 0065);
sending the first-circuit-evaluation to the at least one or more classically-executable-nodes for processing during a first-time-interval, the results of the quantum computer are interpreted by the classical computer (P 0065).
Bruestle does not explicitly disclose evaluating, using the quantum-processor-unit, the second-circuit to provide a second-circuit-evaluation, wherein the evaluating of the second-circuit occurs, at least in part, during the first-time-interval; and sending the second-circuit-evaluation to the at least one or more classically-executable-nodes for processing during a second-time-interval, as disclosed in the claims. However, Bruestle discloses the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). That is, at least the circuit problem being evaluated is changed and the process is repeated, Bruestle does not explicitly disclose that the changed circuit problem is a second circuit problem, and while it is obvious that the process would be repeated during a same time interval, this is not explicitly disclosed in Bruestle. In the same field of invention, Sharma discloses modifications are made to a quantum computing circuit template over a period of time and an analysis is performed of the quantum computing program over the course of development over the period of time (C 3 L 14-26) the quantum computing programs may be one or more programs (C 19 L 4-10) or multiple versions of the quantum computing program (Claim 1) the analysis performed on a quantum computer (C 20 L 50-58). Therefore, considering the teachings of Bruestle and Sharma, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine evaluating, using the quantum-processor-unit, the second-circuit to provide a second-circuit-evaluation, wherein the evaluating of the second-circuit occurs, at least in part, during the first-time-interval; and sending the second-circuit-evaluation to the at least one or more classically-executable-nodes for processing during a second-time-interval with the teachings of Bruestle with the motivation to provide an improved method for developing quantum computing programs and providing results for modifications to or integration of different programs or versions of a program (Sharma: C 1 L 21-34).
Bruestle does not disclose storing the plurality of quantum-circuits in a circuit-buffer of the quantum computer; selecting a quantum-circuit, of the plurality of quantum-circuits, based on a selection-policy; evaluating the selected quantum-circuit to determine a selected-quantum-circuit evaluation; and sending the selected-quantum-circuit-evaluation to the at least one or more classically executable- nodes for processing, as disclosed in the claims. However, Sharma disclose operational data for the quantum computing program in an experimental archive comprising datasets of returned results (C 20 L 59-65) modifying the quantum computing program (C 20 L 66 – C 21 L 8) storing additional operational data (C 21 L 17-30). Therefore, considering the teachings of Bruestle and Sharma, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine storing the plurality of quantum-circuits in a circuit-buffer of the quantum computer; selecting a quantum-circuit, of the plurality of quantum-circuits, based on a selection-policy; evaluating the selected quantum-circuit to determine a selected-quantum-circuit evaluation; and sending the selected-quantum-circuit-evaluation to the at least one or more classically executable- nodes for processing with the teachings of Bruestle and Sharma with the motivation to provide an improved method for developing quantum computing programs and providing results for modifications to or integration of different programs or versions of a program (Sharma: C 1 L 21-34).
Bruestle does not disclose, wherein the selection-policy comprises: partitioning the plurality of quantum-circuits into respective partitions based on identifying, for each respective circuit of the plurality of quantum circuits, a common originating node of the one or more classically-executable-nodes; determining a number of circuits present in each respective partition; and selecting the selected quantum-circuit from a respective partition with the determined number of circuits that is smallest, as disclosed in the claims. However, in the same field of invention, Mukerjee discloses raw baseline features from a broad range of sources are identified in an input signal and are aggregated, abstracted and indexed for later retrieval or manipulation (P 0022) sequences of indexed features are clustered together to form a sequence or pattern for indexing and represented as a vector (P 0026) buffers are accessed to process the sequence of feature indexes associated with a particular data set to generate one or more clusters, then a graph-like data structure is assembled with all of the clusters being tied to a common node that is associated with and indexed to the underlying data (P 0034) feature indexes are compared to identify common nodes with one or more feature indexes associated with the sequence either as leaf nodes or as clusters of leaf nodes with a common root node (P 0065) and node clusters from a common node can be split into a new root node (P 0067). Therefore, considering the teachings of Bruestle, Sharma, Yang and Mukerjee, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine wherein the selecting of the quantum-circuit is based on a selection-policy comprising: partitioning the plurality of quantum circuits into respective partitions based on identifying, for each respective circuit of the plurality of quantum circuits, a common originating node of the one or more classically-executable-nodes; determining a number of circuits present in each respective partition; and selecting the selected quantum-circuit from a respective partition with the determined number of circuits that is smallest with the teachings of Bruestle, Sharma and Yang with the motivation to provide an improved data storage method that avoids redundant storage that provides better efficiency and flexibility (Mukerjee: P 0003, 0004).
Claim 14. Bruestle and Sharma disclose the method of claim 13, and the combination of Bruestle in view of Sharma discloses receiving a third-circuit, of the plurality of quantum-circuits, from the one or more classically-executable-nodes; evaluating, using the quantum-processor-unit, the third-circuit to provide a third-circuit-evaluation, wherein the evaluating of the third-circuit occurs, at least in part, during the first-time-interval and/or the second-time-interval; and sending the third-circuit-evaluation to the at least one or more classically-executable-nodes for processing, with the motivation used in the rejection of Claim 13. Sharma discloses wherein the visualization component updates the quantum state visualization based on respective modifications associated with the multiple versions of the quantum computing program, and wherein the quantum state visualization depicts the characterization at: a first time prior to a first modification within the period of time, a second time of the first modification within the period of time, and a third time a second modification within the period of time (Claim 3). Sharma discloses that first, second and third versions of the program can be analyzed over first, second and third periods of time.
Claim 15. Bruestle and Sharma disclose the method of claim 13, and the combination of Bruestle in view of Sharma discloses wherein the first-circuit is received from a first-node of the one or more classically-executable-nodes and the second-circuit is received from a second-node of the one or more classically-executable-nodes and the first-node is different than the second-node, with the same motivation used in the rejection of Claim 13. Bruestle discloses the classical computer 20 may comprise one or more processors (P 0019) the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). Sharma discloses a computer may comprise multiple processors for parallel processing (C 31 L 7-15) for analyzing multiple programs or versions of a program (Claim 3).
Claim 17. Bruestle and Sharma disclose the method of claim 13, and Bruestle discloses the circuit problem is evaluated, and the results interpreted, but if no solution is found, then constraints of the circuit problem may be changed and the process repeated (P 0069). That is, at least the circuit problem being evaluated is changed and the process is repeated. Sharma discloses execution statistics can be provided including the date and/or time of a run operation, the date and/or time of a returned result, and/or a runtime), statistics regarding a subject backend device, the number of iterations performed (C 16 L 66 – C 17 L 8). Therefore, considering the teachings of Bruestle and Sharma, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine receiving the first-circuit with a first-circuit-repeat-count; evaluating the first-circuit a plurality of times in accordance with the first-circuit-repeat-count; and sending a plurality of first-circuit-evaluations to the at least one or more classically-executable-nodes for processing with the teachings of Bruestle and Sharma with the motivation to provide an improved method for developing quantum computing programs and providing results for modifications to or integration of different programs or versions of a program (Sharma: C 1 L 21-34).
Claim 18, 19. Canceled.
Claim 20 is directed to a computing system similar to the computer-implemented method claim of Claim 13 and is rejected with the same rationale.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruestle et al. (US 2015/0262074 A1) in view of Sharma et al. (US 11,586,966 B2) and Yang et al. (US 2004/0193719 A1) and Mukerjee et al. (US 2009/0112905 A1) further in view of de Beaudrap et al. (US 11,146,339 B1).
Claim 3. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, but Bruestle does not disclose wherein the classical-quantum hybrid algorithm has a structure corresponding to a directed acyclic graph with: vertices formed from the one or more classically-executable-nodes; and edges formed from a plurality of quantum-circuits comprising the first-circuit and the second-circuit, as disclosed in the claims. However, in the same field of invention, de Beaudrap discloses a classical control system formed of a network of nodes (C 15 L 25-31) on which a linear networking solution is applied, but also correspond to the location of qubits of a hardware platform in a quantum network graph that has edges for which an operation is possible (C 15 L 46-53) represented as a directed acyclic graph (C 15 L 66 – C 16 L 2). Therefore, considering the teachings of Bruestle, Sharma, Yang, Mukerjee and de Beaudrap, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine wherein the classical-quantum hybrid algorithm has a structure corresponding to a directed acyclic graph with: vertices formed from the one or more classically-executable-nodes; and edges formed from a plurality of quantum-circuits comprising the first-circuit and the second-circuit with the teachings of Bruestle, Sharma, Yang and Mukerjee with the motivation to implement the network of Bruestle (Bruestle: P 0020) in a well-known configuration for more efficient progression of the operations (de Beaudrap: C 5 L 28-31) and the Supreme Court in KSR International Co. v. Teleflex Inc. identified applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as a rationale to support a conclusion of obviousness which is consistent with the proper “functional approach” to the determination of obviousness as laid down in Graham.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruestle et al. (US 2015/0262074 A1) in view of Sharma et al. (US 11,586,966 B2) and Yang et al. (US 2004/0193719 A1) and Mukerjee et al. (US 2009/0112905 A1) and further in view of Tran et al. (US 2020/0358187 A1).
Claim 5. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, but Bruestle does not disclose tagging the first-circuit with: a first-node-unique-identifier that uniquely identifies a first-node, of the one or more classically-executable-nodes, sending the first-circuit; a first-request-unique-identifier that uniquely identifies a request of the first-node for the first-circuit-evaluation; receiving the first-circuit-evaluation with the first-node-unique-identifier and the first-request-unique-identifier; and sending the first-circuit-evaluation and the first-request-unique-identifier to the first-node for processing, as disclosed in the claims. However, Sharma discloses one or more indicators are provided to the quantum circuit to identify the portion of the quantum circuit (C 11 L 33-52, C 16 L 40-44) being analyzed (debugged) (C 16 L 45-51). In the same field of invention, Tran discloses for a hybrid classical/quantum computer (P 0298) code of a classical specification is converted for a quantum computer, an execution unit selects one or more quantum computers (P 0300) the data is processed using classical computers and then processed by quantum computers (P 0319). Therefore, considering the teachings of Bruestle, Sharma, Yang, Mukerjee and Tran, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine tagging the first-circuit with: a first-node-unique-identifier that uniquely identifies a first-node, of the one or more classically-executable-nodes, sending the first-circuit; a first-request-unique-identifier that uniquely identifies a request of the first-node for the first-circuit-evaluation; receiving the first-circuit-evaluation with the first-node-unique-identifier and the first-request-unique-identifier; and sending the first-circuit-evaluation and the first-request-unique-identifier to the first-node for processing with the teachings of Bruestle, Sharma, Yang and Mukerjee with the motivation to provide an improved method for developing quantum computing programs and providing results for modifications to or integration of different programs or versions of a program (Sharma: C 1 L 21-34).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruestle et al. (US 2015/0262074 A1) in view of Sharma et al. (US 11,586,966 B2) and Yang et al. (US 2004/0193719 A1) and Mukerjee et al. (US 2009/0112905 A1) and further in view of Berkley et al. (US 11,288,073 B2).
Claim 11. Bruestle, Sharma, Yang and Mukerjee disclose the method of claim 1, but Bruestle does not disclose adding one or more new-nodes, to the one or more classically-executable-nodes of the classical-quantum hybrid algorithm, based on the first-circuit-evaluation and/or the second-circuit-evaluation, as disclosed in the claims. However, in the same field of invention, Berkley discloses the graph may be updated by adding or removing vertices (C 2 L 32-37) based on the results of measurements or quantifications (C 10 L 3-12). Therefore, considering the teachings of Bruestle, Sharma, Yang, Mukerjee and Berkley, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine adding one or more new-nodes, to the one or more classically-executable-nodes of the classical-quantum hybrid algorithm, based on the first-circuit-evaluation and/or the second-circuit-evaluation with the teachings of Bruestle, Sharma, Yang and Mukerjee with the motivation in order to provide a known implementation to ensure optimum measurements performed in a classical computer/quantum computer hybrid system (Berkley: C 11 L 12-29).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bruestle et al. (US 2015/0262074 A1) in view of Sharma et al. (US 11,586,966 B2) and Mukerjee et al. (US 2009/0112905 A1) and further in view of Tran et al. (US 2020/0358187 A1).
Claim 16. Bruestle, Sharma and Mukerjee disclose the method of claim 13, but Bruestle does not disclose receiving, from a first-node of the one or more classically-executable-nodes, the first-circuit with: a first-node-unique-identifier that uniquely identifies first-node; a first-request-unique-identifier that uniquely identifies a request of the first-node for the first-circuit-evaluation; and sending the first-circuit-evaluation with the first-node-unique-identifier and the first-request-unique-identifier to the one or more classically-executable-nodes for processing, as disclosed in the claims. However, Sharma discloses one or more indicators are provided to the quantum circuit to identify the portion of the quantum circuit being (C 11 L 33-52, C 16 L 40-44) being analyzed (debugged) (C 16 L 45-51). In the same field of invention, Tran discloses for a hybrid classical/quantum computer (P 0298) code of a classical specification is converted for a quantum computer, an execution unit selects one or more quantum computers (P 0300) the data is processed using classical computers and then processed by quantum computers (P 0319). Therefore, considering the teachings of Bruestle, Sharma, Mukerjee and Tran, one having ordinary skill in the art before the effective filing date of the invention would have been motivated to combine receiving, from a first-node of the one or more classically-executable-nodes, the first-circuit with: a first-node-unique-identifier that uniquely identifies first-node; a first-request-unique-identifier that uniquely identifies a request of the first-node for the first-circuit-evaluation; and sending the first-circuit-evaluation with the first-node-unique-identifier and the first-request-unique-identifier to the one or more classically-executable-nodes for processing with the teachings of Bruestle, Sharma and Mukerjee with the motivation to provide an improved method for developing quantum computing programs and providing results for modifications to or integration of different programs or versions of a program (Sharma: C 1 L 21-34).
Response to Arguments
Applicant’s arguments, see Applicant Arguments/Remarks, filed 16 July 2025, with respect to dependent Claims 10 and 19 have been fully considered and are persuasive. Applicant imported amended limitations of Claim 10 into independent Claim 1 and amended limitations of Claim 19 into independent Claim 13. Furthermore, the amended limitations have been incorporated into independent Claim 20. The amendments have overcome the prior rejection under 35U.S.C. § 112(b).
Applicant’s arguments with respect to claim(s) 1, 13, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The examiner has combined new prior art reference Mukerjee to reject the amended claims. Mukerjee discloses raw baseline features from a broad range of sources are identified in an input signal and are aggregated, abstracted and indexed for later retrieval or manipulation (P 0022) sequences of indexed features are clustered together to form a sequence or pattern for indexing and represented as a vector (P 0026) buffers are accessed to process the sequence of feature indexes associated with a particular data set to generate one or more clusters, then a graph-like data structure is assembled with all of the clusters being tied to a common node that is associated with and indexed to the underlying data (P 0034) feature indexes are compared to identify common nodes with one or more feature indexes associated with the sequence either as leaf nodes or as clusters of leaf nodes with a common root node (P 0065) and node clusters from a common node can be split into a new root node (P 0067). Combining Mukerjee with Bruestle would provide an improved data storage method that avoids redundant storage that provides better efficiency and flexibility (Mukerjee: P 0003, 0004).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to JOHN M HEFFINGTON at telephone number (571)270-1696.
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M HEFFINGTON whose telephone number is (571)270-1696. The examiner can normally be reached on Monday through Friday from 9:30 am to 5:30 pm Eastern.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Cesar B Paula, can be reached at telephone number 671-272-4128. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center to authorized users only. Should you have questions about access to the USPTO patent electronic filing system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/InterviewPractice.
/J.M.H/Examiner, Art Unit 2145 10/18/2025
/CESAR B PAULA/Supervisory Patent Examiner, Art Unit 2145