Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-14, 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maher, III et al. (US 2003/0118029, hereinafter Maher) in view of Kitada (US 2014/0016463), KUIK et al. (US 20100054129), and JANAKIRAMAN et al. (US 20140153577).
Regarding claim 1, Maher discloses
A method, comprising receiving a data packet an on-chip Quality of Service (QoS) circuit (par. 59: The traffic flow scanning engine compares the traffic flows to the associated subscriber policies and assigns data packets from the traffic flows to a QoS queue in the QoS processor 116 based on the results of its policy enforcement), the data packet including metadata relating to providing a predetermined QoS ... forwarding data packet from the on-chip QoS circuit to an on-chip data consumer, the on-chip data consumer including: being an egress port, a switch, or a processing unit, a type of the on-chip data consumer relating to being metadata (par. 39: The fast-path traffic flow scanning engine 140 and QoS processor 116 send packets requiring additional processing to flow management processor 122, which forwards them to microprocessor 124 for processing. The microprocessor 124 then communicates back to traffic flow scanning engine 140 and QoS processor 116 through flow management processor 122; 4] [0038]: QoS processor 116 also includes packet modification engine 130, which is operable to modify, add, or delete bits in any of the fields of a data packet. This allows QoS processor 116 to change addresses for routing or to place the appropriate headers on the data packets for the required protocol. The packet modification engine 130 can also be used to change information within the payload itself if necessary. Data packets are then sent along fast-data path 126 to output PHY interface 120 where it is converted back into an analog signal and placed on the network).
Maher discloses all the subject matter of the claimed invention with the exception of classifying the data packet as a particular traffic class in view of the QoS field indicating the predetermined QoS, wherein the traffic class is used with the at least one other metadata field to determine a handling of the data packet in a QoS queue; responsive to the classifying, forwarding the data packet from the on-chip QoS circuit to an on-chip data consumer, the on-chip data consumer including: an egress port, a switch, or a processing unit, a type of the on-chip data consumer relating to the metadata.
Kitada from the same or similar fields of endeavor discloses classifying the data packet as a particular traffic class in view of the QoS field indicating the predetermined QoS, wherein the traffic class is used (par. 156: A priority class is set on each packet arriving at the scheduler, for example, by an IF card on the input side of the packet processing apparatus or by another apparatus, and each packet is stored in a queue corresponding to the class; 4] [0159]: the packet processing apparatus detects existence of a large and low-priority packet ahead of a high-priority packet based on the packet group information. During a packet read, the packet processing apparatus (1) temporarily stops reading the detected large and low- priority packet, and (2) first reads a high-priority packet arriving later at a high-priority queue. This makes it possible to prevent a delay caused if the high-priority packet is forced to wait until the low- priority packet is outputted) with the at least one other metadata field (par. 64: The QoS circuit 16 includes a packet information extraction unit 101; 4 [0065]: The packet information extraction unit 101 extracts information from each packet arriving at the IF card 1. The extracted information will be referred to hereinafter as "packet information." The packet information includes, for example, flow ID and packet length. The flow ID is identification information about a flow and is stored, for example, in the internal header of the packet) to determine a handling of the data packet in a QoS queue (par. 156: A priority class is set on each packet arriving at the scheduler, for example, by an IF card on the input side of the packet processing apparatus or by another apparatus, and each packet is stored in a queue corresponding to the class), the at least one other metadata field including at least one of: a flow related field (par. 66: The internal header contains information such as IF card number, port number, packet length, flow ID, and queue ID); a flow ID field (par. 66: The internal header contains information such as IF card number, port number, packet length, flow ID, and queue ID); a color field (par. 74: The flow processing unit 106A includes plural pipelines performing a token subtraction process and color determination process on a flow by flow basis); a class field (par. 156: A priority class is set on each packet arriving at the scheduler, for example, by an IF card on the input side of the packet processing apparatus); a destination related field (par. 66: The internal header contains information such as IF card number, port number, packet length, flow ID, and queue ID, where the IF card number is the card number of the IF card at a transfer destination of the packet within the packet processing apparatus 100); a egress port field (par. 38: The flow means a packet group whose source IP address, destination IP address, source port number, destination port number; q] [0066]: The internal header contains information such as IF card number, port number, packet length, flow ID, and queue ID); or a destination sub-interface field (Fig. 1, 5 line port of egress IF card; par. 66: The internal header contains information such as IF card number, port number, packet length, flow ID, and queue ID, where the IF card number is the card number of the IF card at a transfer destination of the packet within the packet processing apparatus 100); and responsive to the classifying, forwarding the data packet from the on-chip QoS circuit to an on-chip data consumer, the on-chip data consumer including: being an egress port, a switch, or a processing unit, a type of the on-chip data consumer relating to being metadata (par. 62: Each of the PHY/MAC circuit 11, memory 12, data processor 13, control processor 14, and QoS circuit 16 contained in the IF card 1 may be a separate device or chip. Also, the IF card 1 may be one or more LSls (Large Scale Integrations) containing the above circuits and devices; par. 66: The internal header of the packet, which is effective within the packet processing apparatus, is attached by an input-side IF card before input to the QoS circuit, and removed by the input-side IF card or an output-side IF card. The internal header contains information such as IF card number, port number, packet length, flow ID, and queue ID, where the IF card number is the card number of the IF card at a transfer destination of the packet within the packet processing apparatus 100).
Therefore, it would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teaching of Maher by classifying, by ingress IF card including QoS circuit implemented as a chip in LSI(s), the priority class of each packet including higher priority and low priority to be stored in QoS queue with the other parameter including flow ID, color, priority class, IF card number at a transfer destination of the packet within the packet processing apparatus, port number, source port number, destination port number and forwarding the each packet to egress IF card including ports, etc. of Kitada.
The motivation would have been to improve processing speed for packet processing including bandwidth control (Kitada par. 182).
Maher discloses all the subject matter of the claimed invention with the exception of the at least one other metadata field including: a session identifier (ID) field;
KUIK et al. (US 20100054129) from the same or similar fields of endeavor discloses classifying the data packet as a particular class in view of the QoS field indicating the predetermined QoS, wherein the class is used with the at least one other metadata field, the at least one other metadata field including: a session identifier (ID) field (par. 16, 19, QoS refers to selectively providing differentiated services to some packets or flows than to other packets or flows. A flow may be identified by a combination of source and destination addresses, source and destination socket numbers, a session identifier, a class of service (COS) field, and other items…QoS may include controlling and predictably servicing a variety of networked applications and traffic types…classification may be based on TCP/IP flow, DSCP, IP precedence, COS, discard class, QOS group, IP packet length, RTP port list, a classification rule set reference, an access control list specification, and so on).
Therefore, it would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teaching of Maher in view of Kitada by classifying the other parameter including session identifier, etc. of KUIK.
The motivation would have been to provide the quality of service to each session.
Maher discloses all the subject matter of the claimed invention with the exception of a session identifier (ID) field representing a layer-2 session or a layer-3 session associated with a packet flow;
JANAKIRAMAN et al. (US 20140153577) teaches the at least one other metadata field including: a session identifier (ID) field representing a layer-2 session or a layer-3 session associated with a packet flow (par. 37, A flow could consist of all packets in a specific session connection or media stream. Each layer 2 or layer 3 network session can be uniquely identified by a session key, which may be a layer 3 network session key or a layer 2 network session key. A layer 3 network session key generally includes information, such as a source Internet Protocol (IP) address, a destination IP address, a protocol, a layer 4 source port, a layer 4 destination port, etc. Moreover, a layer 2 network session key generally includes a source Media Access Control (MAC) address, a destination MAC address, Ethernet type, etc.);
Therefore, it would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teaching of JANAKIRAMAN in view of Kitada, KUIK, and Maher by classifying the other parameter including source IP address and destination IP address as layer 3 session identifier and source MAC address and destination MAC address as layer 2 session identifier.
The motivation would have been to improve look up for layer 2 switching or layer 3 routing.
Regarding claim 2, Maher discloses
further comprising modifying the metadata of the data packet by providing further metadata to the data packet or altering the metadata of the data packet (par. 38: This allows QoS processor 116 to change addresses for routing or to place the appropriate headers on the data packets for the required protocol).
Regarding claim 3, Maher discloses e wherein the metadata is added to the data packet by an on-chip wire-speed engine (par. 28: When a data packet is received that has new session information the header processor creates a unique session id to identify that particular traffic flow ... While the session id is discussed herein as being created by the header processor 104 the session id can be created anywhere in traffic flow scanning engine 140 including in payload analyzer 110) before the on-chip QoS circuit receives the data packet (par. 59: The traffic flow scanning engine compares the traffic flows to the associated subscriber policies and assigns data packets from the traffic flows to a QoS queue in the QoS processor 116 based on the results of its policy enforcement).
Regarding claim 4, Maher discloses
wherein the on-chip QoS circuit includes one or more ingress modules configured to process the data packet, wherein processing the data packet includes at least one of: parsing, classification, congestion control, or storage of ingress data (par. 34: QoS processor 116 takes the conclusion, or treatment, of either or both of header processor 104 and payload analyzer 110 and assigns the data packet to one of its internal quality of service queues 132 based on the conclusion. The quality of service queues 132 can be assigned priority relative to one another or can be assigned a maximum or minimum percentage of the traffic flow through the device).
Regarding claim 5, Maher discloses
wherein the on-chip QoS circuit is operatively coupled to one or more processing units, the processing units being configured to further processing on the data packet (par. 39: The fast- path traffic flow scanning engine 140 and QoS processor 116 send packets requiring additional processing to flow management processor 122, which forwards them to microprocessor 124 for processing).
Regarding claim 6, Maher discloses
wherein the further processing on the data packet (par. 39: The fast-path traffic flow scanning engine 140 and QoS processor 116 send packets requiring additional processing to flow management processor 122, which forwards them to microprocessor 124 for processing) is separate from forward the data packet to the egress port (par. 38: The packet modification engine 130 can also be used to change information within the payload itself if necessary. Data packets are then sent along fast-data path 126 to output PHY interface 120 where it is converted back into an analog signal and placed on the network).
Regarding claim 7, Maher discloses
wherein the egress port and one or more additional egress ports are used as a destination for the data packet once the data packet has been fully processed (par. 36: The QoS queues 132 in QoS processor 116 (there are 65k queues in the present embodiment of the QoS processor although any number of queues could be used) have multiple associated class of service (CoS) queues which feed into schedulers 134 (1024 in the present embodiment), which feed into logic ports 136 (256 in the present embodiment), which send the data to flow control port managers 138 (32 is the present embodiment) which can correspond to physical egress ports for the network device; par. 53: the network device is operable to scan the header information of each packet and determine, among other things, a source address, source port, destination address and destination port).
Regarding claim 8, Maher discloses
wherein the further processing on the data packet includes one or more dedicated functions for data packet processing (par. 33: QoS processor contains engines for traffic management 126, traffic shaping 128 and packet modification 130).
Regarding claim 9, Maher discloses
wherein the one or more processing units each include at least one processor core (par. 61]: While the header processor, the QoS processors, and the flow management processor described with reference to FIGS. 2 and 4 can be any suitable processor capable of executing the described functions, in the preferred embodiment the header processor is the Fast Pattern Processor (FPP), the QoS processor is the Routing Switch Processor (RSP), and the flow management processor is the ASI processor, all manufactured by the Agere Division of Lucent Technologies, Austin Tex. Similarly the switch fabric may be any suitable switch fabric as is well known in the industry, including those manufactured by Power X Networks, Inc., 2833 Junction Ave., Suite 110, San Jose, Calif. The microprocessor described with reference to FIGS. 2 and 4 could be any suitable microprocessor including the PowerPC line of microprocessors from Motorola, Inc., or the X86 or Pentium line of microprocessors available from Intel Corporation. Although particular references have been made to specific protocols, implementations and materials, those skilled in the art should understand that the network apparatus, both the "bump-in-the-line" and the routing apparatus can function independent of protocol, and in a variety of different implementations without departing from the scope of the invention).
Regarding claim 10, Maher discloses
wherein responsive to the data packet being forwarded to a first processing unit by the on-chip QoS circuit, the first processing unit is configured to perform operations including: process the data packet in a first processing step to form processed data, and redirect the processed data from the processing circuit back to the on-chip QoS circuit (par. 39: The fast- path traffic flow scanning engine 140 and QoS processor 116 send packets requiring additional processing to flow management processor 122, which forwards them to microprocessor 124 for processing. The microprocessor 124 then communicates back to traffic flow scanning engine 140 and QoS processor 116 through flow management processor 122).
Regarding claim 11, Maher discloses
further comprising forwarding the processed data to the data consumer (par. 38: Data packets are then sent along fast-data path 126 to output PHY interface 120 where it is converted back into an analog signal and placed on the network).
Regarding claim 12, Maher discloses
wherein the predetermined QoS includes a basic QoS or an advanced QoS (par. 34: The quality of service queues 132 can be assigned priority relative to one another or can be assigned a maximum or minimum percentage of the traffic flow through the device. This allows QoS processor to assign the necessary bandwidth to traffic flows such as VoIP, video and other flows with high quality and reliability requirements while assigning remaining bandwidth to traffic flows with low quality requirements such as email and general web surfing to low priority queues).
Regarding claim 13, Maher discloses
wherein the predetermined QoS includes at least one of a traffic control, peak rate control, or burstiness handling (par. 36: The traffic management engine 126 and the traffic shaping engine 128 determine the operation of the schedulers and logic ports in order to maintain traffic flow in accordance with the programmed parameters).
Regarding claim 14, Maher discloses
wherein the data packet is received at an ingress port (par. 26: Input physical interface 102 takes the data from the physical ports, frames the data, and then formats the data for placement on fast-path data bus 126 which is preferably an industry standard data bus such as a POS-PHY Level 3, or an ATM UTOPIA Level 3 type data bus).
Regarding claim 16, Maher discloses
wherein the QoS is operable to output the data packet to one or more networks, wherein the networks comprise a wireless network, or a wired network (par. 26: Input physical interface 102 takes the data from the physical ports, frames the data, and then formats the data for placement on fast-path data bus 126 which is preferably an industry standard data bus such as a POS-PHY Level 3, or an ATM UTOPIA Level 3 type data bus; par. 38: Data packets are then sent along fast-data path 126 to output PHY interface 120 where it is converted back into an analog signal and placed on the network).
Regarding claim 17, Maher discloses
wherein the metadata relates a predetermined QoS (par. 31: After data packets have been processed by header processor 104 the data packets, their associated session id and any conclusion formed by the header processor, such as routing or QoS information, are sent on fast-data path 126 to the other half of traffic flow scanning engine 140, payload analyzer 110; par. 53: the network device is operable to scan the header information of each packet and determine, among other things, a source address, source port, destination address and destination port. This information can be used to determine if the data packet belongs to a registered customer with a set of programmed policies residing on the network device. Also discussed above, the network device is operable to scan the contents of each data packet and determine the type of content, such as email, web surfing, VoIP, video, file transfers, etc., so that the contents can be used in the handling of the data packet) for an external data consumer; par. 21: VoIP networks 46 and 47 allow IP phones 48 and PCs 50 equipped with the proper software to make telephone calls to other phones, or PCs connected to the internet or even to regular phones connected to the PSTN. VoIP networks, such as VoIP network 46, include media gateways 52 and other equipment, not shown, to collect and concentrate the VoIP calls which are sent through service provider network 34 and private and public internet 12 and 10 as required).
Regarding claim 18, Maher discloses
wherein the external data consumer includes at least one of: a screen, a telephone, an audio equipment, a multimedia application on a computer, wireless or wired internet provider, a household appliance, a surveillance system, an automated machinery control, or a measurement system (par. 21: VoIP networks 46 and 47 allow IP phones 48 and PCs 50 equipped with the proper software to make telephone calls to other phones, or PCs connected to the internet or even to regular phones connected to the PSTN. VoIP networks, such as VoIP network 46, include media gateways 52 and other equipment, not shown, to collect and concentrate the VoIP calls which are sent through service provider network 34 and private and public internet 12 and 10 as required).
7. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Maher, Ill et al. (US 2003/0118029, hereinafter Maher) in view of Kitada (US 2014/0016463), KUIK et al. (US 20100054129), and JANAKIRAMAN et al. (US 20140153577) as applied to claim 1, and further in view of Maxwell et al. (US 8,693,470, hereinafter Maxwell).
Regarding claim 15, Maher in view of Kitada discloses all the subject matter of the claimed invention with the exception of wherein the egress port includes a virtual port.
Maxwell from the same or similar fields of endeavor discloses wherein the egress port includes a virtual port (col. 4, line 67-col. 5, line 11: . The prepended header 225 may provide to the downstream QoS module 140 the identity of the terminal 112a, 112b, 112c, or 112d from which the packet 220 was received and a queue into which the packet should be enqueued for egress. The queue may be identified directly, or indirectly by, e.g., identifying an outgoing logical interface via which the packet is to egress. The combination 210 of the packet 220 and header 225 is passed to the QoS module 140 for egress, either to one of the terminals 113a-d, internally to route processor 150, or even back to one of the packet forwarding modules 130 for an additional pass through the router 110).
Therefore, it would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teaching of Maher in view of Kitada and Kuik by identifying an outgoing logical interface via which the packet is to egress of Maxwell.
The motivation would have been to optimize flexibility and scalability in that it can handle variable and indeterminate egress/ingress speeds (Maxwell col. 6, lines 13-14).
Claim 19, 20 is rejected under 35 U.S.C. 103 as being unpatentable over Maher, Ill et al. (US 2003/0118029, hereinafter Maher) in view of Kitada (US 2014/0016463), KUIK et al. (US 20100054129), and JANAKIRAMAN et al. (US 20140153577) as applied to claim 1, and further in view of Hsin et al. (US 20110019556).
Regarding claim 19, Maher does not disclose the method of claim 1, wherein the data packet is received at a wireless interface.
Hsin from the same or similar fields of endeavor discloses wherein the data packet is received at a wireless interface (par. 14: Some embodiments may be used in conjunction with various devices and systems, for example, a transmitter, receiver; par. 45: To illustrate in further detail how laptop 260 or other wireless communication device may process QoS packets of wireless traffic without explicit control negotiations, we turn now to FIG. 3. FIG. 3 illustrates how a prioritization engine 310 may implement a Non-Negotiated QoS (NNQ) scheme and process QoS packets via a wireless network adapter driver 300; 4] [0046]: Prioritization engine 310 may receive the unmarked network packets (element 305) from applications executing on a wireless station. By way of example, with reference to FIG. 2, laptop 260 may be executing numerous applications and using wireless communications to communicate with wireless display 280 and access point 230; par. 62: Continuing with the previous example, the prioritization engine may mark the packet as a "video" or "VI" packet via the packet header and place the packet in a high priority QoS queue. Upon placing the packet in the queue, the embodiment may return to waiting for an application to forward one or packets for wireless transmission).
Therefore, it would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teaching of Maher by receiving wireless traffic via the wireless receiver, setting bits Traffic Class field based on the match with “voice” access category by examining a packet and determining that one or more field values match predetermined criteria, and placing the packet in a high priority “VO” QoS queue, then forwarding the packet to transmitter for wireless transmission of Hsin.
The motivation would have been to may process the QoS-marked packets for the video stream and voice stream, as well as process packets of the best effort stream, using different transmission queues, dynamically allocated queues, and various first-in first-out (FIFO) buffers according to the marked QoS access categories (Hsin par. [0050]).
Regarding claim 20, Maher does not disclose the method of claim 1, wherein the egress port includes a wireless interface.
Hsin from the same or similar fields of endeavor discloses wherein the egress port includes a wireless interface (par. 14: Some embodiments may be used in conjunction with various devices and systems, for example, a transmitter, receiver; par. 45: To illustrate in further detail how laptop 260 or other wireless communication device may process QoS packets of wireless traffic without explicit control negotiations, we turn now to FIG. 3. FIG. 3 illustrates how a prioritization engine 310 may implement a Non-Negotiated QoS (NNQ) scheme and process QoS packets via a wireless network adapter driver 300; par. 46: Prioritization engine 310 may receive the unmarked network packets (element 305) from applications executing on a wireless station. By way of example, with reference to FIG. 2, laptop 260 may be executing numerous applications and using wireless communications to communicate with wireless display 280 and access point 230; par. 62: Continuing with the previous example, the prioritization engine may mark the packet as a "video" or "VI" packet via the packet header and place the packet in a high priority QoS queue. Upon placing the packet in the queue, the embodiment may return to waiting for an application to forward one or packets for wireless transmission).
Therefore, it would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teaching of Maher by receiving wireless traffic via the wireless receiver, setting bits Traffic Class field based on the match with “voice” access category by examining a packet and determining that one or more field values match predetermined criteria, and placing the packet in a high priority “VO” QoS queue, then forwarding the packet to transmitter for wireless transmission of Hsin.
The motivation would have been to may process the QoS-marked packets for the video stream and voice stream, as well as process packets of the best effort stream, using different transmission queues, dynamically allocated queues, and various first-in first-out (FIFO) buffers according to the marked QoS access categories (Hsin q [0050]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
GHETIE et al. (US 20050114541) teaches quality of service is more appropriately designated on a per user/application session level (par. 9).
PONG et al. (US 20110268119) teaches if the header fields indicate policy based processing is needed, packet processor 110a may send data in header fields, including but not limited to, receive port, transmit port, Media Access Control Source Address (MAC-SA), Internet Protocol (IP) source address, IP destination address session identification etc. to a custom hardware acceleration block such as policy engine 126j (see FIG. 3) for further processing (par. 26).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THINH D TRAN whose telephone number is (571)270-3934. The examiner can normally be reached mon-fri 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FARUK HAMZA can be reached at 5712727969. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THINH D TRAN/for /Thinh Tran/, Patent Examiner of Art Unit 2466 02/27/2026