DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is Final and is in response to the claims filed 02/17/2026. Claims 1, 4-13, 15-21, and 23-25 are currently pending, of which claims 1, 4-13, 15-21, and 23-25 are currently rejected.
Response to Arguments
Applicant’s arguments filed on 02/17/2026 have been fully considered.
35 U.S.C. 102: Applicant’s arguments regarding the 35 U.S.C. 102 rejection have been fully considered. Examiner finds arguments persuasive. However, See new grounds of rejection below necessitated by amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Apparatus claims 13, 15-18 and 20 will be addressed before corresponding method claims 1 and 4-7, and corresponding media claim 25.
Claims 1, 4-9, 13, 15-19, 20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over R. K. Montoye in NPL: “Design of the IBM RISC System/6000 floating-point execution unit” (cited in 892 Notice of References Cited on 04/03/2025), in view of Oberman et al. (U.S. Patent Application Publication US 20090150654 A1), hereinafter “Oberman”.
Regarding Claim 13, Montoye teaches:
An apparatus for performing a floating-point multiply-add operation of a form A*B+C on at least one multiply-add unit with a method according to claim 1 (Fig. 3, e.g., shows multiply-add fused unit pipeline, which performs A*B+C), which comprises:
three input floating-point operands A, B, C, (Fig. 3) …
Montoye does not teach:
… wherein at least one of the floating- point operands A, B, C is provided by a substitution logic, being configured to be separately configurable to substitute the operand A, B, C by the at least one value of the
predefined operand value set to be propagated to at least one output port of the substitution logic, wherein the substitution logic is configured as a multiplexor circuitry, wherein at least one of the three floating-point operands A, B, C is provided by the multiplexor circuitry respectively, and the multiplexor circuitry comprising;
a first input port for the respective floating-point operand A, B, C;
at least a second input port for at least one value of a predefined operand value set; and
at least one output port assigned to the corresponding first and second input ports, wherein the multiplexor circuitry is configured to be separately configurable to select one of the input ports to be propagated to the at least one output port;
wherein three multiplexor circuitries correspond to the three input floating-point operands A, B, C, and correspond to multiple different selectable operations performed by an FMA (Floating-Point-Multiply-Add) unit; and
wherein the three multiplexor circuitries respectively output selected operands of the floating-point operands, directly into the three input floating-point operands A, B, C, of the FMA unit, respectively.
However, Oberman teaches:
wherein at least one of the floating-point operands A, B, C is provided by a substitution logic (Fig. 5, e.g., shows double-precision fused multiply-add (DFMA) unit 320 which includes Operand Preparation 514, Fig. 6, e.g., Shows Operand Preparation 514 using Multiplexers 632, 634, 636, one for each input A, B, and C. Each multiplexer has inputs A or B or C other values for which they can be substituted (0,1, FP32 Extract Output...)), being configured to be separately configurable to substitute the operand A, B, C by the at least one value of the predefined operand value set to be propagated to at least one output port of the substitution logic (Fig. 5, Fig. 6 e.g., Values can be substituted separately by each multiplexer, and selected value is outputted, ¶0094-0096), wherein the substitution logic is configured as a multiplexor circuitry (Fig. 6, ¶0094-0096), wherein at least one of the three floating-point operands A, B, C is provided by the multiplexor circuitry respectively (Fig. 6, e.g., Shows Operand Preparation 514 using Multiplexers 632, 634, 636, one for each input A, B, and C. Each multiplexer has inputs A or B or C other values for which they can be substituted (0,1, FP32 Extract Output...). Values can be substituted separately by each multiplexer. Selected value is outputted; ¶0094-0096), and the multiplexor circuitry comprising;
a first input port for the respective floating-point operand A, B, C (Fig. 6; ¶0094-0096);
at least a second input port for at least one value of a predefined operand value set (Fig. 6, e.g., has at least one constant value (predefined operand value set) 0 and/or 1; ¶0094-0096); and
at least one output port assigned to the corresponding first and second input ports (Fig. 6, e.g., shows first and second inputs (either one of the 3/4 inputs) and output port of the multiplexer to transfer selected data to special number detection circuits; ¶0097), wherein the multiplexor circuitry is configured to be separately configurable to select one of the input ports to be propagated to the at least one output port (Fig. 6; ¶0094-0096, e.g., each paragraph talks about each multiplexer process for each input A, B, C);
wherein three multiplexor circuitries correspond to the three input floating-point operands A, B, C (¶0094, e.g., Operand selection muxes 632, 634, 636 respond to signals from control logic 630 to select operands A, B and C; Fig. 6), and correspond to multiple different selectable operations performed by an FMA (Floating-Point-Multiply-Add) unit (Fig. 6; ¶0094, e.g., multiplexer could output operands A, B, C, or constant values 1 or 0; Fig. 8, e.g., Mantissa path (FMA) could compute A*B+C, A+C, B+C, or other operations depending on the output of muxes 632, 634, 636 (multiplexor circuitries)); …
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the three operand selection muxes 632, 634, 636 and control logic 630 to control muxes as taught by Oberman with the multiply-add fused unit as taught by Montoye. One would have been motivated to combine these references because both references disclose floating-point multiply-add operations, and Oberman enhances the model of Montoye by allowing for the configuration of the MAF unit to operate in different modes according to the selection of the muxes. See Oberman: ¶0094-0096. Combination would cause for the muxes to be placed before the MAF unit, allowing for selection of operands before they are inputted. Hence, Combination of Montoye in view of Oberman teach the limitation “wherein the three multiplexor circuitries respectively output selected operands of the floating-point operands, directly into the three input floating-point operands A, B, C, of the FMA unit, respectively.”
Regarding Claim 15, Montoye in view of Oberman teach:
The apparatus according to claim 13, wherein the floating-point multiply-add operation is triggered by an instruction with a selection code parameter to specify a configuration of the at least one substitution logic (¶0094, Control logic 630 provides control signal (instruction) that holds a parameter (selection code parameter) to select the value for what each operand will be substituted for; Fig. 6).
Regarding Claim 16, Montoye in view of Oberman teach:
The apparatus according to claim 13, wherein the predefined operand value set at least is configured as a set comprising values, selected from a group consisting of: -0, +0, +1, -1 (Oberman: Fig. 6, e.g., predefined operands 0 and/or 1 in multiplexers; ¶0068, e.g., Zero can have either sign; thus both positive and negative zero are allowed; Montoye: Page 60, Second column, Second paragraph, e.g., MAF unit performs floating point, hence a “1” could be positive or negative).
The motivation to combine provided with respect to claim 13 applies equally to claim 16.
Regarding Claim 17, Montoye in view of Oberman teach:
The apparatus according to claim 15, wherein the selection code parameter being used for selecting one of the input ports to be propagated to the at least one output port is at least one of a set corresponding to selectable operations comprising -0, C, A, A+C, B, B+C, A*B, A*B+C, C+1, 1, -A+C, -B+C (Oberman: Fig. 6; ¶0094, e.g., multiplexer would output operands A, B, and C; Montoye: Fig. 3 e.g., Could compute A*B+C).
The motivation to combine provided with respect to claim 13 applies equally to claim 17.
Regarding Claim 18, Montoye in view of Oberman teach:
The apparatus according to claim 13, comprising at least a multiply-add unit with three inputs (Montoye: Fig. 3, e.g., shows MAF unit receiving operands A, B, and C),
wherein at least one input is received from an output of the at least one substitution logic (Montoye: Fig. 3, e.g., shows MAF unit receiving operands A, B, and C; Combination of Montoye in view of Oberman would cause for MAF unit to receive outputs from operand selection muxes (substitution logic)).
The motivation to combine provided with respect to claim 13 applies equally to claim 18.
Regarding Claim 20, Montoye in view of Oberman teach:
The apparatus according to claim 13, being configured for performing a floating-point multiply-multiply-add operation of a form A0*B0+A1*B1+C ((Montoye: Fig. 3, e.g., MAF unit computes A*B; Page 60, Section “Floating-point operations”, e.g., each operand is made out of 52 bit mantissas, hence computing Am0*Bm0, Am1*Bm1... Am51*Bm51. Product is inputted in Adder, where A*B is added to C operand, hence being in the format A0*B0+A1*B1+C), with input floating-point operands comprising A0, A1, B0, B1, C (Montoye: Fig. 3, e.g., shows operands A, B, and C; Page 60, Section “Floating-point operations”, e.g., Each operands contains 52-bit mantissas).
With regards to Claim 1, 4-7, they are directed to a method practiced by the apparatus of claims 13, 15-17 and 20, respectively. They are rejected for the same reasons.
With regards to Claim 25, this is a media version of the claimed method above (claim 1 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Regarding Claim 8, Montoye teaches:
The method according to claim 1 … [and] a register file with at least two read ports and one write port (Montoye: Second Column, Second paragraph, e.g., register file has a five-port bandwidth) …
Montoye does not specifically teach:
The method according to claim 1, further comprising: providing floating-point operands by a register file as input operands and receiving an output from the substitution logic … , in particular providing the input operands being triggered by the instruction with a selection code parameter.
However, Oberman teaches:
The method according to claim 1, further comprising: providing floating-point operands by a register file as input operands (Fig. 3, e.g., Register File 324 outputs operands as input for issue unit 304, then to DFMA Unit 320; ¶0010, e.g., Operands are double-precision operands (Floating point operands)) and receiving an output from the substitution logic by a register file (Fig. 3, e.g., Register File 324 receives output from double-precision fused multiply-add (DFMA) unit 320; Fig. 5, e.g., DFMA unit 320 contains Operand Preparation unit 514; Fig. 6, e.g., Operand Preparation unit 514 contains Multiplexers (substitution logic)) with [a] read port and one write port (¶0059, e.g., Register file has to have at least one write port to receive data), in particular providing the input operands being triggered by the instruction with a selection code parameter (¶0058, e.g., Issue unit issues the instruction by using opcode (selection code parameter) to determine what unit the operands should be provided as input; Fig. 3).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the register file to provide operands as taught by Oberman with the multiply-add fused unit as taught by Montoye. One would have been motivated to combine these references because both references disclose floating-point multiply-add operations, and Oberman enhances the model of Montoye because a register file allows for the providing of input operands to the MAF unit. See Oberman: ¶0058.
Regarding Claim 19, Montoye in view of Oberman teach:
The apparatus according to claim 13, comprising a register file with at least two read ports and one write port (Montoye: Second Column, Second paragraph, e.g., register file has a five-port bandwidth; Oberman: ¶0059, e.g., Register file has to have at least one write port to receive data), wherein the register file is configured for providing input operands (Oberman: ¶0058, e.g., Operands are provided by the register file; Fig. 3, e.g., register file outputs operand to issue unit 304, then to DFMA Unit 320) and is configured for receiving an output from the multiply-add unit (Oberman: Fig. 3, e.g., Register File 324 receives output from double-precision fused multiply-add (DFMA) unit 320), in particular providing the input operands being triggered by the instruction with a selection code parameter (Oberman: ¶0058, e.g., Issue unit issues the instruction by using opcode (selection code parameter) to determine what unit the operands should be provided as input; Fig. 3).
The motivation to combine provided with respect to claim 8 applies equally to claim 19.
Regarding Claim 9, Montoye teaches:
The method according to claim 1, further comprising: … , wherein [the] multiply-add unit comprises at least one local register file for an intermediate storage of data values (Montoye: Fig. 3, e.g., shows register file (local register file) inside MAF unit) …
Montoye does not teach:
The method according to claim 1, further comprising: when a processor comprises an interconnected mesh of apparatuses with at least one multiply-add unit each, … , triggering the floating-point multiply-add operation by an instruction with a selection code parameter to specify a configuration of the substitution logic.
However Oberman teaches:
The method according to claim 1, further comprising: when a processor comprises an interconnected mesh of apparatuses with at least one multiply-add unit each (¶0057, e.g., Other functional units include single precision multiplication and addition; Fig. 3, e.g., DFMA Unit 320 and Functional units 322(1) and 322(N) are connected together (mesh of apparatuses)), … triggering the floating-point multiply-add operation by an instruction with a selection code parameter to specify a configuration of the substitution logic (¶0094, e.g., Control logic 630 provides control signal (instruction) that holds a parameter (selection code parameter) to select the value for what each operand will be substituted for).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the parallel DFMA units as taught by Oberman with the multiply-add fused unit as taught by Montoye. One would have been motivated to combine these references because both references disclose floating-point multiply-add operations, and Oberman enhances the model of Montoye by allowing for parallelization of multiple multiply-add computations.
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Montoye in view of Oberman, further in view of Ganapathy et al. (U.S. Patent Application Publication No.: US 20030018881 A1), hereinafter “Ganapathy”.
Regarding Claim 10, Montoye teaches the method of claim 1. Montoye does not teach:
when a processor comprises a single-instruction-multiple-data device with
multiple apparatuses with at least one multiply-add unit each, wherein providing predicate values per apparatus by a predicate register is specified by an instruction, selecting an execution of a floating-point multiply-add operation for each apparatus.
However, Oberman teaches:
The method according to claim 1, further comprising: when a processor comprises a single-instruction-multiple-data device (¶0061, e.g., Fetch and dispatch unit 302 and issue unit 304 may implement SIMD) with multiple apparatuses with at least one multiply-add unit each (¶0057, e.g., Other functional units include single precision multiplication and addition (multiply-add unit); Fig. 3, e.g., DFMA Unit 320 and Functional units 322(1) and 322(N) are connected together (multiple apparatuses)), … selecting an execution of a floating-point multiply-add operation for each apparatus (¶0058, e.g., Execution is selected depending on the unit selected to process the operands).
The motivation to combine provided with respect to claim 9 applies equally to claim 10.
Montoye in view of Oberman do not teach:
wherein providing predicate values per apparatus by a predicate register is specified by an instruction,
However, Ganapathy teaches:
wherein providing predicate values per apparatus by a predicate register is specified by an instruction (¶0048, e.g., Predicate registers are within RISC control unit 302. Instruction execution changes based on predicate register contents (predicate values); (¶0078, e.g., Predecoding 702 contains RISC control unit 302 that provides preliminary signals (based on predicate values) to final decoders 704A-704N to be decoded for them to select what component (apparatus) to be used for the given instruction (select execution); Fig. 7),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the predecoding block containing predicate registers with predicate values as taught by Ganapathy with the Fetch and dispatch unit to decode instructions as taught by Montoye in view of Oberman. One would have been motivated to combine these references because both references disclose processing of instructions, and Ganapathy enhances the model of Montoye in view Oberman by providing a source of instructions to be able to select what unit/apparatus to use for execution.
With regards to Claim 21, this is similar to the claimed apparatus above (claims 10, 13 and 15), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Apparatus claims 23 and 24 will be addressed before corresponding method claims 11 and 12.
Claims 11, 12, 23, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Montoye in view of Oberman, in view of Ganapathy, further in view of Afzal (U.S. Patent No.: US 11520561 B1), hereinafter “Afzal”.
Regarding Claim 23, Montoye in view of Oberman in view of Ganapathy also teaches:
The processor according to claim 21, wherein the predicate register comprises … the predicate values (Ganapathy:¶0048; ¶0078; Fig. 7), … to change a flavor of individual lanes based on the respective predicates for each lane (Oberman: ¶0058, e.g., Instructions come from an instruction store that is not shown [predicate register from Ganapathy], then decoded by fetch and dispatch unit. Issue unit sends operands (flavor) to each unit (Lane); Ganapathy: ¶0048, e.g., Instruction execution changes based on predicate register contents (predicate values)).
Montoye in view of Oberman in view of Ganapathy does not teach:
… comprises multi-bit predicate fields …
wherein the predicate-fields are enabled by the instructions for executing the predicate values on lanes of apparatuses
However, Afzal teaches:
… comprises multi-bit predicate fields … (Column 4 Lines 47-52, e.g., Predicate registers can have a plurality of 1-bit entries (multi-bit predicate fields))
wherein the predicate-fields are enabled by the instructions for executing the predicate values on lanes of apparatuses (Column 4 Lines 27 – 35, e.g., A component (apparatus) is selected based on the instruction; Column 4 Lines 54 – 58, e.g., Instructions list a predicate bit (predicate value) to execute the instruction)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the predicate registers containing multi-bit predicate fields as taught by Afzal with the predicate register as taught by Montoye in view of Oberman in view of Ganapathy. One would have been motivated to combine these references because both references disclose predicate registers processing instructions for execution, and Afzal enhances the model of Montoye in view of Oberman in view of Ganapathy by allowing for predicate registers to have multiple bit entries for accurate processing of instructions.
Regarding Claim 24, Montoye in view of Oberman in view of Ganapathy
The processor according to claim 21, wherein at least one multiply-add unit is configured to substitute at least one operand of an internal operation by at least one value of a predefined operand value set (Montoye: Fig. 3, e.g., shows MAF unit (internal operation); Oberman: Fig. 6, e.g., shows operand selection muxes) the operation being triggered by a predicate value specified and decoded into a selection code parameter by a predicate logic based on predicate values… (Oberman: ¶0058, e.g., Fetch and Dispatch unit decodes instructions [from the predicate register taught by Ganapathy] into opcodes (selection code parameter); Ganapathy: ¶0048, e.g., Predicate register triggers operation (instruction execution) based on its contents (predicate value)), on results of previous instructions (Oberman: ¶0058, e.g., Issue unit 304 provides previous instructions.) and on an information about dynamic or static use (Oberman: Fig. 6, e.g., Control Unit 630 provides signal that determines if a constant number (static) or the operand (dynamic) will be used; ¶0094).
Montoye in view of Oberman in view of Ganapathy does not teach:
provided by a load-store unit,
However, Afzal teaches:
provided by a load-store unit (Column 5 Lines 28 – 38, e.g., Control sequencer 112 provides LOAD and STORE instructions to the DME to be executed (Load and Store Unit). LOAD and STORE instructions can set a binary semaphore (predicate value) in the predicate register),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the Control sequencer and the DME for providing predicate values as taught by Afzal with the predicate registers as taught by Montoye in view of Oberman in view of Ganapathy. One would have been motivated to combine these references because both references disclose predicate registers processing instructions for execution, and Afzal enhances the model of Montoye in view of Oberman in view of Ganapathy by allowing for predicate registers to have multiple bit entries for accurate processing of instructions.
With regards to Claim 11, this is a method version of the claimed processor above (claim 23 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
With regards to Claim 12, this is a method version of the claimed processor above (claim 24 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Prior Art Made of Record
US 12591412 B1 – teaches an ALU 150 receiving inputs from Muxes A and B for each operand. See Fig. 1 and corresponding description.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
Prosecution Insights