DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is Final and is in response to the claims filed 02/17/2026. Claims 1, 4-13, 15-21, and 23-28 are currently pending, of which claims 1, 4-13, 15-21, and 23-28 are currently rejected.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/15/2026 has been entered.
Response to Arguments
Applicant’s arguments filed on 05/15/2026 have been fully considered.
35 U.S.C. 103: Applicant’s arguments regarding the 35 U.S.C. 103 rejection have been fully considered, but they are not persuasive.
Applicant argues in page 20 of 24 that Oberman does not teach amended claim 1, including a select code encoded in an instruction to control three multiplexors. Applicant specifically argues “However, Oberman's multiplexors are controlled by internal control logic to select operand values for purposes such as operand conditioning and special-case handling, and the FMA unit continues to perform a fixed A*B+C operation… Oberman does not teach a select code whose value corresponds to different selectable operations of the FMA unit, nor any mapping of multiplexor selections to a plurality of selectable operations.”
Examiner respectfully disagrees. Oberman teaches using an opcode to select different possible operations performed by the DFMA unit. Oberman includes a fetch and dispatch unit that receives instructions and decodes them into opcodes to be inputted into a control block. Control block outputs signals OPCTL that go into operand preparation block, which go into a control logic. Control logic controls the selection of operands of the three muxes. See 35 U.S.C. 103 below.
Applicant further argues in Page 21 of 24 that Oberman does not teach multiplexers outputting operands directly to an FMA unit as shown in fig. 3 of the drawings of the instant application. Applicant explains “Oberman does not disclose configuring multiplexors in a manner that defines selectable operations of the FMA unit. For example, as shown in the drawings of the present application at figure 3, and discussed at paragraphs 83-85, multiplexor circuitry 11, 12 and 13 provides operands to the FMA unit 15. In contrast, Oberman at FIG. 6 uses multiplexers 632, 634, and 636 as each providing operands to special number detection circuits 638, 640 and 642, respectively. Further, amended claim 1 recites three multiplexor circuitries correspond to the three input floating-point operands A, B, C, and correspond to multiple different selectable operations performed by an FMA (Floating- Point-Multiply-Add) unit; and wherein the three multiplexor circuitries respectively output selected operands of the floating-point operands, directly into the corresponding operand-input ports of the FMA unit.
In contrast, Oberman discloses operands A, B and C selected by selection muxes are provided to special number detection circuits, where each special number detection circuit generates a special number signal (Oberman, paragraph 97).”
Examiner respectfully disagrees. Examiner does not rely on Oberman alone outputting data from muxes directly to an FMA unit. Examiner explains how the combination of Montoye in view of Oberman teach muxes outputs going directly to a multiply-add fused unit. See 35 U.S.C. 103 rejection below.
Further, Applicant argues in page 23 of 24 that Afzal does not teach the multi-bit predicate fields recited in claim 11. Applicant specifically argues “Afzal teaches a predicate register comprising a set of binary semaphores or flags, each corresponding to a single bit that is indexed within the predicate register before instruction execution (Afzal, col. 4, lines 40-54). In contrast, the present invention integrates predicate selection and substitution logic directly into the multiply-add data path of a floating point multiple-add operation executing predicate values on lanes of apparatuses to change a flavor of individual lanes, as recited in claim 10 and 11.”
Examiner respectfully disagrees. Examiner does not rely on Afzal to teach the limitations of claim 10. Further, Afzal teaches in Column 4 Lines 47-52 how the predicate register “can be a register with a plurality of 1-bit entries”. Applicant argues Afzal alone does not teach the limitations of claim 11. However, Examiner relies on Montoye in view of Oberman, in view of Ganapathy, in view of Afzal to teach these limitations, and provides motivation to perform these combinations. See 35 U.S.C. 103 rejection below.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “encoding, in an instruction, a select code, the select code controlling the selection of one of the input ports of each of the three multiplexor circuitries, such that the select code corresponds to one selectable operation of the multiple different selectable operations performed by the floating-point multiply-add unit, wherein the multiple different selectable operations are predefined selectable operations performable by the FMA unit” as disclosed in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 28 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 28 recites the limitation “wherein the select code has a numerical value selected from the group consisting of: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,”. There is no disclosure in the original description disclosing 13 different modes consisting values 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12. Closest paragraph describing this is paragraph 0019, which describes select codes comprising values 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Apparatus claims 13, 15-18 and 20 will be addressed before corresponding method claims 1 and 4-7, and corresponding media claim 25.
Claims 1, 4-9, 13, 15-19, 20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over R. K. Montoye in NPL: “Design of the IBM RISC System/6000 floating-point execution unit” (cited in 892 Notice of References Cited on 04/03/2025), in view of Oberman et al. (U.S. Patent Application Publication US 20090150654 A1), hereinafter “Oberman”.
Regarding Claim 13, Montoye teaches:
An apparatus for performing a floating-point multiply-add operation of a form A*B+C on at least one multiply-add unit with a method according to claim 1 (Fig. 3, e.g., shows multiply-add fused unit pipeline, which performs A*B+C), which comprises:
three input floating-point operands A, B, C, (Fig. 3) …
Montoye does not teach:
… wherein at least one of the floating- point operands A, B, C is provided by a substitution logic, being configured to be separately configurable to substitute the operand A, B, C by the at least one value of the
predefined operand value set to be propagated to at least one output port of the substitution logic, wherein the substitution logic is configured as a multiplexor circuitry, wherein at least one of the three floating-point operands A, B, C is provided by the multiplexor circuitry respectively, and the multiplexor circuitry comprising;
a first input port for the respective floating-point operand A, B, C;
at least a second input port for at least one value of a predefined operand value set; and
at least one output port assigned to the corresponding first and second input ports, wherein the multiplexor circuitry is configured to be separately configurable to select one of the input ports to be propagated to the at least one output port;
wherein three multiplexor circuitries correspond to the three input floating-point operands A, B, C, and correspond to multiple different selectable operations performed by an FMA (Floating-Point-Multiply-Add) unit; and
wherein the three multiplexor circuitries respectively output selected operands of the floating-point operands, directly into the three input floating-point operands A, B, C, of the FMA unit, respectively; and
a select code encoded in an instruction, the select code controlling the selection of one of the input ports of each of the three multiplexor circuitries, such that the select code corresponds to one selectable operation of the multiple different selectable operations performed by the floating-point multiply-add unit, wherein the multiple different selectable operations are predefined selectable operations performable by the FMA unit.
However, Oberman teaches:
wherein at least one of the floating-point operands A, B, C is provided by a substitution logic (Fig. 5, e.g., shows double-precision fused multiply-add (DFMA) unit 320 which includes Operand Preparation 514, Fig. 6, e.g., Shows Operand Preparation 514 using Multiplexers 632, 634, 636, one for each input A, B, and C. Each multiplexer has inputs A or B or C other values for which they can be substituted (0,1, FP32 Extract Output...)), being configured to be separately configurable to substitute the operand A, B, C by the at least one value of the predefined operand value set to be propagated to at least one output port of the substitution logic (Fig. 5, Fig. 6 e.g., Values can be substituted separately by each multiplexer, and selected value is outputted, ¶0094-0096), wherein the substitution logic is configured as a multiplexor circuitry (Fig. 6, ¶0094-0096), wherein at least one of the three floating-point operands A, B, C is provided by the multiplexor circuitry respectively (Fig. 6, e.g., Shows Operand Preparation 514 using Multiplexers 632, 634, 636, one for each input A, B, and C. Each multiplexer has inputs A or B or C other values for which they can be substituted (0,1, FP32 Extract Output...). Values can be substituted separately by each multiplexer. Selected value is outputted; ¶0094-0096), and the multiplexor circuitry comprising;
a first input port for the respective floating-point operand A, B, C (Fig. 6; ¶0094-0096);
at least a second input port for at least one value of a predefined operand value set (Fig. 6, e.g., has at least one constant value (predefined operand value set) 0 and/or 1; ¶0094-0096); and
at least one output port assigned to the corresponding first and second input ports (Fig. 6, e.g., shows first and second inputs (either one of the 3/4 inputs) and output port of the multiplexer to transfer selected data to special number detection circuits; ¶0097), wherein the multiplexor circuitry is configured to be separately configurable to select one of the input ports to be propagated to the at least one output port (Fig. 6; ¶0094-0096, e.g., each paragraph talks about each multiplexer process for each input A, B, C);
wherein three multiplexor circuitries correspond to the three input floating-point operands A, B, C (¶0094, e.g., Operand selection muxes 632, 634, 636 respond to signals from control logic 630 to select operands A, B and C; Fig. 6), and correspond to multiple different selectable operations performed by an FMA (Floating-Point-Multiply-Add) unit (Fig. 6; ¶0094, e.g., multiplexer could output operands A, B, C, or constant values 1 or 0; Fig. 8, e.g., Mantissa path (FMA) could compute A*B+C, A+C, B+C, or other operations depending on the output of muxes 632, 634, 636 (multiplexor circuitries)); …
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the three operand selection muxes 632, 634, 636 and control logic 630 to control muxes as taught by Oberman with the multiply-add fused unit as taught by Montoye. One would have been motivated to combine these references because both references disclose floating-point multiply-add operations, and Oberman enhances the model of Montoye by allowing for the configuration of the MAF unit to operate in different modes according to the selection of the muxes. See Oberman: ¶0094-0096. Combination would cause for the muxes to be placed before the MAF unit, allowing for selection of operands before they are inputted. Hence, Combination of Montoye in view of Oberman teach the limitation “wherein the three multiplexor circuitries respectively output selected operands of the floating-point operands, directly into the three input floating-point operands A, B, C, of the FMA unit, respectively”
Additionally, Oberman teaches:
a select code encoded in an instruction (¶0058, e.g., fetch and dispatch unit 302 obtains instructions and decodes them to dispatch them as opcodes (select codes)), the select code controlling the selection of one of the input ports of each of the three multiplexor circuitries (Fig. 5, e.g., Control Block receives opcode (select code) and outputs OPCTL; ¶0090, e.g., Absolute value/negation blocks 618, 620, 622 receive OPCTL, and output data to A/B comparison circuit 624, fp32 extraction circuit 626, unsigned/signed (U/S) extraction circuit 628, which output data to control logic 630. Control logic 630 selects operands to be outputted by multiplexers 632, 634, 636), such that the select code corresponds to one selectable operation of the multiple different selectable operations performed by the floating-point multiply-add unit (Fig. 5, e.g., control block receives opcode 508; ¶0078, e.g., opcode indicates operation to be performed by the DFMA unit, where operations are shown in Fig. 4; Fig. 4, e.g., shows double-precision arithmetic operations selectable by opcode (select code), hence, multiplexers 632, 634, and 636 select appropriate operands for the operation), wherein the multiple different selectable operations are predefined selectable operations performable by the FMA unit (Fig. 4, e.g., shows double-precision arithmetic operations selectable by opcode (select code)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the fetch and dispatch unit 302 receiving instructions and decoding them to dispatch them as opcodes, and the control block to receive these opcodes as taught by Oberman with multiply-add fused unit as taught by Montoye. One would have been motivated to combine these references because both references disclose floating-point multiply-add operations, and Oberman enhances the model of Montoye by allowing the multiply-add fused unit to “receive the opcodes and associated operands and perform the specified operation on the operands.” (Oberman: ¶0059)
Regarding Claim 15, Montoye in view of Oberman teach:
The apparatus according to claim 13, wherein the floating-point multiply-add operation is triggered by an instruction with a selection code parameter to specify a configuration of the at least one substitution logic (¶0094, Control logic 630 provides control signal (instruction) that holds a parameter (selection code parameter) to select the value for what each operand will be substituted for; Fig. 6).
Regarding Claim 16, Montoye in view of Oberman teach:
The apparatus according to claim 13, wherein the predefined operand value set at least is configured as a set comprising values, selected from a group consisting of: -0, +0, +1, -1 (Oberman: Fig. 6, e.g., predefined operands 0 and/or 1 in multiplexers; ¶0068, e.g., Zero can have either sign; thus both positive and negative zero are allowed; Montoye: Page 60, Second column, Second paragraph, e.g., MAF unit performs floating point, hence a “1” could be positive or negative).
The motivation to combine provided with respect to claim 13 applies equally to claim 16.
Regarding Claim 17, Montoye in view of Oberman teach:
The apparatus according to claim 15, wherein the selection code parameter being used for selecting one of the input ports to be propagated to the at least one output port is at least one of a set corresponding to selectable operations comprising -0, C, A, A+C, B, B+C, A*B, A*B+C, C+1, 1, -A+C, -B+C (Oberman: Fig. 6; ¶0094, e.g., multiplexer would output operands A, B, and C; Montoye: Fig. 3 e.g., Could compute A*B+C).
The motivation to combine provided with respect to claim 13 applies equally to claim 17.
Regarding Claim 18, Montoye in view of Oberman teach:
The apparatus according to claim 13, comprising at least a multiply-add unit with three inputs (Montoye: Fig. 3, e.g., shows MAF unit receiving operands A, B, and C),
wherein at least one input is received from an output of the at least one substitution logic (Montoye: Fig. 3, e.g., shows MAF unit receiving operands A, B, and C; Combination of Montoye in view of Oberman would cause for MAF unit to receive outputs from operand selection muxes (substitution logic)).
The motivation to combine provided with respect to claim 13 applies equally to claim 18.
Regarding Claim 20, Montoye in view of Oberman teach:
The apparatus according to claim 13, being configured for performing a floating-point multiply-multiply-add operation of a form A0*B0+A1*B1+C ((Montoye: Fig. 3, e.g., MAF unit computes A*B; Page 60, Section “Floating-point operations”, e.g., each operand is made out of 52 bit mantissas, hence computing Am0*Bm0, Am1*Bm1... Am51*Bm51. Product is inputted in Adder, where A*B is added to C operand, hence being in the format A0*B0+A1*B1+C), with input floating-point operands comprising A0, A1, B0, B1, C (Montoye: Fig. 3, e.g., shows operands A, B, and C; Page 60, Section “Floating-point operations”, e.g., Each operands contains 52-bit mantissas).
With regards to Claim 1, 4-7, they are directed to a method practiced by the apparatus of claims 13, 15-17 and 20, respectively. They are rejected for the same reasons.
With regards to Claim 25, this is a media version of the claimed method above (claim 1 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Regarding Claim 8, Montoye teaches:
The method according to claim 1 … [and] a register file with at least two read ports and one write port (Montoye: Second Column, Second paragraph, e.g., register file has a five-port bandwidth) …
Montoye does not specifically teach:
The method according to claim 1, further comprising: providing floating-point operands by a register file as input operands and receiving an output from the substitution logic … , in particular providing the input operands being triggered by the instruction with a selection code parameter.
However, Oberman teaches:
The method according to claim 1, further comprising: providing floating-point operands by a register file as input operands (Fig. 3, e.g., Register File 324 outputs operands as input for issue unit 304, then to DFMA Unit 320; ¶0010, e.g., Operands are double-precision operands (Floating point operands)) and receiving an output from the substitution logic by a register file (Fig. 3, e.g., Register File 324 receives output from double-precision fused multiply-add (DFMA) unit 320; Fig. 5, e.g., DFMA unit 320 contains Operand Preparation unit 514; Fig. 6, e.g., Operand Preparation unit 514 contains Multiplexers (substitution logic)) with [a] read port and one write port (¶0059, e.g., Register file has to have at least one write port to receive data), in particular providing the input operands being triggered by the instruction with a selection code parameter (¶0058, e.g., Issue unit issues the instruction by using opcode (selection code parameter) to determine what unit the operands should be provided as input; Fig. 3).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the register file to provide operands as taught by Oberman with the multiply-add fused unit as taught by Montoye. One would have been motivated to combine these references because both references disclose floating-point multiply-add operations, and Oberman enhances the model of Montoye because a register file allows for the providing of input operands to the MAF unit. See Oberman: ¶0058.
Regarding Claim 19, Montoye in view of Oberman teach:
The apparatus according to claim 13, comprising a register file with at least two read ports and one write port (Montoye: Second Column, Second paragraph, e.g., register file has a five-port bandwidth; Oberman: ¶0059, e.g., Register file has to have at least one write port to receive data), wherein the register file is configured for providing input operands (Oberman: ¶0058, e.g., Operands are provided by the register file; Fig. 3, e.g., register file outputs operand to issue unit 304, then to DFMA Unit 320) and is configured for receiving an output from the multiply-add unit (Oberman: Fig. 3, e.g., Register File 324 receives output from double-precision fused multiply-add (DFMA) unit 320), in particular providing the input operands being triggered by the instruction with a selection code parameter (Oberman: ¶0058, e.g., Issue unit issues the instruction by using opcode (selection code parameter) to determine what unit the operands should be provided as input; Fig. 3).
The motivation to combine provided with respect to claim 8 applies equally to claim 19.
Regarding Claim 9, Montoye teaches:
The method according to claim 1, further comprising: … , wherein [the] multiply-add unit comprises at least one local register file for an intermediate storage of data values (Montoye: Fig. 3, e.g., shows register file (local register file) inside MAF unit) …
Montoye does not teach:
The method according to claim 1, further comprising: when a processor comprises an interconnected mesh of apparatuses with at least one multiply-add unit each, … , triggering the floating-point multiply-add operation by an instruction with a selection code parameter to specify a configuration of the substitution logic.
However Oberman teaches:
The method according to claim 1, further comprising: when a processor comprises an interconnected mesh of apparatuses with at least one multiply-add unit each (¶0057, e.g., Other functional units include single precision multiplication and addition; Fig. 3, e.g., DFMA Unit 320 and Functional units 322(1) and 322(N) are connected together (mesh of apparatuses)), … triggering the floating-point multiply-add operation by an instruction with a selection code parameter to specify a configuration of the substitution logic (¶0094, e.g., Control logic 630 provides control signal (instruction) that holds a parameter (selection code parameter) to select the value for what each operand will be substituted for).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the parallel DFMA units as taught by Oberman with the multiply-add fused unit as taught by Montoye. One would have been motivated to combine these references because both references disclose floating-point multiply-add operations, and Oberman enhances the model of Montoye by allowing for parallelization of multiple multiply-add computations.
Regarding Claim 26, Montoye in view of Oberman teach:
The method of claim 1, wherein the selectable operation is selected from the group consisting of: -0, C, A, A+C, B, B+C, A*B, A*B+C, C+1, 1, -A+C, and -B+C (Fig. 4, e.g., shows operations A+C, A*B, and A*B+C; ¶0068, e.g., negative zeros are allowed (-0); ¶0094, e.g., mux 632 selects 0 for DADD operation (B+C); ¶0090, e.g., operations on fig. 4 may also use negative operands (-A+C; -B+C); ¶0073, e.g., DMAX returns larger of two operands (A; B). DSET returns Boolean value (1); ¶0170, e.g., mux 363 selects operand C while mux 632 and mux 634 select 0 on each operand).
Montoye in view of Oberman do not teach:
wherein the selectable operation is selected from the group consisting of: … C+1 …
However, Finchelstein teaches a comparator bank 310 that detects values of operands A and B, and causes for an adder 335 to output the result of operation C+1. Finchelstein explains “If operand c has non-zero value, comparator bank 310 gates off multiplier array 310 and directs operand a or operand b (both have value 1.0) to the output of multiplexer 345 in step 526. Comparator bank 310 further directs the output of adder 335 to the output of multiplexer 350 to generate a final result 365 of (c+1) in step 526.” (Finchelstein: ¶0056)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the A/B comparison circuit taught by Oberman to also determine if operands A and B are equal to 1 as taught by Finchelstein. One would have been motivated to combine these references because both references disclose fused multiply accumulate operations, and Finchelstein enhances the model of Montoye in view of Oberman because “improved performance can be realized by detecting when elementary operands are applied to the arithmetic processing element 300 and simplifying the math operations accordingly” (Finchelstein: ¶0062)
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Montoye in view of Oberman, further in view of Ganapathy et al. (U.S. Patent Application Publication No.: US 20030018881 A1), hereinafter “Ganapathy”.
Regarding Claim 10, Montoye teaches the method of claim 1. Montoye does not teach:
when a processor comprises a single-instruction-multiple-data device with
multiple apparatuses with at least one multiply-add unit each, wherein providing predicate values per apparatus by a predicate register is specified by an instruction, selecting an execution of a floating-point multiply-add operation for each apparatus.
However, Oberman teaches:
The method according to claim 1, further comprising: when a processor comprises a single-instruction-multiple-data device (¶0061, e.g., Fetch and dispatch unit 302 and issue unit 304 may implement SIMD) with multiple apparatuses with at least one multiply-add unit each (¶0057, e.g., Other functional units include single precision multiplication and addition (multiply-add unit); Fig. 3, e.g., DFMA Unit 320 and Functional units 322(1) and 322(N) are connected together (multiple apparatuses)), … selecting an execution of a floating-point multiply-add operation for each apparatus (¶0058, e.g., Execution is selected depending on the unit selected to process the operands).
The motivation to combine provided with respect to claim 9 applies equally to claim 10.
Montoye in view of Oberman do not teach:
wherein providing predicate values per apparatus by a predicate register is specified by an instruction,
However, Ganapathy teaches:
wherein providing predicate values per apparatus by a predicate register is specified by an instruction (¶0048, e.g., Predicate registers are within RISC control unit 302. Instruction execution changes based on predicate register contents (predicate values); (¶0078, e.g., Predecoding 702 contains RISC control unit 302 that provides preliminary signals (based on predicate values) to final decoders 704A-704N to be decoded for them to select what component (apparatus) to be used for the given instruction (select execution); Fig. 7),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the predecoding block containing predicate registers with predicate values as taught by Ganapathy with the Fetch and dispatch unit to decode instructions as taught by Montoye in view of Oberman. One would have been motivated to combine these references because both references disclose processing of instructions, and Ganapathy enhances the model of Montoye in view Oberman by providing a source of instructions to be able to select what unit/apparatus to use for execution.
With regards to Claim 21, this is similar to the claimed apparatus above (claims 10, 13 and 15), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Apparatus claims 23 and 24 will be addressed before corresponding method claims 11 and 12.
Claims 11, 12, 23, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Montoye in view of Oberman, in view of Ganapathy, further in view of Afzal (U.S. Patent No.: US 11520561 B1), hereinafter “Afzal”.
Regarding Claim 23, Montoye in view of Oberman in view of Ganapathy also teaches:
The processor according to claim 21, wherein the predicate register comprises … the predicate values (Ganapathy:¶0048; ¶0078; Fig. 7), … to change a flavor of individual lanes based on the respective predicates for each lane (Oberman: ¶0058, e.g., Instructions come from an instruction store that is not shown [predicate register from Ganapathy], then decoded by fetch and dispatch unit. Issue unit sends operands (flavor) to each unit (Lane); Ganapathy: ¶0048, e.g., Instruction execution changes based on predicate register contents (predicate values)).
Montoye in view of Oberman in view of Ganapathy does not teach:
… comprises multi-bit predicate fields …
wherein the predicate-fields are enabled by the instructions for executing the predicate values on lanes of apparatuses
However, Afzal teaches:
… comprises multi-bit predicate fields … (Column 4 Lines 47-52, e.g., Predicate registers can have a plurality of 1-bit entries (multi-bit predicate fields))
wherein the predicate-fields are enabled by the instructions for executing the predicate values on lanes of apparatuses (Column 4 Lines 27 – 35, e.g., A component (apparatus) is selected based on the instruction; Column 4 Lines 54 – 58, e.g., Instructions list a predicate bit (predicate value) to execute the instruction)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the predicate registers containing multi-bit predicate fields as taught by Afzal with the predicate register as taught by Montoye in view of Oberman in view of Ganapathy. One would have been motivated to combine these references because both references disclose predicate registers processing instructions for execution, and Afzal enhances the model of Montoye in view of Oberman in view of Ganapathy by allowing for predicate registers to have multiple bit entries for accurate processing of instructions.
Regarding Claim 24, Montoye in view of Oberman in view of Ganapathy
The processor according to claim 21, wherein at least one multiply-add unit is configured to substitute at least one operand of an internal operation by at least one value of a predefined operand value set (Montoye: Fig. 3, e.g., shows MAF unit (internal operation); Oberman: Fig. 6, e.g., shows operand selection muxes) the operation being triggered by a predicate value specified and decoded into a selection code parameter by a predicate logic based on predicate values… (Oberman: ¶0058, e.g., Fetch and Dispatch unit decodes instructions [from the predicate register taught by Ganapathy] into opcodes (selection code parameter); Ganapathy: ¶0048, e.g., Predicate register triggers operation (instruction execution) based on its contents (predicate value)), on results of previous instructions (Oberman: ¶0058, e.g., Issue unit 304 provides previous instructions.) and on an information about dynamic or static use (Oberman: Fig. 6, e.g., Control Unit 630 provides signal that determines if a constant number (static) or the operand (dynamic) will be used; ¶0094).
Montoye in view of Oberman in view of Ganapathy does not teach:
provided by a load-store unit,
However, Afzal teaches:
provided by a load-store unit (Column 5 Lines 28 – 38, e.g., Control sequencer 112 provides LOAD and STORE instructions to the DME to be executed (Load and Store Unit). LOAD and STORE instructions can set a binary semaphore (predicate value) in the predicate register),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the Control sequencer and the DME for providing predicate values as taught by Afzal with the predicate registers as taught by Montoye in view of Oberman in view of Ganapathy. One would have been motivated to combine these references because both references disclose predicate registers processing instructions for execution, and Afzal enhances the model of Montoye in view of Oberman in view of Ganapathy by allowing for predicate registers to have multiple bit entries for accurate processing of instructions.
With regards to Claim 11, this is a method version of the claimed processor above (claim 23 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
With regards to Claim 12, this is a method version of the claimed processor above (claim 24 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Montoye in view of Oberman, further in view of Finchelstein et al. (U.S. Patent Application Publication No.: US 20150095394 A1), hereinafter “Finchelstein”.
Regarding Claim 26, Montoye in view of Oberman teach:
The method of claim 1, wherein the selectable operation is selected from the group consisting of: -0, C, A, A+C, B, B+C, A*B, A*B+C, C+1, 1, -A+C, and -B+C (Fig. 4, e.g., shows operations A+C, A*B, and A*B+C; ¶0068, e.g., negative zeros are allowed (-0); ¶0094, e.g., mux 632 selects 0 for DADD operation (B+C); ¶0090, e.g., operations on fig. 4 may also use negative operands (-A+C; -B+C); ¶0073, e.g., DMAX returns larger of two operands (A; B). DSET returns Boolean value (1); ¶0170, e.g., mux 363 selects operand C while mux 632 and mux 634 select 0 on each operand).
Montoye in view of Oberman do not teach:
wherein the selectable operation is selected from the group consisting of: … C+1 …
However, Finchelstein teaches a comparator bank 310 that detects values of operands A and B, and causes for an adder 335 to output the result of operation C+1. Finchelstein explains “If operand c has non-zero value, comparator bank 310 gates off multiplier array 310 and directs operand a or operand b (both have value 1.0) to the output of multiplexer 345 in step 526. Comparator bank 310 further directs the output of adder 335 to the output of multiplexer 350 to generate a final result 365 of (c+1) in step 526.” (Finchelstein: ¶0056)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the A/B comparison circuit taught by Oberman to also determine if operands A and B are equal to 1 as taught by Finchelstein. One would have been motivated to combine these references because both references disclose fused multiply accumulate operations, and Finchelstein enhances the model of Montoye in view of Oberman because “improved performance can be realized by detecting when elementary operands are applied to the arithmetic processing element 300 and simplifying the math operations accordingly” (Finchelstein: ¶0062)
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Montoye in view of Oberman in view of Finchelstein, further in view of Elsevier Inc. in NPL “Microcomputer Instrumentation and Control” (www.sciencedirect.com/topics/engineering/operation-code?__cf_chl_tk=wOnoQ3PuFpsyta6ntjVV11OLwj1GiSrwDRApqdpnqHI-1784925435-1.0.1.1-SZihth3aMI7lCHyfg7ksZg7TfmTzja99UlmFM1BuoqI), hereinafter “Elsevier”.
Regarding Claim 27, Montoye in view of Oberman teach:
The method of claim 1 wherein the select code … corresponds to a selectable operation selected from a group consisting of: -0, C, A, A+C, B, B+C, A*B, A*B+C, C+1, 1, -A+C, and -B+C (Fig. 4, e.g., shows operations A+C, A*B, and A*B+C; ¶0068, e.g., negative zeros are allowed (-0); ¶0094, e.g., mux 632 selects 0 for DADD operation (B+C); ¶0090, e.g., operations on fig. 4 may also use negative operands (-A+C; -B+C); ¶0073, e.g., DMAX returns larger of two operands (A; B). DSET returns Boolean value (1); ¶0170, e.g., mux 363 selects operand C while mux 632 and mux 634 select 0 on each operand).
Montoye in view of Oberman do not teach:
wherein the select code has a numerical value, and the numerical value corresponds to a selectable operation selected from a group consisting of: … C+1 …
However, Finchelstein teaches a comparator bank 310 that detects values of operands A and B, and causes for an adder 335 to output the result of operation C+1. Finchelstein explains “If operand c has non-zero value, comparator bank 310 gates off multiplier array 310 and directs operand a or operand b (both have value 1.0) to the output of multiplexer 345 in step 526. Comparator bank 310 further directs the output of adder 335 to the output of multiplexer 350 to generate a final result 365 of (c+1) in step 526.” (Finchelstein: ¶0056)
The motivation to combine provided with respect to claim 26 applies equally to claim 27.
Montoye in view of Oberman in view of Finchelstein do not disclose how the opcode is represented.
However, Elsevier teaches op codes being represented by numerical values. Elsevier explains “The instruction register has a part that contains the numeric op codes. A decoder determines from the op codes the operation to be executed, and a data register controls the flow of data inside the CPU as a result of the op code instructions” (Elsevier: Page 141, Section “Operation Codes” second paragraph).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the numeric opcodes as taught by Elsevier with the opcode to select operations as taught by Oberman. One would have been motivated to combine these references because both references disclose Operation codes to represent operations, and Elsevier enhances the model of Montoye in view of Oberman in view of Finchelstein by properly representing them using numerical values.
Allowable Subject Matter
Claim 28 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Oberman teaches a DFMA unit 320 that performs various operations, including multiplication, addition, and fused multiplication and addition. DFMA unit receives a decoded opcode that controls the operation to be performed, and further teaches using three muxes to select operands for the operation performed. See Oberman: Figs. 4-6 and corresponding descriptions. Oberman does not teach or suggest using numerical opcodes numbered from 0-11 to represent each different selectable operation. Instead, Oberman teaches opcodes selecting from arithmetic operations DADD, DMUL, and DFMA, Comparison operations DMAX, DMIN, and DSET, and Format Conversion and Rounding operations D2F, F2D, D2I, I2D, D2D. Therefore, Oberman does not teach or suggest the combination of claim 28 including the limitations “The method of claim 1, wherein the select code has a numerical value selected from the group consisting of: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, which correspond to a selectable operation selected from a group consisting of: -0, C, A, A+C, B, B+C, A*B, A*B+C, C+1, 1, -A+C, -B+C.”
Montoye teaches MAF unit that performs a multiplication and addition operations of operands A, B, and C. Montoye further teaches using muxes on operands A and C to select the operand, or a feedback normalized added output. See Montoye: Fig. 3 and corresponding description. Montoye does not teach or suggest using numerical opcodes numbered from 0-11 to represent each different selectable operation. Instead, Montoye teaches selecting data using muxes depending on the cycle of the multiply-accumulate operation. Therefore, Montoye does not teach or suggest the combination of claim 28 including the limitations “The method of claim 1, wherein the select code has a numerical value selected from the group consisting of: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, which correspond to a selectable operation selected from a group consisting of: -0, C, A, A+C, B, B+C, A*B, A*B+C, C+1, 1, -A+C, -B+C.”
Finchelstein teaches method steps for performing simplified arithmetic operations upon detecting elementary valued operands. Finchelstein uses a comparator bank to determine the operand values, and instructs the operation to be performed based on the combination of values of operators. See Figs. 3 and 5, and corresponding description. Finchelstein does not teach or suggest using numerical opcodes numbered from 0-11 to represent each different selectable operation. Instead, Finchelstein teaches performing operations based on the result of the comparator bank. Therefore, Finchelstein does not teach or suggest the combination of claim 28 including the limitations “The method of claim 1, wherein the select code has a numerical value selected from the group consisting of: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, which correspond to a selectable operation selected from a group consisting of: -0, C, A, A+C, B, B+C, A*B, A*B+C, C+1, 1, -A+C, -B+C.”
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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